TWI630691B - 封裝結構及形成方法 - Google Patents

封裝結構及形成方法 Download PDF

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Publication number
TWI630691B
TWI630691B TW103145157A TW103145157A TWI630691B TW I630691 B TWI630691 B TW I630691B TW 103145157 A TW103145157 A TW 103145157A TW 103145157 A TW103145157 A TW 103145157A TW I630691 B TWI630691 B TW I630691B
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Taiwan
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conductive member
conductive
semiconductor substrate
layer
under bump
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TW103145157A
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TW201539684A (zh
Inventor
李立國
劉永盛
劉宜臻
賴怡仁
陳俊仁
鄭錫圭
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台灣積體電路製造股份有限公司
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    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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Abstract

提供了封裝結構及製作方法。封裝結構包括半導體基底及半導體基底上之第一導電構件。封裝結構還包括基底及基底上之第二導電構件。第二導電構件透過接合結構而與第一導電構件接合。封裝結構更包括圍繞接合結構之保護材料，且保護材料直接接觸第一導電構件之側表面。

Description

封裝結構及形成方法
本揭露書係有關於封裝結構及其形成方法，且特別是有關於具有兩接合基底之封裝結構。
半導體元件用於多種電子應用，例如個人電腦、手機、數位相機、及其他電子設備。半導體元件的製作涉及於半導體基底上相繼沉積絕緣或介電層、導電層、及半導體層，及使用微影及蝕刻製程將各種材料層圖案化，而於半導體基底上形成電路元件及構件。
藉著最小特徵尺寸的持續縮小，半導體工業持續增進各種電子構件(例如，電晶體、二極體、電阻元件、電容元件等)的整合密度，其使得更多的元件能夠整合進給定之區域中。輸入及輸出(I/O)的連接數目顯著地增加。發展了更小的封裝結構(其使用較小區域或較低的高度)來封裝半導體元件。
已發展新穎的封裝技術來增進半導體元件的密度及功能。半導體元件之相對新穎封裝技術面臨著製作上之挑戰。
本揭露書提供一種封裝結構，包括：一半導體基底；一第一導電構件，於該半導體基底之上；一基底；一第二導電構件，於該基底上，其中該第二導電構件透過一接合結構 而與該第一導電構件接合；以及一保護材料，圍繞該接合結構，其中該保護材料直接接觸該第一導電構件之一側表面。
本揭露書提供一種封裝結構，包括：一半導體基底；一第一導電構件，於該半導體基底之上，其中無鈍化層於該第一導電構件上；一基底；以及一第二導電構件，於該基底上，其中該第二導電構件透過一接合結構而與該第一導電構件接合。
本揭露書提供一種封裝結構的形成方法，包括：於一半導體基底上形成一第一導電構件；於一基底上形成一第二導電構件；以及透過一接合結構而將該第一導電構件與該第二導電構件接合，其中在形成該接合結構之前，無鈍化層形成於該第一導電構件上。
100‧‧‧半導體基底
102‧‧‧介電層
104‧‧‧導電構件
105‧‧‧側表面
106‧‧‧凸塊下金屬化層
106a‧‧‧凸塊下金屬化構件
108‧‧‧遮罩層
110‧‧‧開口
112‧‧‧導電柱
114‧‧‧焊料層
114a‧‧‧焊料蓋
114b‧‧‧焊料凸塊
115‧‧‧接合結構
116‧‧‧基底
118‧‧‧導電構件
120‧‧‧保護材料
214b‧‧‧焊料凸塊
215‧‧‧接合結構
304‧‧‧導電構件
305‧‧‧側表面
306a‧‧‧凸塊下金屬化構件
312‧‧‧導電柱
314b‧‧‧焊料凸塊
315‧‧‧接合結構
W1、W1’、W2、W2’、W3‧‧‧寬度
第1A-1I圖顯示根據一些實施例之封裝結構的製程剖面圖。
第2圖顯示根據一些實施例之封裝結構的剖面圖。
第3圖顯示根據一些實施例之封裝結構的剖面圖。
以下的揭露內容提供許多不同的實施例或範例，以實施本案的不同特徵。而本揭露書以下的揭露內容是敘述各個構件及其排列方式的特定範例，以求簡化說明。當然，這些特定的範例並非用以限定。例如，若是本揭露書以下的內容敘述了將一第一特徵形成於一第二特徵之上或上方，即表示其包 含了所形成的上述第一特徵與上述第二特徵是直接接觸的實施例，亦包含了尚可將附加的特徵形成於上述第一特徵與上述第二特徵之間，而使上述第一特徵與上述第二特徵可能未直接接觸的實施例。再者，在以下敘述提及在第二製程前進行第一製程，可包括第二製程於第一製程之後立刻進行之實施例，且亦可包括附加製程於第一製程與第二製程之間進行的實施例。另外，本揭露書中不同範例可能使用重複的參考符號及/或標記。這些重複係為了簡化與清晰的目的，並非用以限定各個實施例及/或所述外觀結構之間的關係。
再者，為了方便描述圖式中一元件或特徵部件與另一(複數)元件或(複數)特徵部件的關係，可使用空間相關用語，例如“在...之下”、“下方”、“較下部”、“上方”、“較上部”及類似的用語等。除了圖式所繪示的方位之外，空間相關用語用以涵蓋使用或操作中的裝置的不同方位。所述裝置也可被另外定位(例如，旋轉90度或者位於其他方位)，並對應地解讀所使用的空間相關用語的描述。
第1A-1I圖顯示根據一些實施例之封裝結構的製程剖面圖。請參照第1A圖，提供半導體基底100。在一些實施例中，半導體基底100為半導體晶圓(例如，矽晶圓)或半導體晶圓之一部分。在一些實施例中，半導體基底100包括元素半導體，其包括單晶、多晶、或非晶結構之矽或鍺。在一些其他實施例中，半導體基底100包括化合物半導體，例如碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、合金半導體(例如，SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP)、或前述之組合。 在一些實施例中，半導體基底100包括多層半導體、絕緣層上覆半導體(SOI)(例如，絕緣層上覆矽或絕緣層上覆鍺)、或前述之組合。
在一些實施例中，於半導體基底100中形成隔離結構(未顯示)。隔離結構可定義並隔離形成於半導體基底100中的各種元件。隔離結構包括淺溝槽隔離(shallow trench isolation，STI)結構、局部矽氧化(local oxidation of silicon，LOCOS)結構、其他適合的隔離結構、或前述之組合。
可形成於半導體基底100中之各種元件例如包括電晶體(例如，金氧半場效電晶體(MOSFET)、互補式金氧半場效電晶體(CMOS)、雙極性接面電晶體(BJT)、高電壓電晶體、高頻率電晶體、P通道及/或N通道場效電晶體(PFETs/NFETs)等等)、二極體、其他可應用元件、或前述之組合。
如第1A圖所示，根據一些實施例，於半導體基底100上形成介電層102。在一些實施例中，許多導電構件(conductive features)係形成於介電層102中。在一些實施例中，導電構件包括多個水平內連線，(例如導線)及多個垂直內連線(例如，導電介層物(conductive vias)或導電接觸(conductive contacts))。在一些實施例中，介電層102為多層介電層之堆疊。形成於介電層102中之導電構件形成了形成在半導體基底100中或上之元件構件(device elements)(未顯示)與介電層102上之導電線路之間的電性連接。元件構件可為形成於半導體基底100中或上之摻雜區。或者，元件構件可為形成於半導體基底100上或中之閘極電極。可於介電層中形成多個導電線路及導 電介層物以形成連至元件構件之導電路徑。介電層102及導電構件可共同形成半導體基底100上之內連線結構。
如第1A圖所示，根據一些實施例，於半導體基底100上之介電層102上形成導電構件(conductive feature)104。在一些實施例中，導電構件104包括導電線路(conductive trace)及導電墊(conductive pad)，它們彼此電性連接。在一些實施例中，導電構件104亦指頂金屬層(top metal)。在一些實施例中，導電構件104透過介電層102中之一些導電構件而電性連接至半導體基底100中之其中一元件構件。在一些實施例中，第1A圖顯示導電構件104之導電墊的剖面圖。在一些其他實施例中，第1A圖顯示導電構件104之導電線路的剖面圖。
在一些實施例中，導電構件104係由AlCu、Al、Cu、其他適合的材料、或前述之組合所製成。在一些實施例中，導電構件104係藉由將沉積在介電層102上之導電層圖案化而形成。例如，使用微影製程及蝕刻製程將導電層圖案化，形成出數個導電構件，其包含導電構件104。
在一些實施例中，介電層102係由氧化矽、氮化矽、氮氧化矽、四乙基矽酸鹽氧化物(TEOS oxide)、磷矽酸鹽玻璃(phosphosilicate glass，PSG)、硼磷矽酸鹽玻璃(borophosphosilicate glass，BPSG)、氟化矽氧玻璃(fluorinated silica glass，FSG)、碳摻雜氧化矽、非晶氟化碳、低介電常數材料、其他適合的材料、或前述之組合所製成。在一些實施例中，形成在介電層102中之導電構件由銅、鋁、鎢、鈦、鎳、金、鉑、其他適合的材料、或前述之組合所製成。可進行數道 的沉積、微影、及蝕刻製程以形成介電層102及其中之導電構件。
如第1A圖所示，根據一些實施例，無鈍化層(passivation layer)(例如，氮化矽層、氧化矽層、氮氧化矽層、或其相似物)形成於導電構件104之上。即，在一些實施例中，不形成鈍化層來覆蓋介電層102及導電構件104。在一些實施例中，不需要形成鈍化層所需之沉積及圖案化製程。因此，減少了製作成本與製作時間。
如第1B圖所示，根據一些實施例，於介電層102及導電構件104上沉積凸塊下金屬化(under-bump metallization，UBM)層106。在一些實施例中，凸塊下金屬化層106為單一材料層或多層材料層之堆疊。例如，凸塊下金屬化層106可由Ti、TiW、TiCu、Ni、其他適合的材料、或前述之組合所製成。在一些實施例中，凸塊下金屬化層106包括子材料層(sub-layers)，其例如包括擴散阻障層(diffusion barrier layer)及晶種層(seed layer)。擴散阻障層可由氮化鉭所形成，雖然其亦可由其他材料所形成，例如氮化鈦、鉭、鈦、或其相似物。晶種層可為形成在擴散阻障層上之銅晶種層。晶種層可由銅或許多銅合金之其中之一所形成，銅合金包括銀、鉻、鎳、錫、金、或前述之組合。在一些實施例中，凸塊下金屬化層106係使用物理氣相沉積(physical vapor deposition，PVD)製程、化學氣相沉積(chemical vapor deposition，CVD)製程、電鍍製程、旋塗(spin-on)製程、其他可應用製程、或前述之組合而沉積。
如第1C圖所示，根據一些實施例，於凸塊下金屬 化層106上形成遮罩層108。遮罩層108具有一或更多的開口，其包括開口110。在一些實施例中，開口110暴露導電構件104上之一部分的凸塊下金屬化層106。在一些實施例中，遮罩層108為光阻層。在一些實施例中，遮罩層108可使用微影製程而形成，其涉及一或更多的光罩覆蓋、曝光、烘烤、顯影、及潤濕製程(非需依此順序)。
如第1D圖所示，根據一些實施例，在遮罩層108之開口110所暴露之凸塊下金屬化層106上沉積導電柱(conductive pillar)112。在一些實施例中，導電柱112係由銅(Cu)、金(Au)、鉑(Pt)、鈦(Ti)、鎳(Ni)、鋁(Al)、其他適合的材料、或前述之組合所製成。在一些實施例中，導電柱112係藉著使用電鍍製程、物理氣相沉積製程、化學氣相沉積製程、其他可應用製程、或前述之組合而形成。在一些實施例中，凸塊下金屬化層106亦可用做電鍍晶種層。將適合的導電材料(例如，銅)電鍍在凸塊下金屬化層106上以形成導電柱112。
如第1D圖所示，根據一些實施例，於導電柱112上形成焊料層(solder layer)114。焊料層114包括錫(Sn)且可包含鉛或可不包含鉛(lead free)。在一些實施例中，焊料層114包括錫(Sn)及其他材料，包括鉛(Pb)、銀(Ag)、鉍(Bi)、銅(Cu)、金(Au)、鋁(Al)、砷(As)、鐵(Fe)、鎳(Ni)、銻(Sb)、其他適合的材料、或前述之組合。在一些實施例中，焊料層114係使用電鍍製程或其他可應用製程而形成。在一些實施例中，亦於焊料層114上形成助焊劑材料(flux material)(未顯示)。在一些實施例中，助焊劑材料係混合在焊料層114之中。
之後，如第1E圖所示，根據一些實施例，移除遮罩層108。在一些實施例中，使用剝除製程(stripping process)、灰化製程(ashing process)、其他可應用製程、或前述之組合來移除遮罩層108。
如第1F圖所示，根據一些實施例，將凸塊下金屬化層106圖案化以形成在半導體基底100上之一或更多的凸塊下金屬化構件(UBM elements)。在一些實施例中，凸塊下金屬化構件106a係形成在導電構件104上，如第1F圖所示。在一些實施例中，使用蝕刻製程將凸塊下金屬化層106圖案化。蝕刻製程可包括乾式蝕刻製程、濕式蝕刻製程、或前述之組合。例如，焊料層114及導電柱112可共同用作蝕刻遮罩。在蝕刻製程之後，移除了未被蝕刻遮罩所覆蓋的凸塊下金屬化層106，因而形成一或更多的凸塊下金屬化構件，其包括凸塊下金屬化構件106a。
如第1G圖所示，根據一些實施例，回焊焊料層114以於導電柱112上形成焊料蓋(solder cap)114a。在一些實施例中，在回焊製程之前，於焊料層114上形成助焊劑(未顯示)。在一些實施例中，焊料層係回焊於介於約180℃至約280℃之回焊溫度。在一些其他實施例中，回焊溫度為約220℃至約260℃。
如第1H圖所示，根據一些實施例，提供基底116。在一些實施例中，基底116為有機基底(organic substrate)。在一些其他實施例中，基底116為多材料層電路板(multi-layer circuit board)。在一些實施例中，基底116包括雙馬來醯亞胺-三氮雜苯樹脂(bismaleimide triazine(BT)resin)、FR-4(由帶有 環氧樹脂黏結劑且具有耐火性之編織玻璃纖維布所製成的一種複合材料)、陶瓷、玻璃、塑膠、膠帶、薄膜、或其他適合的支撐材料。在一些其他實施例中，基底116由半導體材料所製成。基底116可由半導體晶圓或一部分的晶圓所製成。在一些其他實施例中，基底116為印刷電路板。在一些實施例中，基底116包括矽、砷化鎵、絕緣層上覆矽(silicon on insulator，SOI)、或其他相似材料。在一些實施例中，基底116還包括被動元件(例如，電阻元件、電容元件、電感元件、及其相似物)或主動元件(例如，電晶體)。在一些實施例中，基底116包括附加的積體電路。基底116可更包括穿基底導電介層物(through substrate vias，TSVs)，而可用作轉接板(interposer)。
在一些實施例中，於基底116上形成一或更多的導電構件，其包括導電構件118，如第1H圖所示。在一些實施例中，導電構件118為導電線路。在一些實施例中，導電構件118係由銅、鋁、金、鉑、鈦、鎳、其他適合的材料、或前述之組合所製成。在一些實施例中，沉積導電層並將之圖案化以形成導電構件118。
如第1H圖所示，根據一些實施例，將顯示於第1G圖之結構與基底116接合以形成封裝結構。在一些實施例中，焊料蓋114a用以與導電構件118接合。因此，於導電柱112與導電構件118之間形成了焊料凸塊114b。在一些實施例中，凸塊下金屬化構件106a、導電柱112、及焊料凸塊114b共同形成接合結構115。半導體基底100與基底116透過接合結構115而彼此接合。在一些實施例中，凸塊下金屬化構件106a與焊料凸塊 114b夾置(sandwich)導電柱112。
在一些實施例中，焊料蓋114a與導電構件118直接接合。在一些其他實施例中，在接合前，於導電構件118上先形成焊料材料(solder material)及/或助焊劑(flux)(未顯示)。在一些實施例中，使用熱壓製程、熱回焊製程、其他可應用製程、或前述之組合而將導電柱112與導電構件118接合在一起。
如第1I圖所示，根據一些實施例，於半導體基底100與基底116之間形成保護材料120。在一些實施例中，保護材料120圍繞接合結構115。保護材料120可用以保護半導體基底100與基底116之間的接合結構115。在一些實施例中，保護材料120完全填充半導體基底100與基底116之間的空間。本揭露書具有許多變化。在一些其他實施例中，未形成保護材料120。
如第1I圖所示，根據一些實施例，保護材料120圍繞導電構件104、接合結構115、及導電構件118。在一些實施例中，保護材料120直接接觸導電構件104、接合結構115、及導電構件118。如第1I圖所示，導電構件104具有側表面105。在一些實施例中，保護材料120直接接觸導電構件104之側表面105。
在一些實施例中，保護材料120包括樹脂材料，例如環氧樹脂(epoxy resin)、酚樹脂(phenol resin)、其他適合的材料、或前述之組合。在一些實施例中，保護材料120包括底膠材料(underfill material)、非導電膠(non-conductive paste，NCP)、或其相似物。在一些實施例中，保護材料120係分配、流進、及/或塗佈於半導體基底100與基底116之間。在一些實 施例中，無鈍化層形成於導電構件104與保護材料120之間。在一些實施例中，無任何的氮化矽層、氧化矽層、或氮氧化矽層形成於導電構件104與保護材料120之間。
如第1I圖所示，導電構件104具有寬度W1、導電柱112具有寬度W2、而導電構件118具有寬度W3。在一些實施例中，寬度W1大於寬度W2。導電構件104寬於導電柱112。本揭露書之實施例不限於此。在一些其他實施例中，導電柱112寬於導電構件104。在一些實施例中，寬度W1與寬度W2之間的差異不太大，以確保無高應力形成於導電構件104與導電柱112之間。在一些實施例中，導電構件104與導電柱112之間的寬度比值(W1/W2)為約0.5至約2。在一些實施例中，寬度W3為約15μm至約40μm。在一些實施例中，寬度W2與寬度W3之間的差異不太大，以確保在接合製程期間及/或之後，無高應力形成於導電構件118與接合結構115之間。在一些實施例中，導電柱112與導電構件118之間的寬度比值(W2/W3)為約0.5至約2。在一些實施例中，導電柱112寬於導電構件118。寬度比值(W2/W3)為約1.01至約2。
在一些實施例中，在形成接合結構115之前，不於半導體基底100上形成鈍化層來覆蓋導電構件104。不需形成鈍化層之沉積與圖案化製程。因此，減少了製作成本與製作時間。
本揭露書實施例具有許多變化。第2圖顯示根據一些實施例之封裝結構的剖面圖。顯示於第2圖之封裝結構類似於顯示於第1I圖之封裝結構。主要的區別在於形成了焊料凸塊 214b以覆蓋導電構件118。形成出了包括凸塊下金屬化構件106a、導電柱112、及焊料凸塊214b之接合結構215。
本揭露書實施例具有許多變化。例如，凸塊下金屬化構件不限於短於其下之導電構件。在一些實施例中，凸塊下金屬化構件寬於其下之導電構件。
第3圖顯示根據一些實施例之封裝結構的剖面圖。如第3圖所示，形成了凸塊下金屬化構件306a，其寬於導電構件304。在一些實施例中，凸塊下金屬化構件306a延伸超出導電構件304。在一些實施例中，凸塊下金屬化構件306a覆蓋導電構件304之側表面305。在一些實施例中，凸塊下金屬化構件306a進一步延伸至導電層102之上。由於凸塊下金屬化構件306a寬於導電構件304，形成於凸塊下金屬化構件306a上之導電柱312亦寬於導電構件304。如第3圖所示，導電柱312之寬度W2’大於導電構件304之寬度W1’。
在一些實施例中，凸塊下金屬化構件306a及導電柱312之材質及製作方法相似於顯示於第1圖中之凸塊下金屬化構件106a及導電柱112之材質及製作方法。例如，藉由調整第1C圖所示開口110的尺寸及/或形狀，可形成具有不同尺寸及/或形狀之凸塊下金屬化構件及導電柱。
如第3圖所示，根據一些實施例，形成焊料凸塊314b以將導電柱312與導電構件118接合。在一些實施例中，焊料凸塊314b之材質與製作方法相似於顯示於第1圖或第2圖中之焊料凸塊114b或214b之材質與製作方法。如第3圖所示，形成了接合結構315(其包括凸塊下金屬化構件306a、導電柱312、 及焊料凸塊314b)以將半導體基底100與基底116接合在一起。
在一些實施例中，保護材料120不直接接觸導電構件304，如第3圖所示。在一些實施例中，一或更多的中間層係形成於導電構件304與保護材料120之間。例如，凸塊下金屬化構件306a介於導電構件304與保護材料120之間。
本揭露書實施例提供封裝結構及封裝結構的形成方法。封裝結構包括兩接合基底，其透過接合結構而彼此接合。接合結構將兩基底上之導電構件(例如，導電墊)連接在一起。無鈍化層形成於導電構件之上。因此，顯著地縮減了製作時間與製作成本。
根據一些實施例，提供了一種封裝結構。封裝結構包括半導體基底及半導體基底上之第一導電構件。封裝結構還包括基底及基底上之第二導電構件。第二導電構件透過接合結構而與第一導電構件接合。封裝結構更包括圍繞接合結構之保護材料，且保護材料直接接觸第一導電構件之側表面。
根據一些實施例，提供了一種封裝結構。封裝結構包括半導體基底及半導體基底上之第一導電構件。無鈍化層於第一導電構件上。封裝結構還包括基底及基底上之第二導電構件。第二導電構件透過接合結構而與第一導電構件接合。
根據一些實施例，提供了一種封裝結構的形成方法。方法包括於半導體基底上形成第一導電構件。方法還包括於基底上形成第二導電構件。方法更包括透過接合結構而將第一導電構件與第二導電構件接合。在形成接合結構之前，無鈍化層形成於第一導電構件上。
以上概略說明了數個實施例的特徵，使所屬技術領域人士對於本揭露書的各種面向可更為容易理解。所屬技術領域人士應瞭解到，本揭露書可輕易作為其它製程或結構的設計或變化的基礎，以進行相同於所述實施例的目的及/或獲得相同的優點。所屬技術領域人士也可理解與上述等同的結構或製程並未脫離本揭露書之精神和保護範圍內，且在不脫離本揭露書之精神和範圍內，可作各種改變、置換、與變化。

Claims (9)

  1. 一種封裝結構，包括：一半導體基底；一介電層，於該半導體基底上；一第一導電構件，於該半導體基底之上，其中無鈍化層於該第一導電構件和該半導體基底上；一基底；一第二導電構件，於該基底上，其中該第二導電構件透過一接合結構而與該第一導電構件接合，且該接合結構包括：一凸塊下金屬化構件，該凸塊下金屬化構件具有一階梯部分直接接觸該第一導電構件之一側面；以及一導電柱，覆蓋該凸塊下金屬化構件，其中該凸塊下金屬化構件的該階梯部分具有一水平部將該導電柱與該介電層隔開；以及一保護材料，圍繞該接合結構，其中該保護材料直接接觸該凸塊下金屬化構件之一側面。
  2. 如申請專利範圍第1項所述之封裝結構，其中該保護材料直接接觸該接合結構，且該第一導電構件之該側面不與該凸塊下金屬化構件之該側面共平面。
  3. 如申請專利範圍第1項所述之封裝結構，其中該第一導電構件窄於該導電柱。
  4. 如申請專利範圍第1項所述之封裝結構，其中該接合結構更包括夾置該導電柱之該凸塊下金屬化構件及一焊料凸塊。
  5. 如申請專利範圍第1項所述之封裝結構，其中該第一導電構件與該保護材料之間不具有鈍化層。
  6. 如申請專利範圍第1項所述之封裝結構，其中該保護材料與該第一導電構件之間不具有任何的氮化矽層、氧化矽層、或氮氧化矽層。
  7. 一種封裝結構，包括：一半導體基底；一介電層，於該半導體基底上一第一導電構件，於該半導體基底之上，其中無鈍化層於該第一導電構件和該半導體基底上；一基底；以及一第二導電構件，於該基底上，其中該第二導電構件透過一接合結構而與該第一導電構件接合，且該接合結構包括：一凸塊下金屬化構件，該凸塊下金屬化構件具有一階梯部分直接接觸該第一導電構件之一側面；以及一導電柱，覆蓋該凸塊下金屬化構件，其中該凸塊下金屬化構件的該階梯部分具有一水平部將該導電柱與該介電層隔開。
  8. 如申請專利範圍第7項所述之封裝結構，更包括一保護材料，圍繞該接合結構，其中該保護材料與該第一導電構件之間無任何的氮化矽層、氧化矽層、或氮氧化矽層。
  9. 一種封裝結構的形成方法，包括：於一半導體基底上形成一介電層； 於該半導體基底上形成一第一導電構件；於一基底上形成一第二導電構件；以及透過一接合結構而將該第一導電構件與該第二導電構件接合，其中在形成該接合結構之前，無鈍化層形成於該第一導電構件和該半導體基底上，且該接合結構之形成包括：形成一凸塊下金屬化構件，該凸塊下金屬化構件具有一階梯部分直接接觸該第一導電構件之一側面；以及形成一導電柱，覆蓋該凸塊下金屬化構件，其中該凸塊下金屬化構件的該階梯部分具有一水平部將該導電柱與該介電層隔開。
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