TW201310584A - 半導體裝置與半導體裝置的形成方法 - Google Patents

半導體裝置與半導體裝置的形成方法 Download PDF

Info

Publication number
TW201310584A
TW201310584A TW100139546A TW100139546A TW201310584A TW 201310584 A TW201310584 A TW 201310584A TW 100139546 A TW100139546 A TW 100139546A TW 100139546 A TW100139546 A TW 100139546A TW 201310584 A TW201310584 A TW 201310584A
Authority
TW
Taiwan
Prior art keywords
layer
bump
forming
package member
electrical connector
Prior art date
Application number
TW100139546A
Other languages
English (en)
Other versions
TWI463609B (zh
Inventor
Sheng-Yu Wu
Tin-Hao Kuo
Chi-Ta Chuang
Chen-Shien Chen
Original Assignee
Taiwan Semiconductor Mfg
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg filed Critical Taiwan Semiconductor Mfg
Publication of TW201310584A publication Critical patent/TW201310584A/zh
Application granted granted Critical
Publication of TWI463609B publication Critical patent/TWI463609B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
    • H01L2021/60022—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process using bump connectors, e.g. for flip chip mounting
    • H01L2021/60225—Arrangement of bump connectors prior to mounting
    • H01L2021/60255—Arrangement of bump connectors prior to mounting wherein the bump connectors are provided as prepeg, e.g. are provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H01L2224/05027—Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05181—Tantalum [Ta] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/05186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05575—Plural external layers
    • H01L2224/0558—Plural external layers being stacked
    • H01L2224/05582—Two-layer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05639—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05664—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05671—Chromium [Cr] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05684—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/06102—Disposition the bonding areas being at different heights
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11464—Electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13164—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1405—Shape
    • H01L2224/14051—Bump connectors having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1415—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/14152—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry being non uniform, i.e. having a non uniform pitch across the array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/14179—Corner adaptations, i.e. disposition of the bump connectors at the corners of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/17104—Disposition relative to the bonding areas, e.g. bond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1751—Function
    • H01L2224/17515—Bump connectors having different functions
    • H01L2224/17517—Bump connectors having different functions including bump connectors providing primarily mechanical support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the bump connector during or after the bonding process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/811—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector the bump connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/81101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector the bump connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a bump connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83104—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus by applying pressure, e.g. by injection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0494—4th Group
    • H01L2924/04941—TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0495—5th Group
    • H01L2924/04953—TaN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一種半導體裝置包括一金屬墊於一基板上。一鈍化層包括一部份於該金屬墊上。一後鈍化內連線(post-passivation interconnect,PPI)與該金屬墊電性耦接，其中該後鈍化內連線包括一部份於該金屬墊與該鈍化層上。一聚合物層於該後鈍化內連線上。一虛擬凸塊於該聚合物層上，其中該虛擬凸塊與在該聚合物層下方之導電結構電性絕緣。

Description

半導體裝置與半導體裝置的形成方法
本發明係關於一種半導體裝置，且特別關於一種封裝結構。
積體電路通常形成於半導體晶片上。為了增加製造生產量與降低製造成本，將積體電路製造於半導體晶圓中，各含有許多相同之半導體晶片。在製造出積體電路之後，於半導體晶片可被使用之前，將半導體晶片從晶圓鋸開並進行封裝。
在一些封裝程中，將半導體晶片(在本技術領域中也意指為晶粒)與封裝基板接合。使用底層填充材料(underfill)來使接合更牢固，底層填充材料一般包括環氧樹脂。可使用倒裝晶片接合(flip-chip bonding)或導線接合(wire bonding)來使半導體晶片接合。在一晶粒至一封裝基板的倒裝晶片接合製程中，執行一回焊(re-flow)以使介於晶粒與封裝基板之間的焊料熔化，以將晶粒連接至封裝基板。
常見的接合製程遭受到缺點。例如，在回焊製程期間，封裝基板的溫度被提高。由於封裝基板易於翹曲(warpage)，所以在回焊之後，封裝基板可具有翹曲。隨著封裝基板的翹曲，於晶粒之中心或邊緣的凸塊及/或封裝基板被伸長或壓縮。此引起要傳給在晶粒中之低介電常數介電材料的應力，且分層可發生至低介電常數層。此外，應力可更進一步導致介於晶粒與封裝基板之間的焊料遭受破裂。
本發明提供一種半導體裝置，包括：一基板；一金屬墊於該基板上；一鈍化層，其包括一部份於該金屬墊上；一後鈍化內連線(post-passivation interconnect,PPI)與該金屬墊電性耦接，其中該後鈍化內連線包括一部份於該金屬墊與該鈍化層上；一聚合物層於該後鈍化內連線上；以及一虛擬凸塊於該聚合物層上，其中該虛擬凸塊與在該聚合物層下方之導電結構電性絕緣。
本發明另提供一種半導體裝置，包括：一第一封裝構件，其包括一電性連接器；一第二封裝構件，經由該電性連接器與該第一封裝構件結合；以及一虛擬凸塊，介於該第一封裝構件與該第二封裝構件之間，其中該虛擬凸塊與在該第一封裝構件與該第二封裝構件之至少一個中的導電結構電性絕緣。
本發明還提供一種半導體裝置的形成方法，包括：形成一第一封裝構件，其中該形成之步驟包括下列步驟：形成一鈍化層，其包括一部份於一金屬墊上；形成一後鈍化內連線，其與該金屬墊電性耦接，其中該後鈍化內連線包括一部份於該金屬墊與該鈍化層上；形成一聚合物層於該後鈍化內連線上；形成一電性連接器於該後鈍化內連線上且與其電性耦接，其中該電性連接器包括一部份於該聚合物層之一上表面上；以及形成一虛擬凸塊於該聚合物層上，其中該虛擬凸塊與在該聚合物層下方之所有導電結構絕緣。
為了讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉較佳實施例，並配合所附圖示，作詳細說明如下：
依照一實施例提供一封裝結構，此封裝結構包括虛擬凸塊與其形成方法。圖解說明製造各種實施例的中間階段。之後討論實施例的變化。遍及各種圖式與說明之實施例，相同的參考標號被使用來代表相同的元件。
參見第1圖，提供晶圓10，其包括半導體基板20。在一實施例中，晶圓10為一裝置晶圓，其可包括主動裝置，例如電晶體於其中。因此，半導體基板20可為一塊狀矽(bulk silicon)基板或一絕緣層上矽(silicon-on-insulator)基板。也可使用其他半導體材料，包括III族、IV族與V族元素。在替代實施例中，晶圓10可為不包括主動裝置於其中之其他封裝構件的晶圓，且例如可為一中介層晶圓(interposer wafer)。在此實施例中，晶圓10不包括主動裝置，晶圓10可包括被動裝置，例如電阻器或電容器，或無被動裝置。此外，在晶圓10不包括主動裝置於其中的實施例中，基板20可為一介電基板，例如一玻璃基板、一陶瓷基板、一有機基板或其類似物。
當晶圓10為一裝置晶圓時，於半導體基板20的表面形成積體電路裝置，例如電晶體(概要性地繪示為21)。晶圓10可更包括層間介電層(inter-layer dielectric,ILD)22於半導體基板20上，與金屬層24於層間介電層22上。於介電層25中形成金屬層24，其包括金屬線26，其中更進一步藉由接觸插塞(via)28來將金屬線26內連結。在一實施例中，介電層25係由低介電常數介電材料所形成。低介電常數介電材料的介電常數(k值)可為，例如小於約2.8，或小於約2.5。金屬線26與接觸插塞28可由銅或銅合金來形成，然而，它們也可由其他材料來形成。
金屬墊30被形成於金屬層24上，且與金屬線26與接觸插塞28電性連接。金屬墊30可為鋁墊或鋁合金墊，且因此於此之後二擇一地意指為鋁墊30，然而也可使用其他金屬材料。於金屬層24上形成鈍化層32。鈍化層32的一部份可覆蓋鋁墊30的邊緣部分。經由在鈍化層32中的開口露出鋁墊30的中央部分。鈍化層32可為一單一層或一複合層，且可由一非多孔材料所形成。在一實施例中，鈍化層32係由一複合層所形成，複合層包括一氧化矽層(未顯示)與一氮化矽層(未顯示)於氧化矽層上。鈍化層32也可由無摻雜矽玻璃(un-doped silicate glass,USG)、氮氧化矽及/或其類似物所形成。
於鈍化層32上形成聚合物層36。聚合物層36可由一聚合物，例如環氧樹脂、聚亞醯胺、苯並環丁烯(benzocyclobutene,BCB)、聚苯並噁唑(polybenzoxazole,PBO)與其類似物所形成。形成方法包括旋塗(spin coating)或其他方法。將聚合物層圖案化以形成一開口，經由此開口露出鋁墊30。聚合物層36的圖案化可包括光微影蝕刻技術。之後可執行一硬化以硬化聚合物層36。形成後鈍化內連線(post-passivation interconnect,PPI)38以經由在聚合物層36中的開口與鋁墊30電性耦接。後鈍化內連線38被以此命名，是由於後鈍化內連線38的形成係在於鈍化層32的形成之後。後鈍化內連線38可由純銅、實質上純銅、一銅合金或其他金屬或金屬合金所形成。後鈍化內連線38可更包括一含鎳層。形成方法包括電鍍、無電電鍍(electroless plating)、濺鍍、化學氣相沈積方法與其類似方法。
第2圖繪示聚合物層39的形成與圖案化。聚合物層39可包括一聚合物，其可為聚亞醯胺或其類似物，且可使用與圖案化聚合物36相同之方法來將聚合物層39圖案化。在聚合物層39的圖案化之後，後鈍化內連線38的一部份經由開口40被露出。在其中後鈍化內連線38係由一含銅材料所形成的一實施例中，含銅材料之表面可經由在聚合物層39中的開口40被露出。
參見第3圖，凸塊下冶金(undr-bump-metallurgy,UBM)層45被形成。在一實施例中，凸塊下冶金層45包括阻擋層42與晶種層44於阻擋層42上。阻擋層42延伸進入開口40且與後鈍化內連線38電性耦接，且可與後鈍化內連線38物理性接觸。阻擋層42可為一鈦層、一氮化鈦層、一鉭層、一氮化鉭層或由鈦合金或鉭合金所形成的一層。晶種層44的材料可包括銅或銅合金，且因此於此之後可將晶種層44二擇一地意指為一銅晶種層。然而，也可包括其他材料，例如銀、金、鋁、鈀、鎳、鎳合金、鎢合金、鉻、鉻合金與其組合。在一實施例中，使用物理氣相沈積或其他合適的方法來形成阻擋層42與晶種層44。阻擋層42可具有一厚度介於約500 與約2,000 之間。晶種層44可具有一厚度介於約1,000 與10,000 之間，然而，也可使用不同的厚度。
第4圖繪示罩幕46的形成，其可由，例如一光阻或經層壓(laminated)的一乾燥薄膜形成於凸塊下冶金層45上。將罩幕46圖案化，並經由在罩幕46中之開口47與48露出凸塊下冶金層45的部份，而凸塊下冶金層45的一些部份則由罩幕46所覆蓋。開口46係直接於後鈍化內連線38的一金屬墊上。另一方面，將開口48形成於聚合物層39的一部份上，但可不具有一下方的後鈍化內連線墊(PPI pad)。因此，經由開口46所露出之露出部分凸塊下冶金層45A可具有下表面45A1，其接觸後鈍化內連線38，而經由開口48所露出之露出部分凸塊下冶金層45B可具有一下表面45B1，其不與任何後鈍化內連線墊接觸。作為替代地，下表面45B1與一下方之介電材料接觸，而介電材料在一些實施例中可為聚合物層39。
接著，也如於第5圖中所示，形成金屬凸塊50與52。在一實施例中，將晶圓10置入一電鍍溶液中(未顯示)，並執行一鍍覆(plating)步驟以於凸塊下冶金層45上及於開口47與48中分別形成金屬凸塊50與52。鍍覆可為一電鍍、一無電解電鍍、一浸鍍(immersion plating)或其類似方法。在一示範實施例中，金屬凸塊50與52的各個包含一非可回焊(non-reflowable)部分，其在隨後的回焊製程中不熔化。非可回焊(non-reflowable)部分被指示為銅凸塊50A與52A。視需要而定，金屬凸塊50與52可包括蓋層，其擇自由一鎳層、一鎳合金、一鈀層、一金層、一銀層與其多層所組成的群組，形成於銅凸塊50A與52A上。金屬凸塊50與52可更分別包括焊料蓋50B與52B，其可由一Sn-Ag合金、一Sn-Cu合金、一Sn-Ag-Cu合金或其類似物所形成，且可為無鉛或含鉛。
參見第6圖，在形成金屬凸塊50之後，移除罩幕46，且露出先前由罩幕46所覆蓋之凸塊下冶金層45的部分。之後執行一蝕刻以移除不被金屬凸塊(例如，金屬凸塊50與52)所覆蓋之凸塊下冶金層45的部分。在所產生的結構中，凸塊下冶金部分45A與上方之金屬凸塊50結合意指為電性連接器60，而凸塊下冶金部分45B與上方之金屬凸塊52結合意指為虛擬凸塊62。電性連接器60與金屬墊30電性耦接。虛擬凸塊62直接位於聚合物層39上，且可與其物理性接觸。因此虛擬凸塊62不具有與在晶圓10中之結構電性連接的功能，且不與任何後鈍化內連線電性耦接。
第8圖繪示，在電性連接器60與虛擬凸塊62形成後之晶圓10之一部分的上視圖。於此之後，所繪示的部分意指為封裝構件100。當晶圓10為一裝置晶圓時，封裝構件100可為一裝置晶粒。或者，封裝構件100可為一中介層(intrposer)。封裝構件100具有邊緣102。可於封裝構件100之表面形成複數個電性連接器60與虛擬凸塊62。在一實施例中，將虛擬凸塊分佈至在封裝構件100中的複數個部分，而此複數個部分在將封裝構件與其他封裝構件接合之後，遭受高度的應力，又其他封裝構件，例如為一封裝基板。例如，可將虛擬凸塊分佈置封裝構件100之中央與四個角落，封裝構件100的這些部分相較於其他部分具有較高的應力。在封裝構件100的其他部分中，配置電性連接器60，其與封裝構件100內之結構電性連接。在所繪示之實施例中，將四個虛擬凸塊62配置於封裝構件100的中央，並將兩個虛擬凸塊62配置於封裝構件100的各角落，然而可將較多或較少之虛擬凸塊62配置於各位置。剩餘之凸塊可為電性連接器60。
在形成電性連接器60與虛擬凸塊62之後，可將晶圓10鋸成晶粒，其中這些晶粒的一個，如第8圖中之封裝構件100所示。之後將封裝構件100與封裝構件200接合，如於第7圖中所示。或者，可在晶圓10的晶粒鋸之前來執行封裝構件100至封裝構件200的接合，且因此個別之接合為一晶圓至晶圓接合(wafer to wafer bonding)。封裝構件200可為一裝置晶粒，其包括主動裝置，例如電晶體於其中，或可為其他封裝構件，具有非主動裝置於其中，例如一封裝基板、一中介層或其類似物。封裝構件200也可為一封裝體，其包括一或多個裝置晶粒、中介層及/或封裝基板於任何結合形式中。電性連接器60可與電性連接器202接合，其可為一金屬結構。電性連接器202可與結構206電性耦接，而結構206相較於電性連接器202在封裝構件200的相對側上。在一實施例中，結構206為一焊料凸塊，且經由金屬線與接觸插塞204與電性連接器202耦接。
虛擬凸塊60可與介電層210物理性接觸，介電層210為在封裝構件200的表面。因此虛擬凸塊62可與在封裝構件200中的所有金屬結構絕緣，且可為電性飄移。或者，虛擬凸塊62可與在封裝構件200中之接合墊212接合，而使用虛線來標示接合墊212。然而，接合墊不與在封裝構件200之相對側上的任何其他導電結構電性耦接，且不與在封裝構件200內的任何其他導電結構電性耦接。
第7圖繪示一凸塊導線直接(bump on trace,BOT)結構，其中金屬結構202為一金屬導線，且電性連接器60與金屬導線202接合，此接合結構包括焊料220，其也與金屬導線202之側壁接合。焊料220可包括於第6圖中之焊料蓋50B，且可視需要而定包括預焊料(pre-solder)，其被預先提供至金屬結構202上。在替代實施例中，如於第9圖中所示，電性連接器60可與在封裝構件200表面的接合墊214接合，而虛擬凸塊62仍為電性飄移，且可與在封裝構件200中的所有導電結構絕緣。在如第7與9圖中所示之封裝構件100與200的接合之後，將一底層填充材料(underfill)230填入介於封裝構件100與200之間的空間中。底層填充材料230可與電性連接器60與虛擬凸塊62物理性接觸。
在這些實施例中，虛擬凸塊62(第7與第9圖)可不與在封裝結構100中的任何後鈍化內連線連接。在用來接合封裝構件100與封裝構件200的回焊製程之後，封裝構件100與200可具有翹曲。當應力由於翹曲而產生時，虛擬凸塊62可將應力傳給相對地軟的聚合物層39而不是傳送至後鈍化內連線38與封裝構件100內的結構，以使應力可藉由聚合物層39來吸收。因此可改善封裝構件100的可靠度。相似地，在封裝構件200的那側，藉由介電層210將應力部分吸收，來取代直接提供至在封裝構件200中的金屬墊、金屬線與接觸插塞。
根據實施例，一種裝置包括一金屬墊於一基板上。鈍化層包括一部份於金屬墊上。一後鈍化內連線與金屬墊電性耦接，其中後鈍化內連線包括一部份於金屬墊與鈍化層上。一聚合物層於後鈍化內連線上。一虛擬凸塊於聚合物層上，其中虛擬凸塊與在聚合物層下方之導電結構電性絕緣。
根據其他實施例，一種裝置包括一第一封裝構件，其具有一電性連接器，與包括一第二封裝構件，其經由第一電性連接器與第一封裝結構接合。一虛擬凸塊位於第一封裝構件與第二封裝構件之間。虛擬凸塊與在第一封裝構件與第二封裝構件之至少一個中的導電結構電性絕緣。
根據又其他實施例，一種形成一封裝構件的方法，包括形成一鈍化層，其具有一部份於一金屬墊上，與形成一後鈍化內連線，其與金屬墊電性耦合。後鈍化內連線具有一部份於金屬墊與鈍化層上。於後鈍化內連線上形成一聚合物層。形成一電性連接器，且其與後鈍化內連線電性耦接，其中電性連接器包括一部份於聚合物層之上表面上。於聚合物層上形成一虛擬凸塊，其中虛擬凸塊與在聚合物層下方的所有導電結構絕緣。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10．．．晶圓
20．．．半導體基板
21．．．電晶體
22．．．層間介電層
24．．．金屬層
25．．．介電層
26．．．金屬線
28、204．．．接觸插塞
30．．．金屬墊
32．．．鈍化層
36、39．．．聚合物層
38．．．後鈍化內連線(post-passivation interconnect,PPI)
40、47、48．．．開口
42．．．阻擋層
44．．．晶種層
45．．．凸塊下冶金(undr-bump-metallurgy,UBM)層
46．．．罩幕
45A．．．經由開口46所露出之露出部分凸塊下冶金層
45A1．．．部分凸塊下冶金層45A的下表面
45B．．．經由開口48所露出之露出部分凸塊下冶金層
45B1．．．部分凸塊下冶金層45B的下表面
50、52．．．金屬凸塊
50A、52A．．．銅凸塊
50B、52B．．．焊料蓋
60、202．．．電性連接器
62．．．虛擬凸塊
100、200．．．封裝構件
102．．．封裝晶粒的邊緣
206．．．結構(焊料凸塊)
210．．．介電層
212．．．接合墊
214．．．接合墊
220．．．焊料
230．．．底層填充材料(underfill)
第1圖至第7圖為根據各種實施例在一封裝體之製造中的中間階段的剖面圖；
第8圖繪示一晶片的上視圖，其中虛擬凸塊被分佈至晶片之高應力區域；以及
第9圖繪示根據替代實施例之一封裝體。
10．．．晶圓
20．．．半導體基板
21．．．電晶體
22．．．層間介電層
24．．．金屬層
25．．．介電層
30．．．金屬墊
32．．．鈍化層
36、39．．．聚合物層
38．．．後鈍化內連線(post-passivation interconnect,PPI)
45A．．．經由開口46所露出之露出部分凸塊下冶金層
45B．．．經由開口48所露出之露出部分凸塊下冶金層
50、52．．．金屬凸塊
50A、52A．．．銅凸塊
50B、52B．．．焊料蓋
60．．．電性連接器
62．．．虛擬凸塊

Claims (11)

  1. 一種半導體裝置，包括：一基板；一金屬墊於該基板上；一鈍化層，其包括一部份於該金屬墊上；一後鈍化內連線(post-passivation interconnect,PPI)與該金屬墊電性耦接，其中該後鈍化內連線包括一部份於該金屬墊與該鈍化層上；一聚合物層於該後鈍化內連線上；以及一虛擬凸塊於該聚合物層上，其中該虛擬凸塊與在該聚合物層下方之導電結構電性絕緣。
  2. 如申請專利範圍第1項所述之裝置，其中該虛擬凸塊與該聚合物層物理性接觸。
  3. 如申請專利範圍第1項所述之裝置，其中該虛擬凸塊包括一非可回焊凸塊與一焊料蓋於該非可回焊凸塊上。
  4. 如申請專利範圍第1項所述之裝置，更包括一非可回焊電性連接器形成於該聚合物層中，其中該電性連接器與該後鈍化內連線電性耦接。
  5. 如申請專利範圍第4項所述之裝置，更包括一封裝構件，其中該封裝構件包括：一額外之電性連接器與該非可回焊電性連接器接合；以及一介電層在該封裝構件的一表面，其中該虛擬凸塊與該介電層接觸，且藉由該介電層與該封裝構件中之導電結構電性絕緣。
  6. 如申請專利範圍第1項所述之裝置，其中該聚合層為一聚亞醯胺層，且其中該虛擬凸塊包括一含銅材料。
  7. 一種半導體裝置，包括：一第一封裝構件，其包括一電性連接器；一第二封裝構件，經由該電性連接器與該第一封裝構件接合；以及一虛擬凸塊，介於該第一封裝構件與該第二封裝構件之間，其中該虛擬凸塊與在該第一封裝構件與該第二封裝構件之至少一個中的導電結構電性絕緣。
  8. 一種半導體裝置的形成方法，包括：形成一第一封裝構件，其中該形成之步驟包括下列步驟：形成一鈍化層，其包括一部份於一金屬墊上；形成一後鈍化內連線，其與該金屬墊電性耦接，其中該後鈍化內連線包括一部份於該金屬墊與該鈍化層上；形成一聚合物層於該後鈍化內連線上；形成一電性連接器於該後鈍化內連線上且與其電性耦接，其中該電性連接器包括一部份於該聚合物層之一上表面上；以及形成一虛擬凸塊於該聚合物層上，其中該虛擬凸塊與在該聚合物層下方之所有導電結構絕緣。
  9. 如申請專利範圍第8項所述之方法，其中形成該電性連接器與該虛擬凸塊的該些步驟，包括：形成一開口於該聚合物層中；形成一凸塊下冶金(undr-bump-metallurgy,UBM)層延伸進入該開口；形成一罩幕於該凸塊下冶金層上；圖案化該罩幕以形成一第一開口與一第二開口，其中該第一開口的一部份為在該後鈍化內連線之一部分上且與其重直對齊，且該第二開口之全部為在於該聚合物層之一部分上且與其垂直對齊；形成一第一凸塊於該第一開口中；形成一第二凸塊於該第二開口中；移除該罩幕；以及移除該凸塊下冶金層由該罩幕所覆蓋的部分，其中該第一凸塊與該凸塊下冶金層之一第一部份直接於該第一凸塊下方形成該電性連接器，且其中該第二凸塊與該凸塊下冶金層之一第二部分直接於該第二凸塊下方形成該虛擬凸塊。
  10. 如申請專利範圍第9項所述之方法，其中該凸塊下冶金層之該第二部份具有一底部與該聚合物層物理性接觸，而不與在該第一封裝構件中的任何後鈍化內連線電性耦接。
  11. 如申請專利範圍第8項所述之方法，其中該電性連接器與該虛擬凸塊為同時形成。
TW100139546A 2011-08-17 2011-10-31 半導體裝置與半導體裝置的形成方法 TWI463609B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/211,438 US8912649B2 (en) 2011-08-17 2011-08-17 Dummy flip chip bumps for reducing stress

Publications (2)

Publication Number Publication Date
TW201310584A true TW201310584A (zh) 2013-03-01
TWI463609B TWI463609B (zh) 2014-12-01

Family

ID=47712065

Family Applications (1)

Application Number Title Priority Date Filing Date
TW100139546A TWI463609B (zh) 2011-08-17 2011-10-31 半導體裝置與半導體裝置的形成方法

Country Status (4)

Country Link
US (5) US8912649B2 (zh)
KR (1) KR101449789B1 (zh)
CN (1) CN102956590B (zh)
TW (1) TWI463609B (zh)

Families Citing this family (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5538682B2 (ja) * 2008-03-06 2014-07-02 ピーエスフォー ルクスコ エスエイアールエル 半導体装置及びその製造方法
KR20110124993A (ko) * 2010-05-12 2011-11-18 삼성전자주식회사 반도체 칩 및 이를 포함하는 반도체 패키지 및 반도체 칩의 제조 방법
US8912649B2 (en) 2011-08-17 2014-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy flip chip bumps for reducing stress
US8871629B2 (en) * 2011-11-08 2014-10-28 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of and semiconductor devices with ball strength improvement
US9978656B2 (en) * 2011-11-22 2018-05-22 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming fine-pitch copper bump structures
KR101383002B1 (ko) * 2012-05-25 2014-04-08 엘지이노텍 주식회사 반도체 패키지 기판, 이를 이용한 패키지 시스템 및 이의 제조 방법
US9355978B2 (en) 2013-03-11 2016-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging devices and methods of manufacture thereof
US9773724B2 (en) * 2013-01-29 2017-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices, methods of manufacture thereof, and semiconductor device packages
US9196559B2 (en) * 2013-03-08 2015-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. Directly sawing wafers covered with liquid molding compound
US9196529B2 (en) 2013-09-27 2015-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. Contact pad for semiconductor devices
KR20150038842A (ko) * 2013-10-01 2015-04-09 삼성디스플레이 주식회사 구동 칩, 이를 구비한 표시 장치 및 구동 칩 제조 방법
KR101697603B1 (ko) 2014-12-08 2017-01-19 삼성전자주식회사 반도체 패키지
JP6470320B2 (ja) * 2015-02-04 2019-02-13 オリンパス株式会社 半導体装置
CN106206516B (zh) * 2015-05-26 2019-08-06 意法半导体公司 带有悬臂式焊盘的叠层半导体封装体
JP6530298B2 (ja) * 2015-10-09 2019-06-12 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
KR102491069B1 (ko) * 2015-12-03 2023-01-26 삼성전자주식회사 반도체 소자
KR102478381B1 (ko) 2015-12-21 2022-12-20 삼성전자주식회사 반도체 패키지
CN106971949B (zh) * 2016-01-14 2019-06-28 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法和电子装置
US9984987B2 (en) * 2016-08-05 2018-05-29 Nanya Technology Corporation Semiconductor structure and manufacturing method thereof
DE102017118183B4 (de) 2016-09-14 2022-03-10 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleiter-Packages mit Dummy-Verbindern und Verfahren zu deren Herstellung
US10276548B2 (en) * 2016-09-14 2019-04-30 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages having dummy connectors and methods of forming same
US9922964B1 (en) * 2016-09-19 2018-03-20 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure with dummy die
US9911709B1 (en) 2016-10-26 2018-03-06 Advanced Semiconductor Engineering, Inc. Semiconductor device and semiconductor manufacturing process
US10692813B2 (en) * 2016-11-28 2020-06-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package with dummy bumps connected to non-solder mask defined pads
US10274818B2 (en) 2016-12-15 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Lithography patterning with sub-resolution assistant patterns and off-axis illumination
US10319695B2 (en) * 2017-06-29 2019-06-11 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and bump formation process
US10818627B2 (en) * 2017-08-29 2020-10-27 Advanced Semiconductor Engineering, Inc. Electronic component including a conductive pillar and method of manufacturing the same
TWI636533B (zh) * 2017-09-15 2018-09-21 Industrial Technology Research Institute 半導體封裝結構
CN107895698A (zh) * 2017-09-26 2018-04-10 宁波芯健半导体有限公司 一种15μm铜厚的封装方法
US20190295979A1 (en) * 2018-03-23 2019-09-26 Nanya Technology Corporation Solder bump, flip chip structure and method for preparing the same
US10593640B2 (en) 2018-04-18 2020-03-17 Texas Instruments Incorporated Flip chip integrated circuit packages with spacers
US11145564B2 (en) * 2018-06-29 2021-10-12 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-layer passivation structure and method
US11456268B2 (en) * 2019-01-21 2022-09-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof
US11600590B2 (en) * 2019-03-22 2023-03-07 Advanced Semiconductor Engineering, Inc. Semiconductor device and semiconductor package
US11289376B2 (en) 2019-07-31 2022-03-29 Taiwan Semiconductor Manufacturing Co., Ltd Methods for forming self-aligned interconnect structures
JP7293056B2 (ja) * 2019-09-12 2023-06-19 キオクシア株式会社 半導体装置およびその製造方法
US11894829B2 (en) * 2019-11-13 2024-02-06 Rf360 Singapore Pte. Ltd. Variation of metal layer stack under under bump metallization (UBM)
CN113658929B (zh) * 2020-05-12 2023-09-12 合肥晶合集成电路股份有限公司 一种半导体结构及其制备方法
KR20210146608A (ko) * 2020-05-27 2021-12-06 삼성전자주식회사 반도체 패키지
US11715755B2 (en) * 2020-06-15 2023-08-01 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and method for forming integrated high density MIM capacitor
US11424213B2 (en) * 2020-09-10 2022-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure including a first surface mount component and a second surface mount component and method of fabricating the semiconductor structure
US11855028B2 (en) 2021-01-21 2023-12-26 Taiwan Semiconductor Manufacturing Hybrid micro-bump integration with redistribution layer
US12057423B2 (en) 2021-02-04 2024-08-06 Taiwan Semiconductor Manufacturing Co., Ltd. Bump integration with redistribution layer
US11817361B2 (en) * 2021-02-12 2023-11-14 Taiwan Semiconductor Manufacturing Co., Ltd. Passivation structure with planar top surfaces
US12009400B2 (en) 2021-02-14 2024-06-11 Taiwan Semiconductor Manufacturing Company, Ltd. Device providing multiple threshold voltages and methods of making the same
CN113628984A (zh) * 2021-08-26 2021-11-09 西安紫光国芯半导体有限公司 一种3dic芯片及3dic芯片的制备方法
US20230307418A1 (en) * 2022-03-23 2023-09-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package with enhanced bonding force

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01238148A (ja) 1988-03-18 1989-09-22 Fuji Electric Co Ltd 半導体装置
US5872393A (en) * 1995-10-30 1999-02-16 Matsushita Electric Industrial Co., Ltd. RF semiconductor device and a method for manufacturing the same
KR100269540B1 (ko) * 1998-08-28 2000-10-16 윤종용 웨이퍼 상태에서의 칩 스케일 패키지 제조 방법
US6225206B1 (en) * 1999-05-10 2001-05-01 International Business Machines Corporation Flip chip C4 extension structure and process
JP2003100801A (ja) * 2001-09-25 2003-04-04 Mitsubishi Electric Corp 半導体装置
US6750552B1 (en) * 2002-12-18 2004-06-15 Netlogic Microsystems, Inc. Integrated circuit package with solder bumps
KR100576156B1 (ko) 2003-10-22 2006-05-03 삼성전자주식회사 댐이 형성된 반도체 장치 및 그 반도체 장치의 실장 구조
US7465654B2 (en) * 2004-07-09 2008-12-16 Megica Corporation Structure of gold bumps and gold conductors on one IC die and methods of manufacturing the structures
US7122458B2 (en) * 2004-07-22 2006-10-17 Taiwan Semiconductor Manufacturing Co., Ltd. Method for fabricating pad redistribution layer
US7397121B2 (en) 2005-10-28 2008-07-08 Megica Corporation Semiconductor chip with post-passivation scheme formed over passivation layer
JP4871164B2 (ja) * 2007-02-21 2012-02-08 富士通株式会社 半導体集積回路
TWI351729B (en) * 2007-07-03 2011-11-01 Siliconware Precision Industries Co Ltd Semiconductor device and method for fabricating th
KR101485105B1 (ko) * 2008-07-15 2015-01-23 삼성전자주식회사 반도체 패키지
JP2010171125A (ja) * 2009-01-21 2010-08-05 Sharp Corp 半導体装置およびその製造方法
KR101307490B1 (ko) * 2009-03-30 2013-12-11 메기가 코포레이션 상부 포스트-패시베이션 기술 및 하부 구조물 기술을 이용한 집적 회로 칩
US8324738B2 (en) * 2009-09-01 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned protection layer for copper post structure
KR101632399B1 (ko) 2009-10-26 2016-06-23 삼성전자주식회사 반도체 패키지 및 그 제조방법
US20110193235A1 (en) * 2010-02-05 2011-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC Architecture with Die Inside Interposer
US8610270B2 (en) * 2010-02-09 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and semiconductor assembly with lead-free solder
US8174124B2 (en) * 2010-04-08 2012-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Dummy pattern in wafer backside routing
US8912649B2 (en) 2011-08-17 2014-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy flip chip bumps for reducing stress

Also Published As

Publication number Publication date
US20170309588A1 (en) 2017-10-26
US8912649B2 (en) 2014-12-16
US20150004751A1 (en) 2015-01-01
US9711477B2 (en) 2017-07-18
US20130043583A1 (en) 2013-02-21
CN102956590B (zh) 2015-11-25
KR20130020512A (ko) 2013-02-27
US20190259724A1 (en) 2019-08-22
KR101449789B1 (ko) 2014-10-13
US20160181220A1 (en) 2016-06-23
CN102956590A (zh) 2013-03-06
US10290600B2 (en) 2019-05-14
TWI463609B (zh) 2014-12-01
US9287234B2 (en) 2016-03-15
US10734347B2 (en) 2020-08-04

Similar Documents

Publication Publication Date Title
TWI463609B (zh) 半導體裝置與半導體裝置的形成方法
US11094641B2 (en) Fan-out package having a main die and a dummy die
US20240266189A1 (en) Semiconductor device and manufacturing method thereof
US11961791B2 (en) Package structures and methods for forming the same
TWI470756B (zh) 半導體結構及形成半導體裝置的方法
KR101447322B1 (ko) 멀티 칩 패키징을 위한 범프 구조물들
US8299616B2 (en) T-shaped post for semiconductor devices
US8921222B2 (en) Pillar structure having a non-planar surface for semiconductor devices
CN110957279B (zh) 半导体器件及其形成方法
US9673158B2 (en) Formation of connectors without UBM
US9548283B2 (en) Package redistribution layer structure and method of forming same
US10867975B2 (en) Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices
US11296012B2 (en) Barrier structures between external electrical connectors
US11239103B2 (en) Package-on-package structure
KR102481141B1 (ko) 반도체 패키징된 디바이스 내의 본딩 구조물 및 그 형성 방법
US10651055B2 (en) Post-passivation interconnect structure and method of forming the same
US9576888B2 (en) Package on-package joint structure with molding open bumps
TW202312399A (zh) 晶粒與凸塊下金屬之間的分離重新分布層連接