JP5150518B2 - 半導体装置および多層配線基板ならびにそれらの製造方法 - Google Patents
半導体装置および多層配線基板ならびにそれらの製造方法 Download PDFInfo
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- JP5150518B2 JP5150518B2 JP2009001253A JP2009001253A JP5150518B2 JP 5150518 B2 JP5150518 B2 JP 5150518B2 JP 2009001253 A JP2009001253 A JP 2009001253A JP 2009001253 A JP2009001253 A JP 2009001253A JP 5150518 B2 JP5150518 B2 JP 5150518B2
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- insulating layer
- wiring board
- multilayer wiring
- pad
- pads
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- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
- H05K1/113—Via provided in pad; Pad over filled via
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Description
において大きな温度変化を受けると、半導体チップと多層配線基板との接続を担うはんだバンプに応力が集中し、はんだバンプまたはその近傍にクラックが発生して接続不良が起きるおそれがあった。
多層配線基板4の製造方法としては、第2〜第4絶縁層42〜44の製造までは一般的にシーケンシャルビルドアップ製造工法と呼ばれるビルドアップ基板作製方法を用い、ガラスクロスを含むコア基板40上に絶縁層と回路パターンとを順次形成する。以下に、多層配線基板4の具体的な製造方法を図3〜図5を参照しながら説明する。
ガラスマスクを位置合わせる。その後、露光と現像を行うことで必要な導体パターン以外の部位の銅めっき膜を露出させたエッチングレジストを形成する。そして、銅めっき膜のうちエッチングレジストに覆われていない部分をエッチングにより溶解させて除去した後、エッチングレジストを剥離することで、第2絶縁層42上に回路パターン51に電気的に接続された第2接続パッド5bおよび回路パターン52を形成する。
図6に示すように、半導体チップ2の第1電極パッド3aおよび第2電極パッド3b上の所定位置に直径100μmのはんだボールを搭載し、窒素ガス雰囲気下でリフロー処理を行うことではんだバンプ7を形成する。
クス71が付着しなければ特に問わない。例えば、はんだバンプ7の高さよりも薄い膜厚(例えば50μm)で平坦面に均一に塗布されたフラックス71中に、半導体チップ2に形成されたはんだバンプ7を浸漬することによって、はんだバンプ7にフラックス71を付着させることができる。こうすることで、フラックス71のはんだに対する濡れ性の作用により、はんだバンプ7のフラックス71中に浸漬されていない部分にまでフラックス71がぬれ広がり、はんだバンプ7の表面を均一にフラックス71で覆うことができる。
図7に示すように、多層配線基板4と半導体チップ2を所定の位置関係となるように位置合わせし、多層配線基板4の表面4a上に半導体チップ2を接続パッド5と電極パッド3とがはんだバンプ7を挟んで対向するように搭載する。この搭載段階では、多層配線基板4の第1接続パッド5aおよび第2接続パッド5bにフラックス71を介して(正確にはバリアメタル層50をも介して)はんだバンプ7が接触しているのみであり、はんだ接続は行われていない。
実施例1では、8.0×8.0mmの大きさの半導体チップ2を用い、電極パッド3、接続パッド5、およびはんだバンプ7の数量を1600個とした(パッドピッチ:180μm)。コア基板40としてガラスエポキシ基板を用いた。第1絶縁層41を構成する熱可塑性樹脂としてはポリフェニレンエーテルを用い、第2絶縁層42を構成する熱硬化性樹脂としては平均粒径5μmの球状のシリカ(無機フィラー)が50体積%配合されたエポキシ樹脂を用いた。最表面に存在する第1絶縁層41の厚さを30μmとし、第2絶縁層42の厚さを45μmとした。その他(はんだバンプ7の体積、電極パッド3および接続パッド5の形状および大きさ、開口45a,45bの大きさなど)は前記実施形態で具体的に例示したものを採用した。以上の条件で、半導体装置を製造した。
実施例1に対し、表側ソルダーレジスト45における第1接続パッド5aに対応する位置の開口45aの大きさを130μmから他の開口45bと同じ90μmに変更した以外は、実施例1と同様の条件で半導体装置を製造した。
実施例1に対し、第1絶縁層41の厚さが第2電極パッド3bと第2接続パッド5bの間に形成されるはんだバンプ7の高さの2分の1となるように45μmと変更した以外は、実施例1と同様の条件で半導体装置を製造した。
比較例では、図11に示すような半導体装置10を製造した。比較例に係る多層配線基板4’は、半導体チップ2の電極パッド3とはんだバンプ7を介して接続する接続パッド5が、全て同一の絶縁層上に形成された構造を有している。この比較例に係る多層配線基板4’の製造は、第2絶縁層に相当する絶縁層49aを形成するまでは前記実施形態と同様に行い、絶縁層49aの全面上に絶縁層49bを絶縁層49aと同じ材料(無機フィラーが配合された熱硬化性樹脂)で形成した。すなわち、全ての絶縁層を同一材料とし、その厚さを全て45μmとした。そして、絶縁層49b上に接続パッド5を形成した。また、ソルダーレジストの厚さを20μmとし、接続パッド5を露出させる開口の直径を全て90μmとした。その他の部分は実施例1と同様にした。
2 半導体チップ
2a 裏面
3 電極パッド
3a 第1電極パッド
3b 第2電極パッド
4 多層配線基板(インターポーザ)
4a 表面
4b 裏面
41 第1絶縁層(上側絶縁層)
42 第2絶縁層(下側絶縁層)
45 表側ソルダーレジスト
46 裏側ソルダーレジスト
45a,45b 開口
5 接続パッド
5a 第1接続パッド
5b 第2接続パッド
6 外部接続用パッド
7 はんだバンプ
8 アンダーフィル
Claims (18)
- 裏面に電極パッドが設けられた半導体チップと、表面に前記電極パッドと対向する接続パッドが設けられた多層配線基板と、を備え、
前記電極パッドは、前記半導体チップの裏面の各角に近接して配置された電極パッドを含む第1電極パッドと、前記第1電極パッド以外の第2電極パッドとからなり、
前記接続パッドは、前記第1電極パッドとバンプを介して接続された第1接続パッドと、前記第2電極パッドとバンプを介して接続された第2接続パッドとからなり、
前記多層配線基板は、前記第1接続パッドを支持する第1絶縁領域と、前記第2接続パッドを支持する第2絶縁領域とを有し、
前記第1絶縁領域は、熱可塑性樹脂で構成されており、前記第2絶縁領域は、熱硬化性樹脂で構成されている、半導体装置。 - 前記多層配線基板は、第1絶縁領域を構成する第1絶縁層と、第2絶縁領域を構成する第2絶縁層とを有し、前記第1絶縁層は、前記第2絶縁層上に積層されている、請求項1に記載の半導体装置。
- 裏面に電極パッドが設けられた半導体チップと、表面に前記電極パッドと対向する接続パッドが設けられた多層配線基板と、を備え、
前記電極パッドは、前記半導体チップの裏面の各角に近接して配置された電極パッドを含む第1電極パッドと、前記第1電極パッド以外の第2電極パッドとからなり、
前記接続パッドは、前記第1電極パッドとバンプを介して接続された第1接続パッドと、前記第2電極パッドとバンプを介して接続された第2接続パッドとからなり、
前記多層配線基板は、前記第1接続パッドを支持する第1絶縁領域を構成する第1絶縁層と、前記第2接続パッドを支持する第2絶縁領域を構成する第2絶縁層とを有し、
前記第1絶縁層は、前記第2絶縁層上に積層されている、半導体装置。 - 前記第1絶縁層は、熱可塑性樹脂で構成されており、前記第2絶縁層は、熱硬化性樹脂で構成されている、請求項3に記載の半導体装置。
- 前記第1絶縁層の厚さは、前記多層配線基板中の第1絶縁層の下にある回路パターンの厚さの1.5倍以上であり、かつ、前記第2電極パッドと前記第2接続パッドの間に形成されるバンプの高さの2分の1以下である、請求項2〜4のいずれか一項に記載の半導体装置。
- 前記多層配線基板は、前記第1絶縁層および前記第2絶縁層を覆い、前記第1接続パッドおよび前記第2接続パッドに対応する位置に開口が設けられたソルダーレジストをさらに有し、
前記第1接続パッドに対応する位置の開口の大きさは、前記第2接続パッドに対応する位置の開口の大きさよりも大きく設定されている、請求項2〜5のいずれか一項に記載の半導体装置。 - 前記バンプは、いずれも略同じ体積のはんだバンプである、請求項1〜6のいずれか一項に記載の半導体装置。
- 前記熱可塑性樹脂は、融点が280℃以上のものである、請求項1、2または4に記載の半導体装置。
- 前記熱硬化性樹脂は、無機フィラーが配合されたものである、請求項1、2、4または8に記載の半導体装置。
- 前記多層配線基板と前記半導体チップとの間には、アンダーフィルが充填されている、請求項1〜9のいずれか一項に記載の半導体装置。
- 前記多層配線基板は、裏面に外部接続用パッドが設けられたインターポーザである、請求項1〜10のいずれか一項に記載の半導体装置。
- 前記多層配線基板は、ガラスクロスを含むコア基板を有している、請求項1〜11のいずれか一項に記載の半導体装置。
- 表面上に半導体チップが実装される多層配線基板であって、
前記表面上の矩形領域内に配置された複数のパッドと、前記複数のパッドのうち少なくとも四隅に位置するパッドを支持する第1絶縁領域を構成する第1絶縁層と、前記複数のパッドのうち前記第1絶縁層で支持されるパッド以外のパッドを支持する第1絶縁領域を構成する第2絶縁層と、を備え、
前記第1絶縁層は、熱可塑性樹脂で構成されており、前記第2絶縁層は、熱硬化性樹脂で構成されているとともに、前記第1絶縁層は、前記第2絶縁層上に積層されている、多層配線基板。 - 前記第1絶縁層の厚さは、5〜50μmである、請求項13に記載の多層配線基板。
- 前記多層配線基板は、前記第1絶縁層および前記第2絶縁層を覆い、前記複数のパッドに対応する位置に開口が設けられたソルダーレジストをさらに有し、
前記第1絶縁層で支持されるパッドに対応する位置の開口の大きさは、前記第2絶縁層で支持されるパッドに対応する位置の開口の大きさよりも大きく設定されている、請求項13または14に記載の多層配線基板。 - 前記熱可塑性樹脂は、融点が280℃以上のものである、請求項13〜15のいずれか一項に記載の多層配線基板。
- 前記熱硬化性樹脂は、無機フィラーが配合されたものである、請求項13〜16のいずれか一項に記載の多層配線基板。
- ガラスクロスを含むコア基板をさらに有する、請求項13〜17のいずれか一項に記載の多層配線基板。
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