JP5263053B2 - 半導体パッケージおよび半導体パッケージモジュール - Google Patents
半導体パッケージおよび半導体パッケージモジュール Download PDFInfo
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- JP5263053B2 JP5263053B2 JP2009173073A JP2009173073A JP5263053B2 JP 5263053 B2 JP5263053 B2 JP 5263053B2 JP 2009173073 A JP2009173073 A JP 2009173073A JP 2009173073 A JP2009173073 A JP 2009173073A JP 5263053 B2 JP5263053 B2 JP 5263053B2
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 125
- 229910000679 solder Inorganic materials 0.000 claims abstract description 55
- 230000001681 protective effect Effects 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims description 35
- 239000011241 protective layer Substances 0.000 claims 1
- 238000002161 passivation Methods 0.000 abstract description 12
- 238000005452 bending Methods 0.000 abstract description 5
- 229910052751 metal Inorganic materials 0.000 abstract description 5
- 239000002184 metal Substances 0.000 abstract description 5
- 150000002739 metals Chemical class 0.000 abstract description 2
- 230000035882 stress Effects 0.000 description 36
- 230000002093 peripheral effect Effects 0.000 description 22
- 230000006355 external stress Effects 0.000 description 12
- 239000011347 resin Substances 0.000 description 6
- 229920005989 resin Polymers 0.000 description 6
- 230000007423 decrease Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
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Description
この構成では、UBMを、ボンディングパッドに接続する部分と、半田バンプが形成される部分とから形成する。そして、バネ係数を低くするために、ボンディングパッドに接続する部分の径を小さくする。これにより、形成可能な半田バンプの形状を小さくすることなく、バネ係数を低くすることができる。また、ボンディングパッドに接続する部分の方が、半田バンプが形成される部分よりも、ボンディングパッドの表面に垂直な方向の長さが長いので、応力を緩和しやすい。したがって、より効果的に応力を緩和するUBMを形成することができる。
図1(A)は、本実施形態の半導体パッケージ10をダイ11の実装面11F側から見た外観斜視図である。図1(B)は当該半導体パッケージ10をダイ11の実装面11F側から見た平面図である。
以上のような構成により、本実施形態の半導体パッケージ10が形成される。
図5(A)は、本実施形態の半導体パッケージ10Aをダイ11の実装面11F側から見た外観斜視図である。図5(B)は当該半導体パッケージ10Aをダイ11の実装面11F側から見た平面図である。
図6は本実施形態の半導体パッケージ10Bをダイ11の実装面11F側から見た平面図である。
本実施形態の半導体パッケージ10Bは、UBM15の位置毎に径が異なるものであり、他の構成は、第1の実施形態に示した半導体パッケージ10と同じである。
Claims (5)
- 所定の電子回路が形成された半導体で平板状のダイと、
該ダイの実装面に配列形成された複数のボンディングパッドと、
該複数のボンディングパッドの表面にそれぞれに形成され、該表面に垂直な方向へ延びる形状からなるUBMと、
を備えた半導体パッケージであって、
前記UBMは、前記ボンディングパッドに接合する首部分と、該首部分の前記ボンディングパッドと反対側の端部に形成された頭部分とからなり、
各UBMの前記首部分の径は前記頭部分の径よりも小さく、
全てのUBMの頭部分の径は同じであり、
前記ダイの実装面における前記UBMの前記首部分の周囲を覆い且つ前記頭部分を露出する形状からなり所定の弾性を有する保護膜を備え、
前記ダイの角部のボンディングパッドに形成されたUBMの首部分の径は、前記ダイの中央位置のボンディングパッドに形成されたUBMの首部分の径よりも小さく形成されている、半導体パッケージ。 - 所定の電子回路が形成された半導体で平板状のダイと、
該ダイの実装面に配列形成された複数のボンディングパッドと、
該複数のボンディングパッドの表面にそれぞれに形成され、該表面に垂直な方向へ延びる形状からなるUBMと、
を備えた半導体パッケージであって、
前記UBMは、前記ボンディングパッドに接合する首部分と、該首部分の前記ボンディングパッドと反対側の端部に形成された頭部分とからなり、
各UBMの前記首部分の径は前記頭部分の径よりも小さく、
全てのUBMの頭部分の径は同じであり、
前記ダイの実装面における前記UBMの前記首部分の周囲を覆い且つ前記頭部分を露出する形状からなり所定の弾性を有する保護膜を備え、
前記ダイの外周辺部のボンディングパッドに形成されたUBMの首部分の径は、前記ダイの中央位置のボンディングパッドに形成されたUBMの首部分の径よりも小さく形成されている、半導体パッケージ。 - 前記保護膜は、前記ボンディングパッドのそれぞれを部分的に覆い、前記UBMの前記ボンディングパッドに接続する部分を囲む形状からなる、請求項1または請求項2に記載の半導体パッケージ。
- 所定の電子回路が形成された半導体で平板状のダイと、
該ダイの実装面に配列形成された複数ボンディングパッドと、
該複数のボンディングパッドの表面にそれぞれに形成され、該表面に垂直な方向へ延びる形状からなるUBMと、
を備えた半導体パッケージであって、
前記UBMは、前記ボンディングパッドに接合する首部分と、該首部分の前記ボンディングパッドと反対側の端部に形成された頭部分とからなり、
各UBMの前記首部分の径は前記頭部分の径よりも小さく、
全てのUBMの頭部分の径は同じであり、
前記ダイの実装面における前記UBMの前記首部分の周囲を覆い且つ前記頭部分を露出する形状からなり所定の弾性を有する保護膜を備え、
各ボンディングパッドに形成されるUBMの首部分の径は、前記ダイの中央位置のボンディングパッドに形成されたUBMからの距離が遠ざかるほど小さくなるように形成されている、半導体パッケージ。 - 請求項1〜請求項4のいずれかに記載の半導体パッケージと、
該半導体パッケージの各半田バンプに対向する位置に形成された実装用ランドを有する実装用基板と、を備え、
各UBMがそれぞれの半田バンプにより前記実装用ランドに接合されてなる、半導体パッケージモジュール。
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