TWI559410B - 以壓差法抑制材料翹曲的方法 - Google Patents
以壓差法抑制材料翹曲的方法 Download PDFInfo
- Publication number
- TWI559410B TWI559410B TW105114374A TW105114374A TWI559410B TW I559410 B TWI559410 B TW I559410B TW 105114374 A TW105114374 A TW 105114374A TW 105114374 A TW105114374 A TW 105114374A TW I559410 B TWI559410 B TW I559410B
- Authority
- TW
- Taiwan
- Prior art keywords
- carrier
- pressure
- gas
- carrier plates
- differential pressure
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
- H01L21/6735—Closed carriers
- H01L21/67389—Closed carriers characterised by atmosphere control
- H01L21/67393—Closed carriers characterised by atmosphere control characterised by the presence of atmosphere modifying elements inside or attached to the closed carrierl
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4842—Mechanical treatment, e.g. punching, cutting, deforming, cold welding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67092—Apparatus for mechanical treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67098—Apparatus for thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67121—Apparatus for making assemblies not otherwise provided for, e.g. package constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
- H01L21/6732—Vertical carrier comprising wall type elements whereby the substrates are horizontally supported, e.g. comprising sidewalls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
- H01L21/67346—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders characterized by being specially adapted for supporting a single substrate or by comprising a stack of such individual supports
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
- H01L21/6735—Closed carriers
- H01L21/67369—Closed carriers characterised by shock absorbing elements, e.g. retainers or cushions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
- H01L21/6735—Closed carriers
- H01L21/67379—Closed carriers characterised by coupling elements, kinematic members, handles or elements to be externally gripped
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
- H01L21/6735—Closed carriers
- H01L21/67383—Closed carriers characterised by substrate supports
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
Description
本發明係屬電子封裝的技術領域,尤指其技術上提供一以壓差法抑制材料翹曲的方法,透過氣囊內部之第一預定壓力和處理腔室的工作壓力所形成的壓力差,對載板之第一表面施加作用力,有效抑制載板翹曲變形,大幅度提高了載板的生產品質及有效降低生產成本。
近年來電子技術日新月異,利用積體電路元件所組成的電子產品,已成為現代人日常生活中不可或缺的工具。隨著電子產品邁向輕、薄、短、小設計的潮流,半導體封裝技術也相對地開發出許多高密度的半導體封裝形式。惟當一封裝構造大量生產時,一般係將複數個半導體晶片或電子元件固設於一基板上,隨後進行封膠製程,接著再對該封裝基板進行切割,以形成複數個封裝單元。然而,由於該封膠製程所使用之封膠材料與該封裝基板之熱膨脹係數不同,因此在封膠後的硬化(curing)製程中,該封裝基板與該封膠材料間係會隨溫度變化而產生不同的熱膨脹或熱收縮,導致該封裝基板產生熱應力而翹曲(warpage);且當硬化時的溫度越高或時間越長,該封裝基板所產生的翹曲就越大,使得後續切割製程難以進行。再者,該封裝基板上會產生一彎曲力矩施加在該半導體晶片或電子元件上,若該彎曲力矩太大,其甚至會造成該半導體晶片或電子元件的損壞。另,封裝過程為了防止基板及晶片因熱膨脹係數差距太大,造成變形量不同,進而發生翹曲情況,因此基板儘可能使用熱膨脹係數與晶片(主要成份為矽)較為接近的材料製作,使得基板材料的使用受到極大的限制,實有加以改良的必要。
是以,針對上述習知封裝結構因熱應力而產生翹曲所存在之問題點,如何開發一種更具理想實用性並兼顧經濟效益之抑制材料翹曲的方法,實為相關業者積極研發突破之目標及方向。
有鑑於此,發明人本於多年從事相關產品之製造開發與設
計經驗,針對上述之目標,詳加設計與審慎評估後,終得一確具實用性之本發明。
習知封裝結構由於在封膠製程所使
用之封膠材料與封裝基板之熱膨脹係數不同,導致該封裝基板因溫度變化產生熱應力而翹曲(warpage),嚴重影響產品之可靠性與品質,實有加以改良的必要。
為改善上述之問題,本發明提供一
種以壓差法抑制材料翹曲的方法,其步驟包括:a.準備複數個載板,各該載板具有相對之一第一表面及一第二表面。
b.準備複數個載板抵壓裝置,各該載板抵壓裝置相互平行設置於一處理框架內側之滑槽上,該載板抵壓裝置包含至少一氣體入口、至少一氣體出口、至少一氣囊及至少一氣體通道,至少一該氣體入口連接一氣壓源,該載板抵壓裝置具有相對之一上表面及一下表面,該下表面設置至少一該氣囊,該上表面對應至少一該氣囊放置至少一該載板,使至少一該第二表面和該上表面貼合,至少一該氣體通道一端結合至少一該氣體入口及至少一該氣體出口,另一端結合至少一該氣囊,該氣囊及該氣體通道相連通且形成一密閉空間,另,最上層之該載板抵壓裝置之上表面不放置載板。
c.各該載板及各該載板抵壓裝置於一處理腔室內,籠罩在該處理腔室的工作溫度及工作壓力中。
d.透過該氣壓源經由各該氣體入口對各該氣囊填充氣體,使氣體經由各該氣體通道流入各該氣囊,讓各該氣囊內部充滿氣體至第一預定壓力,使各該氣囊外部抵壓各該載板之第一表面,利用各該氣囊內部之第一預定壓力和該處理腔室的工作壓力所形成的壓力差,克服各該載板在該處理腔室的工作溫度下由於材料熱膨脹所產生的熱應力,有效抑制各該載板翹曲變形,其中各該氣囊內部之第一預定壓力大於該處理腔室的工作壓力,其壓力差大於0.01大氣壓(atm)。
e.各該載板在處理腔室內完成相關製程,令工作溫度下降
至初始溫度(室溫)、工作壓力下降至初始壓力(室壓),在各該氣體出口連接一真空產生器,透過該真空產生器,使各該氣體通道及各該氣囊內的壓力下降為真空壓力之第二預定壓力,藉由真空吸力將各該氣囊吸附在各該載板抵壓裝置之下表面,以便輕易地取出各該載板,其中第二預定壓力變化範圍之設定介於0.01托耳(Torr)至760托耳(Torr)之間,其中各該載板抵壓裝置上之氣體入口、氣體出口亦可合併形成氣體出入口,氣體出入口可同時連接該氣壓源及該真空產生器。另,當置入載板於載板抵壓裝置前亦可先執行本步驟,藉以挪出更多的作業空間,有效節省人力作業成本。
前述,該載板係為一印刷電路板(printed circuit board)、一有機基板、一玻璃基板、一金屬基板、一導電支架(lead frame)、一晶圓(wafer)、一矽中介層(silicon interposer)、一封裝體(package)至少其中之一者。
前述,該該載板抵壓裝置可滑移地套設於該處理框架內側之滑槽上。
前述,該載板抵壓裝置之下表面透過至少一密封結構固設至少一該氣囊。
前述,該氣壓源係為一空氣壓縮機或廠務氣體管路。
前述,該真空產生器係為一真空泵浦。
前述,該氣囊係以聚酰亞腔(polyimide)或鐵氟龍(Teflon)材質製成。
前述,在最底層之該載板抵壓裝置下方,更可相互平行設置一置物板於該處理框架內側之滑槽上,該置物板上表面對應最底層之該載板抵壓裝置上之至少一該氣囊放置至少一該載板,使至少一該第二表面和該置物板上表面貼合。
前述,該置物板可滑移地套設於該處理框架內側之滑槽上。
前述,處理腔室內工作溫度之設定介於室溫至攝氏800度的範圍,工作壓力變化範圍之設定介於1.01大氣壓(atm)至100大氣壓(atm)之間。
前述,第二預定壓力變化範圍之設定介於0.01托耳(Torr)至760托耳(Torr)之間。
前述,各該載板抵壓裝置可分別連接或共用氣壓源。
前述,各該該載板抵壓裝置可分別連接或共用真空產生器。
本發明之以壓差法抑制材料翹曲的
方法,可視製程需求調整各該載板抵壓裝置之間距及載板抵壓裝置的使用數量,有效提升製程彈性運用的靈活度;利用氣囊內部之第一預定壓力和處理腔室的工作壓力所形成的壓力差,對載板之第一表面施加作用力,有效抑制載板翹曲變形,大幅度提高了載板的生產品質及有效降低生產成本;藉由真空吸力將各該氣囊吸附在各該載板抵壓裝置之下表面,無需人力挪移各該氣囊,即可輕易地置入及取出各該載板,有效節省人力作業成本。
有關本發明所採用之技術、手段及其功效,茲舉一較佳實施例並配合圖式詳細說明於後,相信本發明上述之目的、構造及特徵,當可由之得一深入而具體的瞭解。
501-505‧‧‧步驟
10‧‧‧載板
11‧‧‧第一表面
12‧‧‧第二表面
20‧‧‧載板抵壓裝置
201‧‧‧上表面
202‧‧‧下表面
21‧‧‧氣體入口
22‧‧‧氣體出口
23‧‧‧氣囊
24‧‧‧密封結構
25‧‧‧氣體通道
26‧‧‧氣壓源
27‧‧‧置物板
28‧‧‧真空產生器
30‧‧‧處理框架
31‧‧‧滑槽
40‧‧‧處理腔室
第1圖係本發明之較佳實施例之以壓差法抑制材料翹曲的方法的流程圖。
第2圖係本發明之較佳實施例之氣囊抵壓狀態示意圖。
參閱第1至2圖所示,本發明係提供一種以壓差法抑制材料翹曲的方法,其步驟包括:a.(步驟501)準備複數個載板10,各該載板10具有相對之一第一表面11及一第二表面12,該載板10係為一印刷電路板(printed circuit board)、一有機基板、一玻璃基板、一金屬基板、一導電支架(lead frame)、一晶圓(wafer)、一矽中介層(silicon interposer)、一封裝體(package)至少其中之一者。
b.(步驟502)準備複數個載板抵壓裝置20,各該載板抵壓裝置20相互平行及可滑移地套設於一處理框架30內側之滑槽31上,該載板抵壓裝置20包含至少一氣體入口21、至少一氣體出口22、至少一氣囊23、至少一密封結構24及至少一氣體通道25,至少一該氣體入口21連接一氣壓源26,該氣壓源26係為一空氣壓縮機或廠務氣體管路,該載板抵壓裝置20具有相對之一上表面201及一下表面202,該下表面202透過至少
一該密封結構24設置至少一該氣囊23,該密封結構24例如為迫緊環及O形環等的組合,該上表面201對應至少一該氣囊23放置至少一該載板10,使至少一該第二表面12和該上表面201貼合,至少一該氣體通道25一端結合至少一該氣體入口21及至少一該氣體出口22,另一端結合至少一該氣囊23,該氣囊23係以聚酰亞胺(polyimide)或鐵氟龍(Teflon)材質製成,該氣囊23及該氣體通道25相連通且形成一密閉空間,其中最底層之該載板抵壓裝置20下方,更可相互平行及可滑移地套設一置物板27於該處理框架30內側之滑槽31上,該置物板27上表面對應最底層之該載板抵壓裝置20上之至少一該氣囊23放置至少一該載板10,使至少一該第二表面12和該置物板27上表面貼合,另,最上層之該載板抵壓裝置20之上表面201不放置載板10。
c.(步驟503)將各該載板10及各該載板抵壓裝置20於一處理腔室40內執行封膠後的硬化(curing)、除泡等相關製程,使其籠罩在該處理腔室40的工作溫度及工作壓力中,該處理腔室40內工作溫度之設定介於攝氏20度(室溫)至攝氏800度的範圍,工作壓力變化範圍之設定介於1.01大氣壓(atm)至100大氣壓(atm)之間。
d.(步驟504)透過該氣壓源26經由各該氣體入口21對各該氣囊23填充氣體,使氣體經由各該氣體通道25流入各該氣囊23,讓各該氣囊23內部充滿氣體至第一預定壓力,使各該氣囊23外部抵壓各該載板10之第一表面11,利用各該氣囊23內部之第一預定壓力和該處理腔室40的工作壓力所形成的壓力差,克服各該載板10在該處理腔室40的工作溫度下由於材料熱膨脹所產生的熱應力,有效抑制各該載板10翹曲變形,其中各該氣囊23內部之第一預定壓力大於該處理腔室40的工作壓力,其壓力差大於0.01大氣壓(atm)。
e.(步驟505)各該載板10在處理腔室40內完成相關製程,令工作溫度下降至初始溫度(室溫)、工作壓力下降至初始壓力(室壓),在各該氣體出口22連接一真空產生器28,該真空產生器28係為一真空泵浦,同時關閉該氣壓源26及啟動該真空產生器28,透過該真空產生器28,使各該氣體通道25及各該氣囊23內的壓力下降為真空壓力之第二預定壓力,藉由真空吸力將各該氣囊23吸附在各該載板抵壓裝置20之下表面202,以便
輕易地取出各該載板10,其中第二預定壓力變化範圍之設定介於0.01托耳(Torr)至760托耳(Torr)之間。另,在步驟502中當置入載板10於載板抵壓裝置20前亦可先執行本步驟,藉以挪出更多的作業空間,有效節省人力作業成本。
本發明之以壓差法抑制材料翹曲的方法,在步驟502中可視製程需求調整各該載板抵壓裝置20之間距及載板抵壓裝置20的使用數量,有效提升製程彈性運用的靈活度。
本發明之以壓差法抑制材料翹曲的方法,在步驟504中利用各該氣囊23內部之第一預定壓力和該處理腔室40的工作壓力所形成的壓力差,對各該載板10之第一表面11施加作用力,有效抑制至各該載板10翹曲變形,大幅度提高了載板10的生產品質及有效降低生產成本。
本發明之以壓差法抑制材料翹曲的方法,在步驟505中藉由真空吸力將各該氣囊23吸附在各該載板抵壓裝置20之下表面202,無需人力挪移各該氣囊23,即可輕易地取出各該載板10,有效節省人力作業成本。
前文係針對本發明之較佳實施例為本發明之技術特徵進行具體之說明;惟,熟悉此項技術之人士當可在不脫離本發明之精神與原則下對本發明進行變更與修改,而該等變更與修改,皆應涵蓋於如下申請專利範圍所界定之範疇中。
501-505‧‧‧步驟
Claims (10)
- 一種以壓差法抑制材料翹曲的方法,其步驟包括:(a)準備複數個載板,各該載板具有相對之一第一表面及一第二表面;(b)準備複數個載板抵壓裝置,各該載板抵壓裝置相互平行設置於一處理框架內側,該載板抵壓裝置包含至少一氣體入口、至少一氣體出口、至少一氣囊及至少一氣體通道,至少一該氣體入口連接一氣壓源,該載板抵壓裝置具有相對之一上表面及一下表面,該下表面設置至少一該氣囊,該上表面對應至少一該氣囊放置至少一該載板,至少一該氣體通道一端結合至少一該氣體入口及至少一該氣體出口,另一端結合至少一該氣囊,該氣囊及該氣體通道相連通且形成一密閉空間;(c)各該載板及各該載板抵壓裝置於一處理腔室內,籠罩在該處理腔室的工作溫度及工作壓力中;(d)透過該氣壓源對各該氣囊填充氣體,使氣體經由各該氣體通道流入各該氣囊,讓各該氣囊內部充滿氣體至第一預定壓力,使各該氣囊外部抵壓各該載板之第一表面,利用各該氣囊內部之第一預定壓力和該處理腔室的工作壓力所形成的壓力差,克服各該載板由於材料熱膨脹所產生的熱應力,抑制各該載板翹曲變形,其中各該氣囊內部之第一預定壓力大於該處理腔室的工作壓力,其壓力差大於0.01大氣壓(atm)。
- 如申請專利範圍第1項所述之以壓差法抑制材料翹曲的方法,更包括下列步驟:將各該氣體出口連接一真空產生器,透過該真空產生器,使各該氣體通道及各該氣囊內的壓力下降為真空壓力之第二預定壓力,藉由真空吸力將各該氣囊吸附在各該載板抵壓裝置之下表面,方便取出各該載板。
- 如申請專利範圍第1項所述之以壓差法抑制材料翹曲的方法,其中該載板抵壓裝置可滑移地套設於該處理框架內側。
- 如申請專利範圍第1項所述之以壓差法抑制材料翹曲的方法,其中該載板抵壓裝置之下表面透過至少一密封結構固設至少一該氣囊。
- 如申請專利範圍第1項所述之以壓差法抑制材料翹曲的方法,其中該載板係為一印刷電路板、一有機基板、一玻璃基板、一金屬基板、一導電支架、一晶圓、一矽中介層、一封裝體至少其中之一。
- 如申請專利範圍第1項所述之以壓差法抑制材料翹曲的方法,其中該氣囊係以聚酰亞胺(polyimide)或鐵氟龍(Teflon)材質製成。
- 如申請專利範圍第1項所述之以壓差法抑制材料翹曲的方法,其中該處理腔室內工作溫度之設定介於攝氏20度至攝氏800度的範圍,工作壓力變化範圍之設定介於1.01大氣壓(atm)至100大氣壓(atm)之間。
- 如申請專利範圍第1項所述之電子封裝結構之處理方法,其中在最底層之該載板抵壓裝置下方,更可相互平行設置 一置物板於該處理框架內側,該置物板上表面對應最底層之該載板抵壓裝置上之至少一該氣囊放置至少一該載板。
- 如申請專利範圍第8項所述之電子封裝結構之處理方法,其中該置物板可滑移地套設於該處理框架內側。
- 如申請專利範圍第2項所述之電子封裝結構之處理方法,其中該第二預定壓力變化範圍之設定介於0.01托耳(Torr)至760托耳(Torr)之間。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW105114374A TWI559410B (zh) | 2016-05-09 | 2016-05-09 | 以壓差法抑制材料翹曲的方法 |
CN201710220761.1A CN107359140B (zh) | 2016-05-09 | 2017-04-06 | 以压差法抑制材料翘曲的方法 |
KR1020170049652A KR102038192B1 (ko) | 2016-05-09 | 2017-04-18 | 차압법으로 재료의 뒤틀림을 억제하는 방법 |
US15/491,971 US10388613B2 (en) | 2016-05-09 | 2017-04-19 | Method for suppressing material warpage by means of pressure difference |
JP2017086817A JP6263297B2 (ja) | 2016-05-09 | 2017-04-26 | 差圧法の利用により材料の反りを抑制する方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW105114374A TWI559410B (zh) | 2016-05-09 | 2016-05-09 | 以壓差法抑制材料翹曲的方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
TWI559410B true TWI559410B (zh) | 2016-11-21 |
TW201740469A TW201740469A (zh) | 2017-11-16 |
Family
ID=57851743
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW105114374A TWI559410B (zh) | 2016-05-09 | 2016-05-09 | 以壓差法抑制材料翹曲的方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US10388613B2 (zh) |
JP (1) | JP6263297B2 (zh) |
KR (1) | KR102038192B1 (zh) |
CN (1) | CN107359140B (zh) |
TW (1) | TWI559410B (zh) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102563929B1 (ko) * | 2018-03-09 | 2023-08-04 | 삼성전자주식회사 | 반도체 다이들의 개별화 방법 및 반도체 패키지의 제조 방법 |
CN109473380A (zh) * | 2018-10-26 | 2019-03-15 | 志圣科技(广州)有限公司 | 晶圆加工机台及其加工方法 |
CN109742191B (zh) * | 2019-01-14 | 2020-10-02 | 浙江晶科能源有限公司 | 一种太阳能电池的制作方法及太阳能电池烧结装置 |
WO2020185016A1 (ko) | 2019-03-12 | 2020-09-17 | 에스케이씨 주식회사 | 패키징 기판 및 이를 포함하는 반도체 장치 |
EP3916772A4 (en) | 2019-03-12 | 2023-04-05 | Absolics Inc. | PACKAGING SUBSTRATE AND SEMICONDUCTOR DEVICE WITH IT |
JP7087205B2 (ja) | 2019-03-29 | 2022-06-20 | アブソリックス インコーポレイテッド | 半導体用パッケージングガラス基板、半導体用パッケージング基板及び半導体装置 |
KR20220089715A (ko) | 2019-08-23 | 2022-06-28 | 앱솔릭스 인코포레이티드 | 패키징 기판 및 이를 포함하는 반도체 장치 |
CN113449239A (zh) * | 2020-03-24 | 2021-09-28 | 上海梅山钢铁股份有限公司 | 一种镀铝锌机组带钢表面风机压力单因素对c翘影响预报方法 |
CN112151418B (zh) * | 2020-09-11 | 2024-04-05 | 安徽龙芯微科技有限公司 | 一种硅基转接板的封装机构及其封装方法 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020171129A1 (en) * | 2001-03-29 | 2002-11-21 | Huang Chien Ping | Ball grid array substrate strip with warpage-preventive linkage structure |
US20040107569A1 (en) * | 2002-12-05 | 2004-06-10 | John Guzek | Metal core substrate packaging |
US20060180944A1 (en) * | 2004-09-02 | 2006-08-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Flip chip ball grid array package with constraint plate |
US20080222884A1 (en) * | 2007-03-14 | 2008-09-18 | Honeywell International Inc. | Packaging for chip-on-board pressure sensor |
US20110018130A1 (en) * | 2009-07-24 | 2011-01-27 | Murata Manufacturing Co., Ltd. | Semiconductor package and semiconductor package module |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0569996A (ja) | 1991-09-05 | 1993-03-23 | Smc Corp | 真空ユニツト |
JPH10275852A (ja) | 1997-03-31 | 1998-10-13 | Shin Etsu Handotai Co Ltd | 半導体基板の接着方法および接着装置 |
JP3098003B2 (ja) * | 1998-09-24 | 2000-10-10 | 日清紡績株式会社 | 太陽電池におけるラミネート装置 |
KR100676314B1 (ko) * | 1999-12-17 | 2007-01-31 | 삼성전자주식회사 | 반도체 패키지 경화 장치 및 그를 이용한 경화 방법 |
JP4535937B2 (ja) | 2005-05-27 | 2010-09-01 | 大日本印刷株式会社 | 基板収納体 |
US8137498B2 (en) * | 2005-08-30 | 2012-03-20 | Rockwell Collins Inc. | System and method for completing lamination of rigid-to-rigid substrates by the controlled application of pressure |
JP2008126407A (ja) * | 2006-11-16 | 2008-06-05 | Npc Inc | ラミネート装置 |
JP2008137673A (ja) * | 2006-11-30 | 2008-06-19 | Optrex Corp | 表示基板用搬送ケース |
JP2011001106A (ja) * | 2009-06-19 | 2011-01-06 | Panasonic Corp | 半導体ウエハ収納容器 |
JP6178683B2 (ja) | 2013-09-25 | 2017-08-09 | 芝浦メカトロニクス株式会社 | 吸着ステージ、貼合装置、および貼合方法 |
JP2015079832A (ja) | 2013-10-16 | 2015-04-23 | 東京エレクトロン株式会社 | 薄基板の矯正方法および矯正装置 |
-
2016
- 2016-05-09 TW TW105114374A patent/TWI559410B/zh active
-
2017
- 2017-04-06 CN CN201710220761.1A patent/CN107359140B/zh active Active
- 2017-04-18 KR KR1020170049652A patent/KR102038192B1/ko active IP Right Grant
- 2017-04-19 US US15/491,971 patent/US10388613B2/en active Active
- 2017-04-26 JP JP2017086817A patent/JP6263297B2/ja active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020171129A1 (en) * | 2001-03-29 | 2002-11-21 | Huang Chien Ping | Ball grid array substrate strip with warpage-preventive linkage structure |
US20040107569A1 (en) * | 2002-12-05 | 2004-06-10 | John Guzek | Metal core substrate packaging |
US20060180944A1 (en) * | 2004-09-02 | 2006-08-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Flip chip ball grid array package with constraint plate |
US20080222884A1 (en) * | 2007-03-14 | 2008-09-18 | Honeywell International Inc. | Packaging for chip-on-board pressure sensor |
US20110018130A1 (en) * | 2009-07-24 | 2011-01-27 | Murata Manufacturing Co., Ltd. | Semiconductor package and semiconductor package module |
Also Published As
Publication number | Publication date |
---|---|
CN107359140B (zh) | 2019-11-22 |
CN107359140A (zh) | 2017-11-17 |
KR20170126394A (ko) | 2017-11-17 |
US20170323856A1 (en) | 2017-11-09 |
KR102038192B1 (ko) | 2019-10-29 |
TW201740469A (zh) | 2017-11-16 |
JP6263297B2 (ja) | 2018-01-17 |
JP2017204633A (ja) | 2017-11-16 |
US10388613B2 (en) | 2019-08-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI559410B (zh) | 以壓差法抑制材料翹曲的方法 | |
JP5587962B2 (ja) | ガス加圧により載置板の反りを抑制する載置板固定方法 | |
JP5189194B2 (ja) | 真空加熱接合装置及び真空加熱接合方法 | |
US6128066A (en) | Method of manufacturing liquid crystal panels with simultaneously evacuating and pressurizing and manufacturing apparatus | |
JP3041221B2 (ja) | インサートを用いずにキャビティを形成する装置および方法 | |
EP3348400A2 (en) | System and method for vacuum film lamination | |
JP7102157B2 (ja) | 切断装置及び切断品の製造方法 | |
TWI455244B (zh) | 用於重工製程之夾持治具及設備 | |
CN103946006A (zh) | 层压方法及层压装置 | |
KR101744371B1 (ko) | 시트 부착 장치 및 부착 방법 | |
US9227261B2 (en) | Vacuum carriers for substrate bonding | |
CN115483138A (zh) | 压膜结构、压膜系统及压膜方法 | |
JP2010258274A (ja) | 貼り合わせ方法及び装置 | |
CN108511363B (zh) | 一种键合装置 | |
JP2011135108A (ja) | 半導体装置の製造方法 | |
JP2011222633A5 (ja) | 基板貼り合わせ装置、積層半導体の製造方法、積層半導体及び基板貼り合わせ方法 | |
WO2017006682A1 (ja) | 加圧装置およびそれを備えた個片化装置、樹脂成形装置、デバイス製造装置、ならびに加圧方法およびそれを含む個片化方法、樹脂成形方法、デバイス製造方法 | |
TWI499098B (zh) | 用於模塑電子器件的襯底載體 | |
JP4044906B2 (ja) | 真空プレス貼着装置 | |
JP2020526023A (ja) | 真空引き装置及び真空引き方法 | |
JP5516237B2 (ja) | 回路モジュールの製造方法 | |
TW202130489A (zh) | 貼膜機及貼膜方法 | |
JP2972661B2 (ja) | 熱圧着装置 | |
CN114496891A (zh) | 一种静电卡盘的集成装置及制造方法 | |
JP2013153012A (ja) | 電子部品モジュールの製造方法 |