JP2009532917A - 半導体デバイス内のアルミニウム端子パッド材料を除去する方法及び構造体 - Google Patents
半導体デバイス内のアルミニウム端子パッド材料を除去する方法及び構造体 Download PDFInfo
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- JP2009532917A JP2009532917A JP2009504439A JP2009504439A JP2009532917A JP 2009532917 A JP2009532917 A JP 2009532917A JP 2009504439 A JP2009504439 A JP 2009504439A JP 2009504439 A JP2009504439 A JP 2009504439A JP 2009532917 A JP2009532917 A JP 2009532917A
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Abstract
【解決手段】 遠後工程(far back end of line(FBEOL))半導体デバイス形成の方法は、半導体ウェハ(106)の上部内に端子銅パッド(104)を形成するステップと、端子銅パッドの上に絶縁スタック(114)を形成するステップと、端子銅パッドを保護する絶縁スタックの底部キャップ層を残すように絶縁スタックの一部分の中に端子ビア(116)をパターン付けし開口するステップとを含む。有機保護層(126)は、絶縁スタックの上に形成されてパターン付けされ、そして端子銅パッドの上の底部キャップ層(118)は除去される。ボール制限メタラジ(BLM)スタック(128)は、有機保護層及び端子銅パッドの上に堆積され、はんだボール接続(108)は、BLMスタックのパターン付けされた部分の上に形成される。
【選択図】 図11
Description
102:端子金属(TD)アルミニウム・パッド構造部
104:端子銅層(銅パッド)
106:半導体ウェハ
108:はんだボール接続
110:絶縁層
112:垂直酸化物ピラー
114:絶縁スタック
116:TDビア(端子ビア)
118:SiC(N,H)キャップ層
120:酸化物層
122:窒化シリコン層
124:薄いライナ・スタック
126:感光性ポリイミド(PSPI)層
128:BLMスタック
300:TDアルミニウムのない構造体
Claims (14)
- 遠後工程(far back end of line(FBEOL))半導体デバイス形成の方法であって、
半導体ウェハ(106)の上部内に端子銅パッド(104)を形成するステップと、
前記端子銅パッドの上に絶縁スタック(114)を形成するステップと、
前記端子銅パッドを保護する前記絶縁スタックの底部キャップ層(118)を残すように、前記絶縁スタックの一部分の内部に端子ビア(116)をパターン付けし開口するステップと、
前記絶縁スタックの上に有機保護層(126)を形成しパターン付けするステップと、
前記端子銅パッドの上の前記底部キャップ層を除去するステップと、
前記有機保護層及び前記端子銅パッドの上に、ボール制限メタラジ(BLM)スタッ
ク(128)を堆積させるステップと、
前記BLMスタックのパターン付けされた部分の上に、はんだボール接続(108)を形成するステップと
を含む方法。 - 前記底部キャップ層は、窒素ドープの水素化炭化シリコン・キャップ層を含む、請求項1に記載の方法。
- 前記窒素ドープの水素化炭化シリコン・キャップ層は、前記有機保護層の硬化後に化学エッチングによって除去される、請求項2に記載の方法。
- 前記窒素ドープの水素化炭化シリコン・キャップ層は、前記BLMスタックを前記堆積させるステップの前に、バック・スパッタ・エッチングによって除去される、請求項2に記載の方法。
- 前記端子銅層をプリフラックス(organic solderability preservative(OSP))層でコーティングするステップと、前記OSP層を、前記BLMスタックを前記堆積させるステップの前にバック・スパッタ・エッチングにより除去するステップとをさらに含む、請求項2に記載の方法。
- 前記有機保護層及び前記端子銅層を、前記端子ビアをパターン付けするステップに続いて、導電性酸化防止障壁層でコーティングするステップと、その後に前記有機保護層から前記障壁層の部分を除去するステップとをさらに含む、請求項2に記載の方法。
- 前記有機保護層はポリイミド層をさらに含む、請求項1に記載の方法。
- 前記絶縁スタックは、窒素ドープの水素化炭化シリコン・キャップ層(118)と、前記窒素ドープの水素化炭化シリコン・キャップ層の上に堆積させた酸化シリコン層(120)と、前記酸化シリコン層の上に堆積させた窒化シリコン層(122)とをさらに含む、請求項1に記載の方法。
- 半導体デバイスであって、
半導体ウェハ(106)の上部内に形成された端子銅パッド(104)と、
前記端子銅パッドの上に形成された絶縁スタック(114)と、
前記端子銅パッドの直接上及びパターン付けされた有機保護層(126)の側壁上に形成されたボール制限メタラジ(BLM)スタック(128)と、
前記BLMスタックのパターン付けされた部分の上に形成されたはんだボール接続(108)と
を含むデバイス。 - 前記端子銅パッドの上に形成された底部キャップ層(118)をさらに含む、請求項9に記載のデバイス。
- 前記底部キャップ層は、窒素ドープの水素化炭化シリコン・キャップ層を含む、請求項10に記載のデバイス。
- 前記有機保護層はポリイミド層をさらに含む、請求項9に記載のデバイス。
- 前記端子銅パッドと前記有機保護層との間に形成された絶縁スタック(114)をさらに含む、請求項9に記載のデバイス。
- 前記絶縁スタックは、窒素ドープの水素化炭化シリコン・キャップ層(118)と、前記窒素ドープの水素化炭化シリコン・キャップ層の上に堆積させた酸化シリコン層(129)と、前記酸化シリコン層の上に堆積させた窒化シリコン層(122)とをさらに含む、請求項13に記載の方法。
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US11/308,539 US7375021B2 (en) | 2006-04-04 | 2006-04-04 | Method and structure for eliminating aluminum terminal pad material in semiconductor devices |
US11/308,539 | 2006-04-04 | ||
PCT/US2007/065929 WO2007115292A2 (en) | 2006-04-04 | 2007-04-04 | Method and structure for eliminating aluminum terminal pad material in semiconductor devices |
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EP (1) | EP2008301A4 (ja) |
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US8563336B2 (en) * | 2008-12-23 | 2013-10-22 | International Business Machines Corporation | Method for forming thin film resistor and terminal bond pad simultaneously |
US8227918B2 (en) * | 2009-09-16 | 2012-07-24 | International Business Machines Corporation | Robust FBEOL and UBM structure of C4 interconnects |
US8482125B2 (en) | 2010-07-16 | 2013-07-09 | Qualcomm Incorporated | Conductive sidewall for microbumps |
US8580672B2 (en) * | 2011-10-25 | 2013-11-12 | Globalfoundries Inc. | Methods of forming bump structures that include a protection layer |
US9842810B1 (en) | 2016-06-08 | 2017-12-12 | Globalfoundries Inc. | Tiled-stress-alleviating pad structure |
CN107481976B (zh) * | 2016-06-08 | 2019-12-17 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制作方法和电子装置 |
CN107611036A (zh) * | 2016-07-12 | 2018-01-19 | 碁鼎科技秦皇岛有限公司 | 封装基板及其制作方法、封装结构 |
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