JP2009524254A - 界面キャップ構造体を用いて最終レベル銅・c4間接続部を形成する方法 - Google Patents
界面キャップ構造体を用いて最終レベル銅・c4間接続部を形成する方法 Download PDFInfo
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- JP2009524254A JP2009524254A JP2008551511A JP2008551511A JP2009524254A JP 2009524254 A JP2009524254 A JP 2009524254A JP 2008551511 A JP2008551511 A JP 2008551511A JP 2008551511 A JP2008551511 A JP 2008551511A JP 2009524254 A JP2009524254 A JP 2009524254A
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- interfacial conductive
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- 238000000034 method Methods 0.000 title claims abstract description 27
- 239000010949 copper Substances 0.000 claims abstract description 44
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 38
- 229910052802 copper Inorganic materials 0.000 claims abstract description 38
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 23
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 23
- 230000008569 process Effects 0.000 claims abstract description 13
- 239000004065 semiconductor Substances 0.000 claims abstract description 10
- 238000007772 electroless plating Methods 0.000 claims abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 24
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 16
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 16
- 235000012239 silicon dioxide Nutrition 0.000 claims description 12
- 239000000377 silicon dioxide Substances 0.000 claims description 12
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- 238000004140 cleaning Methods 0.000 claims description 11
- 229920001721 polyimide Polymers 0.000 claims description 11
- 238000005272 metallurgy Methods 0.000 claims description 5
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- 238000009792 diffusion process Methods 0.000 description 7
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- 229910052751 metal Inorganic materials 0.000 description 5
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000011065 in-situ storage Methods 0.000 description 3
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- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
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- 238000000059 patterning Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- -1 region Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000012459 cleaning agent Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
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- 150000002170 ethers Chemical class 0.000 description 1
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- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920000412 polyarylene Polymers 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 238000001029 thermal curing Methods 0.000 description 1
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Abstract
【解決手段】 本発明は、実質的にアルミニウムを含まない最終レベル銅・C4間接続部を含む半導体デバイスの製造方法に関する。具体的には、最終レベル銅・C4間接続部は、CoWP、NiMoP、NiMoB、NiReP、NiWP及びこれらの組み合わせを含む界面キャップ構造体(30)を含む。界面キャップ構造体は、少なくとも1つのCoWP層を含むことが好ましい。こうしたCoWP層は、選択的な無電解めっきプロセスによって、最終レベル銅相互接続部(22)の上に、容易に形成することができる。
【選択図】 図9
Description
最終レベル誘電体層内に埋め込まれた最終レベル銅相互接続部を含む半導体デバイスを準備するステップと、
最終レベル銅相互接続部を選択的に覆う界面導電性キャップ構造体を形成するステップであって、界面導電性キャップ構造体は、CoWP、NiMoP、NiMoB、NiReP、NiWP、又はこれらの組み合わせを含む、ステップと、
界面導電性キャップ構造体及び最終レベル誘電体層の上に第1の誘電体キャップ層を形成するステップと、
第1の誘電体キャップ層の上に少なくとも1つの付加的な誘電体キャップ層を形成するステップと、
第1の誘電体キャップ層及び少なくとも1つの付加的な誘電体キャップ層を通るビアを形成して、界面導電性キャップ構造体を露出させるステップと、
界面導電性キャップ構造体の上に、ビア内に少なくとも1つのボール制限メタラジ(BLM)層を形成するステップと、
少なくとも1つのBLM層の上に少なくとも1つの制御崩壊チップ接続部(C4)を形成するステップと
を含む方法に関する。
このような界面導電性キャップ構造体は、窒化シリコンを含み、約100Åから約300Åまでの厚さであることが好ましい、第1の誘電体キャップ層内に埋め込むことができる。
最終レベル誘電体層内に埋め込まれた最終レベル銅相互接続部を含む半導体デバイスを準備するステップと、
最終レベル銅相互接続部を選択的に覆う界面導電性キャップ構造体を形成するステップと、
界面導電性キャップ構造体及び最終レベル誘電体層の上に第1の誘電体キャップ層を形成するステップと、
第1の誘電体キャップ層の上に少なくとも1つの付加的な誘電体キャップ層を形成するステップと、
少なくとも1つの付加的な誘電体キャップ層の部分を選択的に除去して、第1の誘電体キャップ層を露出させるステップと、
第1の誘電体キャップ層の露出された部分を選択的に除去し、少なくとも1つの付加的な誘電体キャップ層で停止する、インサイチュ(in-situ)スパッタ洗浄を行なうステップと、
界面導電性キャップ構造体の上に少なくとも1つのボール制限メタラジ(BLM)層を形成するステップと、
少なくとも1つのBLM層の上に少なくとも1つの制御崩壊チップ接続部(C4)を形成するステップと
を含む方法に関する。
米国特許出願公開第2005/016575 A1号として2005年7月28日に公開され、2004年1月22日に出願された、「INTEGRATION OF HIGH PERFORMANCE COPPER INDUCTORS WITH BOND PADS」という名称の特許文献1。
20:最終レベル誘電体層
22:最終レベル相互接続部
30:界面導電性キャップ層
32:薄い誘電体キャップ層
40:二酸化シリコン層
50:窒化シリコン層
60:感光性ポリイミド層
62:コンタクト開口部
62’:トレンチ
70:ボール制限メタラジ(BLM)
80:C4はんだボール
Claims (12)
- 最終レベル誘電体層(20)内に埋め込まれた最終レベル銅相互接続部(22)を含む半導体デバイスを準備するステップと、
前記最終レベル銅相互接続部(22)を選択的に覆う界面導電性キャップ構造体(30)を形成するステップであって、前記界面導電性キャップ構造体は、CoWP、NiMoP、NiMoB、NiReP、NiWP、又はこれらの組み合わせを含む、ステップと、
前記界面導電性キャップ構造体(30)及び前記最終レベル誘電体層(20)の上に第1の誘電体キャップ層(32)を形成するステップと、
前記第1の誘電体キャップ層(32)の上に少なくとも1つの付加的な誘電体キャップ層(40、50、60)を形成するステップと、
前記第1の誘電体キャップ層(32)及び前記少なくとも1つの付加的な誘電体キャップ層(40、50、60)を通るビア(62‘)を形成して、前記界面導電性キャップ構造体(30)を露出させるステップと、
前記界面導電性キャップ構造体(30)の上に、前記ビア内に少なくとも1つのボール制限メタラジ(BLM)層(70)を形成するステップと、
前記少なくとも1つのBLM層の上に少なくとも1つの制御崩壊チップ接続部(C4)(80)を形成するステップと
を含む方法。 - 前記界面導電性キャップ構造体(30)は、アルミニウムを含んでいない、請求項1に記載の方法。
- 前記界面導電性キャップ構造体(30)は、200Åから1000Åまでの範囲の厚さを有するCoWP層を含む、請求項1に記載の方法。
- 前記界面導電性キャップ構造体(30)は、前記第1の誘電体キャップ層(32)内に埋め込まれている、請求項1に記載の方法。
- 前記第1の誘電体キャップ層(32)は、窒化シリコンを含み、100Åから300Åまでの範囲の厚さを有する、請求項1に記載の方法。
- 前記最終レベル銅相互接続部(22)、前記界面導電性キャップ構造体(30)、前記少なくとも1つのBLM層(70)及び前記少なくとも1つのC4接続部は、前記第1の誘電体キャップ層(32)及び前記少なくとも1つの付加的な誘電体キャップ層を通って延びる導電性経路を形成する、請求項1に記載の方法。
- 前記第1の誘電体キャップ層(32)の上に、二酸化シリコン層、窒化シリコン層及び感光性ポリイミド層を含む前記少なくとも3つの付加的な誘電体キャップ層が形成される、請求項1に記載の方法。
- 前記最終レベル銅相互接続部(22)は太線を含む、請求項1に記載の方法。
- 前記最終レベル誘電体層(20)はフッ化ケイ酸塩ガラスを含む、請求項1に記載の方法。
- 前記界面導電性キャップ構造体(30)は、選択的な無電解めっきによって形成される、請求項1に記載の方法。
- 前記ビアは、最初に前記少なくとも1つの付加的な誘電体キャップ層(40、50、60)の部分を選択的に除去して前記第1の誘電体キャップ層(32)を露出させ、次に前記第1の誘電体キャップ層(32)の露出された部分を選択的に除去し、前記界面導電性キャップ構造体(30)で停止することによって形成される、請求項1に記載の方法。
- 前記第1の誘電体キャップ層(32)の前記部分は、事前BLMスパッタ洗浄プロセスによって選択的に除去される、請求項11に記載の方法。
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PCT/US2007/060615 WO2007084907A2 (en) | 2006-01-18 | 2007-01-17 | Method for fabricating last level copper-to-c4 connection with interfacial cap structure |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015092548A (ja) * | 2013-09-16 | 2015-05-14 | エスピーティーエス テクノロジーズ リミティド | 半導体構造のプレクリーニング |
JP2015173256A (ja) * | 2014-03-11 | 2015-10-01 | インテル コーポレイション | 集積回路パッケージ |
JP2016525274A (ja) * | 2013-08-06 | 2016-08-22 | クアルコム,インコーポレイテッド | ダイ上の積層再分配層 |
CN110574158A (zh) * | 2017-05-09 | 2019-12-13 | 国际商业机器公司 | 具有自对准焊料凸块的衬底通孔 |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7785935B2 (en) * | 2007-11-13 | 2010-08-31 | Qimonda Ag | Manufacturing method for forming an integrated circuit device and corresponding integrated circuit device |
US7868453B2 (en) * | 2008-02-15 | 2011-01-11 | International Business Machines Corporation | Solder interconnect pads with current spreading layers |
US8241547B2 (en) | 2008-10-02 | 2012-08-14 | California Institute Of Technology | Lithographically defined adhesion microstructures |
US8932956B2 (en) * | 2012-12-04 | 2015-01-13 | International Business Machines Corporation | Far back end of the line stack encapsulation |
US8846529B2 (en) * | 2013-01-10 | 2014-09-30 | International Business Machines Corporation | Electroless plating of cobalt alloys for on chip inductors |
US8956975B2 (en) * | 2013-02-28 | 2015-02-17 | International Business Machines Corporation | Electroless plated material formed directly on metal |
US8937009B2 (en) * | 2013-04-25 | 2015-01-20 | International Business Machines Corporation | Far back end of the line metallization method and structures |
US8994173B2 (en) | 2013-06-26 | 2015-03-31 | International Business Machines Corporation | Solder bump connection and method of making |
US9159547B2 (en) * | 2013-09-17 | 2015-10-13 | Deca Technologies Inc. | Two step method of rapid curing a semiconductor polymer layer |
US10204803B2 (en) * | 2013-09-17 | 2019-02-12 | Deca Technologies Inc. | Two step method of rapid curing a semiconductor polymer layer |
US20150206798A1 (en) * | 2014-01-17 | 2015-07-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect Structure And Method of Forming |
US11764153B1 (en) | 2022-07-28 | 2023-09-19 | Chun-Ming Lin | Interconnect structure and manufacturing method for the same |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005210121A (ja) * | 2004-01-22 | 2005-08-04 | Internatl Business Mach Corp <Ibm> | ボンディング・パッドと高性能銅インダクタの集積化 |
JP2005277390A (ja) * | 2004-02-27 | 2005-10-06 | Handotai Rikougaku Kenkyu Center:Kk | 半導体装置及びその製造方法 |
Family Cites Families (75)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2445629A1 (fr) * | 1978-12-27 | 1980-07-25 | Thomson Csf | Antenne commune pour radar primaire et radar secondaire |
EP0101024B1 (en) * | 1982-08-09 | 1988-11-09 | Kabushiki Kaisha Meidensha | Contact material of vacuum interrupter and manufacturing process therefor |
JPS6067634A (ja) * | 1983-09-24 | 1985-04-18 | Meidensha Electric Mfg Co Ltd | 真空インタラプタの電極材料とその製造方法 |
US4755904A (en) * | 1986-06-06 | 1988-07-05 | The Boeing Company | Lightning protection system for conductive composite material structure |
US5194161A (en) * | 1989-09-25 | 1993-03-16 | Board Of Regents, The University Of Texas System | Materials and methods for enhanced photocatalyzation of organic compounds with palladium |
US5300813A (en) * | 1992-02-26 | 1994-04-05 | International Business Machines Corporation | Refractory metal capped low resistivity metal conductor lines and vias |
US5602365A (en) * | 1992-10-02 | 1997-02-11 | Lucent Technologies Inc. | Microwave duplexer and component |
US5674787A (en) * | 1996-01-16 | 1997-10-07 | Sematech, Inc. | Selective electroless copper deposited interconnect plugs for ULSI applications |
US5847327A (en) * | 1996-11-08 | 1998-12-08 | W.L. Gore & Associates, Inc. | Dimensionally stable core for use in high density chip packages |
US5695810A (en) * | 1996-11-20 | 1997-12-09 | Cornell Research Foundation, Inc. | Use of cobalt tungsten phosphide as a barrier material for copper metallization |
US6437441B1 (en) * | 1997-07-10 | 2002-08-20 | Kawasaki Microelectronics, Inc. | Wiring structure of a semiconductor integrated circuit and a method of forming the wiring structure |
US6660656B2 (en) * | 1998-02-11 | 2003-12-09 | Applied Materials Inc. | Plasma processes for depositing low dielectric constant films |
US6287990B1 (en) * | 1998-02-11 | 2001-09-11 | Applied Materials, Inc. | CVD plasma assisted low dielectric constant films |
US6054379A (en) * | 1998-02-11 | 2000-04-25 | Applied Materials, Inc. | Method of depositing a low k dielectric with organo silane |
US6303523B2 (en) * | 1998-02-11 | 2001-10-16 | Applied Materials, Inc. | Plasma processes for depositing low dielectric constant films |
US6245663B1 (en) * | 1998-09-30 | 2001-06-12 | Conexant Systems, Inc. | IC interconnect structures and methods for making same |
US6093628A (en) * | 1998-10-01 | 2000-07-25 | Chartered Semiconductor Manufacturing, Ltd | Ultra-low sheet resistance metal/poly-si gate for deep sub-micron CMOS application |
US6457234B1 (en) | 1999-05-14 | 2002-10-01 | International Business Machines Corporation | Process for manufacturing self-aligned corrosion stop for copper C4 and wirebond |
US6174812B1 (en) * | 1999-06-08 | 2001-01-16 | United Microelectronics Corp. | Copper damascene technology for ultra large scale integration circuits |
US6342733B1 (en) * | 1999-07-27 | 2002-01-29 | International Business Machines Corporation | Reduced electromigration and stressed induced migration of Cu wires by surface coating |
US6596624B1 (en) | 1999-07-31 | 2003-07-22 | International Business Machines Corporation | Process for making low dielectric constant hollow chip structures by removing sacrificial dielectric material after the chip is joined to a chip carrier |
JP4554011B2 (ja) | 1999-08-10 | 2010-09-29 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置の製造方法 |
US6413854B1 (en) * | 1999-08-24 | 2002-07-02 | International Business Machines Corp. | Method to build multi level structure |
US6184138B1 (en) * | 1999-09-07 | 2001-02-06 | Chartered Semiconductor Manufacturing Ltd. | Method to create a controllable and reproducible dual copper damascene structure |
US6251786B1 (en) * | 1999-09-07 | 2001-06-26 | Chartered Semiconductor Manufacturing Ltd. | Method to create a copper dual damascene structure with less dishing and erosion |
US6040243A (en) * | 1999-09-20 | 2000-03-21 | Chartered Semiconductor Manufacturing Ltd. | Method to form copper damascene interconnects using a reverse barrier metal scheme to eliminate copper diffusion |
US6153935A (en) * | 1999-09-30 | 2000-11-28 | International Business Machines Corporation | Dual etch stop/diffusion barrier for damascene interconnects |
US6610151B1 (en) * | 1999-10-02 | 2003-08-26 | Uri Cohen | Seed layers for interconnects and methods and apparatus for their fabrication |
US6274499B1 (en) * | 1999-11-19 | 2001-08-14 | Chartered Semiconductor Manufacturing Ltd. | Method to avoid copper contamination during copper etching and CMP |
US6136680A (en) * | 2000-01-21 | 2000-10-24 | Taiwan Semiconductor Manufacturing Company | Methods to improve copper-fluorinated silica glass interconnects |
TW486801B (en) * | 2000-04-07 | 2002-05-11 | Taiwan Semiconductor Mfg | Method of fabricating dual damascene structure |
ATE399752T1 (de) * | 2000-04-24 | 2008-07-15 | Toho Titanium Co Ltd | Feste katalysatorkomponente und katalysaor für die olefinpolymerisation |
US6352921B1 (en) * | 2000-07-19 | 2002-03-05 | Chartered Semiconductor Manufacturing Ltd. | Use of boron carbide as an etch-stop and barrier layer for copper dual damascene metallization |
JP2002110679A (ja) | 2000-09-29 | 2002-04-12 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
US6503834B1 (en) * | 2000-10-03 | 2003-01-07 | International Business Machines Corp. | Process to increase reliability CuBEOL structures |
US6750113B2 (en) * | 2001-01-17 | 2004-06-15 | International Business Machines Corporation | Metal-insulator-metal capacitor in copper |
US6709874B2 (en) * | 2001-01-24 | 2004-03-23 | Infineon Technologies Ag | Method of manufacturing a metal cap layer for preventing damascene conductive lines from oxidation |
TW480662B (en) | 2001-01-29 | 2002-03-21 | Macronix Int Co Ltd | Method for forming dual damascene |
US6534863B2 (en) * | 2001-02-09 | 2003-03-18 | International Business Machines Corporation | Common ball-limiting metallurgy for I/O sites |
US6554002B2 (en) * | 2001-02-21 | 2003-04-29 | United Microelectronics Corp. | Method for removing etching residues |
US7192645B2 (en) | 2001-02-26 | 2007-03-20 | Dielectric Systems, Inc. | Porous low E (<2.0) thin films by transport co-polymerization |
US6528185B2 (en) * | 2001-02-28 | 2003-03-04 | Hong Kong Polytechnic University | Cobalt-tungsten-phosphorus alloy diffusion barrier coatings, methods for their preparation, and their use in plated articles |
US6724069B2 (en) * | 2001-04-05 | 2004-04-20 | International Business Machines Corporation | Spin-on cap layer, and semiconductor device containing same |
EP1265468B1 (en) * | 2001-06-05 | 2011-12-28 | Kabushiki Kaisha Toshiba | Method for manufacturing a composite member |
US6544698B1 (en) * | 2001-06-27 | 2003-04-08 | University Of South Florida | Maskless 2-D and 3-D pattern generation photolithography |
US6764796B2 (en) * | 2001-06-27 | 2004-07-20 | University Of South Florida | Maskless photolithography using plasma displays |
GB2379795B (en) * | 2001-09-13 | 2004-02-18 | Univ Glasgow | Method of manufacturing optical devices and related improvements |
JP2003142579A (ja) * | 2001-11-07 | 2003-05-16 | Hitachi Ltd | 半導体装置の製造方法および半導体装置 |
US6589881B2 (en) * | 2001-11-27 | 2003-07-08 | United Microelectronics Corp. | Method of forming dual damascene structure |
US20030134499A1 (en) | 2002-01-15 | 2003-07-17 | International Business Machines Corporation | Bilayer HDP CVD / PE CVD cap in advanced BEOL interconnect structures and method thereof |
US20030134495A1 (en) | 2002-01-15 | 2003-07-17 | International Business Machines Corporation | Integration scheme for advanced BEOL metallization including low-k cap layer and method thereof |
US6737747B2 (en) | 2002-01-15 | 2004-05-18 | International Business Machines Corporation | Advanced BEOL interconnect structures with low-k PE CVD cap layer and method thereof |
US6732908B2 (en) * | 2002-01-18 | 2004-05-11 | International Business Machines Corporation | High density raised stud microjoining system and methods of fabricating the same |
US6756294B1 (en) * | 2002-01-30 | 2004-06-29 | Taiwan Semiconductor Manufacturing Company | Method for improving bump reliability for flip chip devices |
US6531386B1 (en) * | 2002-02-08 | 2003-03-11 | Chartered Semiconductor Manufacturing Ltd. | Method to fabricate dish-free copper interconnects |
US6821324B2 (en) * | 2002-06-19 | 2004-11-23 | Ramot At Tel-Aviv University Ltd. | Cobalt tungsten phosphorus electroless deposition process and materials |
US6617690B1 (en) * | 2002-08-14 | 2003-09-09 | Ibm Corporation | Interconnect structures containing stress adjustment cap layer |
US6827868B2 (en) * | 2002-11-27 | 2004-12-07 | International Business Machines Corporation | Thinning of fuse passivation after C4 formation |
US7825516B2 (en) | 2002-12-11 | 2010-11-02 | International Business Machines Corporation | Formation of aligned capped metal lines and interconnections in multilevel semiconductor structures |
JP2004200273A (ja) | 2002-12-17 | 2004-07-15 | Sony Corp | 半導体装置の製造方法 |
US7153766B2 (en) | 2003-01-09 | 2006-12-26 | Chartered Semiconductor Manufacturing Ltd. | Metal barrier cap fabrication by polymer lift-off |
US6967158B2 (en) | 2003-03-07 | 2005-11-22 | Freescale Semiconductor, Inc. | Method for forming a low-k dielectric structure on a substrate |
US6767827B1 (en) * | 2003-06-11 | 2004-07-27 | Advanced Micro Devices, Inc. | Method for forming dual inlaid structures for IC interconnections |
US6977218B2 (en) * | 2003-07-17 | 2005-12-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for fabricating copper interconnects |
US20050056810A1 (en) * | 2003-09-17 | 2005-03-17 | Jinru Bian | Polishing composition for semiconductor wafers |
US20050064701A1 (en) * | 2003-09-19 | 2005-03-24 | International Business Machines Corporation | Formation of low resistance via contacts in interconnect structures |
US7273803B2 (en) * | 2003-12-01 | 2007-09-25 | International Business Machines Corporation | Ball limiting metallurgy, interconnection structure including the same, and method of forming an interconnection structure |
TW200603698A (en) * | 2004-04-13 | 2006-01-16 | Unitive International Ltd | Methods of forming solder bumps on exposed metal pads and related structures |
KR100631876B1 (ko) * | 2004-10-29 | 2006-10-09 | 삼성전기주식회사 | 반도체 레이저 소자의 제조 방법 |
US7196014B2 (en) * | 2004-11-08 | 2007-03-27 | International Business Machines Corporation | System and method for plasma induced modification and improvement of critical dimension uniformity |
US7138717B2 (en) * | 2004-12-01 | 2006-11-21 | International Business Machines Corporation | HDP-based ILD capping layer |
US7253105B2 (en) * | 2005-02-22 | 2007-08-07 | International Business Machines Corporation | Reliable BEOL integration process with direct CMP of porous SiCOH dielectric |
US7279411B2 (en) * | 2005-11-15 | 2007-10-09 | International Business Machines Corporation | Process for forming a redundant structure |
US7435676B2 (en) * | 2006-01-10 | 2008-10-14 | International Business Machines Corporation | Dual damascene process flow enabling minimal ULK film modification and enhanced stack integrity |
US8367543B2 (en) * | 2006-03-21 | 2013-02-05 | International Business Machines Corporation | Structure and method to improve current-carrying capabilities of C4 joints |
-
2006
- 2006-01-18 US US11/306,983 patent/US7863183B2/en not_active Expired - Fee Related
-
2007
- 2007-01-05 TW TW096100592A patent/TW200741915A/zh unknown
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Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005210121A (ja) * | 2004-01-22 | 2005-08-04 | Internatl Business Mach Corp <Ibm> | ボンディング・パッドと高性能銅インダクタの集積化 |
JP2005277390A (ja) * | 2004-02-27 | 2005-10-06 | Handotai Rikougaku Kenkyu Center:Kk | 半導体装置及びその製造方法 |
Cited By (7)
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---|---|---|---|---|
JP2016525274A (ja) * | 2013-08-06 | 2016-08-22 | クアルコム,インコーポレイテッド | ダイ上の積層再分配層 |
JP2015092548A (ja) * | 2013-09-16 | 2015-05-14 | エスピーティーエス テクノロジーズ リミティド | 半導体構造のプレクリーニング |
JP2015173256A (ja) * | 2014-03-11 | 2015-10-01 | インテル コーポレイション | 集積回路パッケージ |
CN110574158A (zh) * | 2017-05-09 | 2019-12-13 | 国际商业机器公司 | 具有自对准焊料凸块的衬底通孔 |
JP2020520090A (ja) * | 2017-05-09 | 2020-07-02 | インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation | 自己整列はんだバンプを備えた基板貫通ビアを含む半導体デバイスを製造する方法および半導体構造 |
JP6996823B2 (ja) | 2017-05-09 | 2022-01-17 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 自己整列はんだバンプを備えた基板貫通ビアを含む半導体デバイスを製造する方法および半導体構造 |
CN110574158B (zh) * | 2017-05-09 | 2024-02-20 | 国际商业机器公司 | 具有自对准焊料凸块的衬底通孔 |
Also Published As
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WO2007084907A3 (en) | 2007-12-21 |
JP5186392B2 (ja) | 2013-04-17 |
WO2007084907A8 (en) | 2009-01-29 |
EP1989730A2 (en) | 2008-11-12 |
TW200741915A (en) | 2007-11-01 |
WO2007084907A2 (en) | 2007-07-26 |
CN101361174A (zh) | 2009-02-04 |
US20070166992A1 (en) | 2007-07-19 |
CN101361174B (zh) | 2011-03-16 |
US7863183B2 (en) | 2011-01-04 |
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