JP2005217419A - 高qファクタ(q値)の集積回路インダクタ - Google Patents
高qファクタ(q値)の集積回路インダクタ Download PDFInfo
- Publication number
- JP2005217419A JP2005217419A JP2005021309A JP2005021309A JP2005217419A JP 2005217419 A JP2005217419 A JP 2005217419A JP 2005021309 A JP2005021309 A JP 2005021309A JP 2005021309 A JP2005021309 A JP 2005021309A JP 2005217419 A JP2005217419 A JP 2005217419A
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- layer
- inductor
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- pad
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Abstract
【解決手段】インダクタを形成する方法は、(a)半導体基板を提供するステップと、(b)基板の上表面上に誘電層を形成するステップと、(c)誘電層中に下側トレンチを形成するステップと、(d)誘電層の上表面上にレジスト層を形成するステップと、(e)下側トレンチに対して位置合せされ、底部が下側トレンチに開いている上側トレンチをレジスト層中に形成するステップと、(f)インダクタを形成する目的で、導体で下側トレンチを完全に充填し、上側トレンチを少なくとも部分的に充填するステップとを含む。半導体構造は、上表面、底表面および側壁を含むインダクタと、前記インダクタを電気的に接触させる手段とを含み、前記インダクタの下側部分は、半導体基板上に形成された誘電層中に固定した距離だけ延び、上側部分は、前記誘電層の上に延在する。
【選択図】図1
Description
105 インダクタ
110A、110B 一体ビア
115 I/Oターミナル・パッド
120 ビア
125 導電性不動態化層
130 パッド限定メタラジ層、PLM層
135 はんだボール
140 導電性不動態化パッド、パッド
200 半導体基板
205A、205B アンダーパス・ワイヤ
210 上表面
215A、215B 上表面
220 上表面
225 第1の誘電層
230 第2の誘電層
235 上表面
240 第3の誘電層
245 上表面
250A、250B トレンチ
260 トレンチ
265 コンフォーマル・ライナ、ライナ
270 上表面
275 コンフォーマル・シード層、シード層
280 上表面
285 レジスト層
290 第1の導電性不動態化層
295 第2の導電性不動態化層
300 ブラケット有機不動態化層
305 コンタクト・パッド
310 コンタクト・パッド
D1、D2、D3、D4、D5 深さ
W1 コイルの幅
S1 コイルの間隔
Claims (61)
- インダクタを形成する方法であって、
(a)半導体基板を提供するステップと、
(b)前記基板の上表面上に誘電層を形成するステップと、
(c)前記誘電層中に下側トレンチを形成するステップと、
(d)前記誘電層の上表面上にレジスト層を形成するステップと、
(e)前記下側トレンチに位置合せされ、底部が前記下側トレンチに開いた上側トレンチを前記レジスト層中に形成するステップと、
(f)前記インダクタを形成するために、導体で前記下側トレンチを完全に充填し、前記上側トレンチを少なくとも部分的に充填するステップと
を備える方法。 - 前記基板中のI/Oターミナル・パッドまで達するビアを前記誘電層中に形成するステップをさらに含む、請求項1に記載の方法。
- 前記ビアを介して前記I/Oターミナル・パッドと電気的に接触するワイヤボンド・パッドを形成するステップをさらに含む、請求項2に記載の方法。
- 前記ビアを介して前記I/Oターミナル・パッドと接触するはんだボール接続部を形成するステップをさらに含む、請求項2に記載の方法。
- 前記はんだボール接続部を形成する前記ステップが、前記I/Oターミナル・パッドの上に1つまたは複数の金属を電気メッキするステップを含む、請求項4に記載の方法。
- 前記ステップ(c)が、前記基板中のI/Oターミナル・パッドに開いた底部を有するビアを前記誘電層中に形成するステップを含み、
前記ステップ(d)が、前記ビアに位置合せされ、底部が前記ビアに開いたトレンチを前記レジスト層中に形成するステップを含み、
前記ステップ(f)が、盛り上がったコンタクト・パッドを形成するために、前記導体で前記ビアを完全に充填し、前記トレンチを少なくとも部分的に充填するステップを含む、請求項1に記載の方法。 - 前記盛り上がったコンタクト・パッドと接触するはんだボール接続部を形成するステップをさらに含む、請求項6に記載の方法。
- 前記はんだボール接続部を形成する前記ステップが、前記基板に位置合せされたマスクを通して1つまたは複数の金属を蒸着するステップを含む、請求項7に記載の方法。
- 前記はんだボール接続部を形成する前記ステップが、前記I/Oターミナル・パッドの上に1つまたは複数の金属を電気メッキするステップを含む、請求項7に記載の方法。
- 前記下側トレンチが、前記誘電層中に所定の距離だけ形成される、請求項1に記載の方法。
- 前記ステップ(c)が、前記基板中のアンダーパス接続ワイヤに達するビアを形成するステップを含み、前記ビアが前記下側トレンチの底部表面中に形成され、
前記ステップ(f)が、前記導体で前記ビアを完全に充填するステップを含む、請求項10に記載の方法。 - 前記レジスト層を除去し、前記インダクタの上に導電性不動態化層を形成するステップ(g)をさらに含む、請求項1に記載の方法。
- 前記上側および下側トレンチが、スパイラル・トレンチである、請求項1に記載の方法。
- 前記導体が、CuまたはTaN/TaライナおよびCuコアを含む、請求項1に記載の方法。
- インダクタを形成する方法であって、
(a)半導体基板を提供するステップと、
(b)前記基板の上表面上に誘電層を形成するステップと、
(c)前記誘電層中に下側トレンチを形成するステップと、
(d)前記下側トレンチ中、および前記誘電層の上表面の上にコンフォーマルな導電性ライナを形成するステップと、
(e)前記導電性ライナの上にコンフォーマルなCuシード層を形成するステップと、
(f)前記基板上にレジスト層を形成するステップと、
(g)前記下側トレンチに対して位置合せされ、底部が前記下側トレンチに開いた上側トレンチを前記レジスト層中に形成するステップと、
(h)前記インダクタを形成するために、Cuを電気メッキして前記下側トレンチを完全に充填し、前記上側トレンチを少なくとも部分的に充填するステップと、
(i)前記レジスト層を除去するステップと、
(j)すべての露出したCu表面の上に導電性不動態化層を選択的に形成するステップと、
(k)前記誘電層の前記表面にある前記導電性ライナの領域から前記Cuシード層を選択的に除去し、前記誘電層の前記表面から前記導電性ライナを除去するステップと
を備える方法。 - 前記ステップ(e)の後に、前記誘電層の前記上表面にある前記導電性ライナの領域から前記Cuシード層を除去し、前記下側トレンチの側壁および底部表面上の前記導電性ライナ上に前記シード層を残しておくステップをさらに含み、
前記ステップ(k)が、前記誘電層の前記上表面にある前記導電性層の前記領域から前記シード層を除去するステップを含まない、請求項15に記載の方法。 - 前記基板中のI/Oターミナル・パッドに達するビアを前記誘電層中に形成するステップをさらに含む、請求項15に記載の方法。
- 前記I/Oターミナル・パッドに対して位置合せされたビアを前記誘電層中に形成するステップと、
前記誘電層中の前記ビアに対して位置合せされたポリイミド層を前記基板の上に形成するステップと、
前記I/Oターミナル・パッドに対して位置合せされた前記ポリイミド層中にあり、ワイヤボンド・パッドを画定するビアを前記ポリイミド層中に形成するステップと
をさらに含む、請求項17に記載の方法。 - 前記ポリイミド層および前記誘電層中の前記ビアを介して前記I/Oターミナル・パッドと接触するはんだボール接続部を形成するステップをさらに含む、請求項17に記載の方法。
- 前記はんだボール接続部を形成する前記ステップが、パッド限定メタラジ層およびシード層を蒸着またはスパッタリングするステップと、Pb層またはPb/Sn合金層を電気メッキするステップとを含む、請求項19に記載の方法。
- 前記ステップ(c)が、前記基板中のI/Oターミナル・パッドに達するビアを前記誘電層中に形成するステップを含み、
前記ステップ(d)が、前記誘電層中の前記ビア中にコンフォーマル導電性ライナを形成するステップを含み、
前記ステップ(g)が、前記誘電層中の前記ビアに対して位置合せされ、底部が前記誘電層中の前記ビアに開いたトレンチを前記レジスト層中に形成するステップを含み、
前記ステップ(h)が、盛り上がったコンタクト・パッドを形成するために、Cuを電気メッキして前記誘電層中の前記ビアを完全に充填し、前記トレンチを少なくとも部分的に充填するステップを含む、請求項15に記載の方法。 - 前記盛り上がったコンタクト・パッドと接触するはんだボール接続部を形成するステップをさらに含む、請求項21に記載の方法。
- 前記はんだボール接続部を形成する前記ステップが、前記基板に対して位置合せされたマスクを通して、パッド限定メタラジ層およびPb層またはPb/Sn合金層を蒸着またはスパッタリングするステップを含む、請求項22に記載の方法。
- 前記はんだボール接続部を形成する前記ステップが、パッド限定メタラジ層およびシード層をスパッタリングするステップと、Pb層またはPb/Sn合金層を電気メッキするステップとを含む、請求項22に記載の方法。
- 前記下側トレンチが、前記誘電層中に所定の距離だけ形成される、請求項15に記載の方法。
- 前記ステップ(c)が、前記基板中のアンダーパス接続ワイヤに達するビアを形成するステップを含み、前記ビアが前記下側トレンチの底部表面中に形成され、
前記ステップ(h)が、Cuを電気メッキして前記下側トレンチの前記底部表面中の前記ビアを完全に充填するステップを含む、請求項25に記載の方法。 - 前記導電性不動態化層が、Ni層の上にNi層またはAu層を含む、請求項15に記載の方法。
- 前記上側および下側トレンチがスパイラル・トレンチであり、前記インダクタがスパイラル・インダクタである、請求項15に記載の方法。
- 前記誘電層が、SiO2層の上表面と接触するSi3N4の上側層を含み、前記SiO2層がSi3N4の下側層の上表面と接触する、請求項15に記載の方法。
- 前記ステップ(h)が、少なくとも5μmの深さまでCuを電気メッキする、請求項15に記載の方法。
- 上表面、底部表面および側壁を有するインダクタと、前記インダクタを電気的に接触させる手段とを含み、
前記インダクタの下側部分が、半導体基板上に形成された誘電層中に固定した距離だけ延び、上側部分が前記誘電層の上に延在する、半導体構造。 - 前記インダクタの前記下側部分が、導電性ライナと、コア導体とを含み、前記インダクタの前記上側部分が、前記コア導体を含む、請求項31に記載の構造。
- 前記コア導体がCuであり、前記ライナがTaNおよびTaの2重の層を含む、請求項32に記載の構造。
- 前記上側部分が、前記インダクタの前記上側部分の上表面および側壁上に導電性不動態化層をさらに含む、請求項32に記載の構造。
- 前記不動態化層が、Ni層の上にNi層またはAu層を含む、請求項34に記載の構造。
- 前記インダクタが、前記側壁によって画定される、5μmより高い高さを有する、請求項31に記載の構造。
- 前記下側部分が、前記誘電層中に3μmより短い距離だけ延びている、請求項31に記載の構造。
- 前記インダクタを接触させる前記手段が、前記インダクタの前記底部から前記誘電層を貫通して延び、前記基板中のメタラージを貫通するパスと電気的に接触する一体ビアを含む、請求項31に記載の構造。
- 前記ビアの上の前記インダクタの前記上表面が、前記ビアの上でない前記インダクタの前記上表面の部分より、前記誘電層の上表面の近くにある、請求項38に記載の構造。
- 前記インダクタが、スパイラル・コイル中の前記誘電層の上表面と平行に延在する、請求項31に記載の構造。
- 前記インダクタが、幅2〜30μmであり、前記スパイラル・コイルの互いに隣接するコイルが、2〜20μmの間隔で配置されている、請求項40に記載の構造。
- 前記インダクタが、0.5nHより大きいインダクタンスを有する、請求項31に記載の構造。
- 前記インダクタが、25より大きいQ値を有する、請求項31に記載の構造。
- 前記インダクタが、40より大きいQ値を有する、請求項31に記載の構造。
- 前記誘電層中に形成されたビアを有するコンタクト・パッドをさらに含み、前記ビアが前記基板中のI/Oターミナル・パッドの少なくとも一部分を露出させ、前記ビアの側壁および前記I/Oターミナル・パッドの少なくとも一部分が、導電性ライナの上のコンフォーマル・シード層の上の不動態化層によって覆われている、請求項31に記載の構造。
- 前記導電性ライナがTaNおよびTaの2重の層を含み、前記シード層がCuを含み、前記不動態化層がNi層の上にNi層またはAu層を含む、請求項45に記載の構造。
- 前記コンタクト・パッドに導通状態になるようにボンディングされたAlワイヤまたはAuワイヤをさらに含む、請求項46に記載の構造。
- 前記不動態化層上のパッド限定メタラジ層と、前記パッド限定メタラジ層上のはんだボールとをさらに含む、請求項46に記載の構造。
- 前記パッド限定メタラジ層が、Cr層、CrCu層、Au層、Cu層およびTiW層からなる群から選択される1つまたは複数の層を含み、前記はんだボールが、PbまたはPb/Sn合金を含む、請求項48に記載の構造。
- 前記インダクタの前記上表面が、前記コンタクト・パッドの上表面とは異なる平面上にある、請求項45に記載の構造。
- 前記インダクタの上表面が、前記誘電層の上表面を基準にして前記コンタクト・パッドの前記上表面より高い、請求項45に記載の構造。
- 前記基板中に形成されたI/Oターミナル・パッドと、
前記I/Oターミナル・パッドと電気的に接触する盛り上がったコンタクト・パッドとをさらに含み、
前記盛り上がったコンタクト・パッドが、上表面と、底部表面と、側壁とを有し、
前記インダクタの下側部分が、半導体基板上に形成された前記誘電層中に前記固定した距離だけ延び、
上側部分が、前記誘電層の上に延在する、請求項31に記載の構造。 - 前記盛り上がったコンタクト・パッドの前記下側部分が、導電性ライナと、コア導体とを有し、
前記盛り上がったコンタクト・パッドの前記上側部分が、前記コア導体を有する、請求項52に記載の構造。 - 前記コア導体がCuであり、前記ライナがTaNおよびTaの2重の層を含む、請求項53に記載の構造。
- 前記上側部分が、前記盛り上がったコンタクト・パッドの前記上側部分の前記上表面および側壁上に導電性不動態化層をさらに含む、請求項53に記載の構造。
- 前記不動態化層が、Ni層の上にNi層またはAu層を含む、請求項55に記載の構造。
- 前記盛り上がったコンタクト・パッドに導電的にボンディングされたAlワイヤまたはAuワイヤをさらに含む、請求項56に記載の構造。
- 前記不動態化層上のパッド限定メタラジ層と、前記パッド限定メタラジ層上のはんだボールとをさらに含む、請求項56に記載の構造。
- 前記パッド限定メタラジ層が、Cr層、CrCu層、Au層、Cu層およびTiW層からなる群から選択される1つまたは複数の層を含み、前記はんだボールがPbまたはPb/Sn合金を含む、請求項58に記載の構造。
- 前記インダクタの前記上表面が、前記盛り上がったコンタクト・パッドの上表面とは異なる平面上にある、請求項52に記載の構造。
- 前記インダクタの上表面が、前記誘電層の上表面を基準にして前記盛り上がったコンタクト・パッドの前記上表面より高い、請求項52に記載の構造。
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US11501908B2 (en) | 2016-10-04 | 2022-11-15 | Nanohenry, Inc. | Miniature inductors and related circuit components and methods of making same |
KR102511578B1 (ko) * | 2016-10-04 | 2023-03-16 | 나노헨리, 인코포레이티드 | 소형 인덕터와 관련 회로 컴포넌트 및 그 제조 방법 |
US11990266B2 (en) | 2016-10-04 | 2024-05-21 | Nanohenry, Inc. | Miniature transmission lines and related circuit components |
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US20060105534A1 (en) | 2006-05-18 |
TW200537671A (en) | 2005-11-16 |
US7068138B2 (en) | 2006-06-27 |
TWI351747B (en) | 2011-11-01 |
JP3996602B2 (ja) | 2007-10-24 |
CN100341112C (zh) | 2007-10-03 |
US7829427B2 (en) | 2010-11-09 |
US20100047990A1 (en) | 2010-02-25 |
CN1649087A (zh) | 2005-08-03 |
TWI351748B (en) | 2011-11-01 |
US20050167780A1 (en) | 2005-08-04 |
US7638406B2 (en) | 2009-12-29 |
TW201036127A (en) | 2010-10-01 |
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