CN1649087A - 形成电感器的方法以及半导体结构 - Google Patents

形成电感器的方法以及半导体结构 Download PDF

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CN1649087A
CN1649087A CNA2005100018650A CN200510001865A CN1649087A CN 1649087 A CN1649087 A CN 1649087A CN A2005100018650 A CNA2005100018650 A CN A2005100018650A CN 200510001865 A CN200510001865 A CN 200510001865A CN 1649087 A CN1649087 A CN 1649087A
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Prior art keywords
layer
inductor
dielectric layer
via hole
groove
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CN100341112C (zh
Inventor
D·C·埃德尔斯坦
P·C·安德里卡科斯
J·M·科特
H·德利吉安尼
J·H·梅格莱因
K·S·彼得拉尔卡
K·J·施泰因
R·P·沃朗
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Core Usa Second LLC
GlobalFoundries Inc
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International Business Machines Corp
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Abstract

本发明提供了一种电感器及形成电感器的方法，该方法包括：(a)提供半导体衬底；(b)在衬底的上表面上形成介质层；(c)在介质层中形成下沟槽；(d)在介质层的上表面形成抗蚀剂层；(e)在抗蚀剂层中形成上沟槽，上沟槽与下沟槽对准，上沟槽的底部开口到下沟槽；以及(f)用导体完全填充下沟槽并至少部分地填充上沟槽，以形成电感器。该电感器包括上表面、下表面和侧壁，所述电感器的下部延伸固定距离进入半导体衬底上形成的介质层中，且上部在所述介质层上延伸；以及电接触所述电感器的装置。

Description

形成电感器的方法以及半导体结构
技术领域
本发明涉及集成电路领域；更具体地说，它涉及高品质(Q)因子电感器结构，制造高Q因子电感器结构的方法以及将高Q因子电感器结构集成到集成电路制造工艺中的方法。
背景技术
在用于射频RF应用的许多集成电路中使用电感器。电感器一般由集成电路芯片的表面上或接近表面的较厚金属制成。随着集成电路工作的RF频率增加，功耗增加，除非电感器的Q因子也增加。电感器的Q因子定义为Q＝Es/El，其中Es是电感器的电抗部分中存储的能量，以及El是电感器的电抗部分中损失的能量。电感器的Q值还可以表示为Q＝W0L/R，其中W0是谐振频率，L是电感值以及R是电感器的电阻。第二等式的重要性是Q随R减小而增加。
使用高导电性金属、宽金属线或厚金属线制造电感器可以减小电感器中的电阻。但是，使用宽金属线电感器可能消耗大量的集成电路芯片表面，以及用于布置电感器的集成电路的合适面积通常非常有限。特别当使用高导电性金属并随后将高导电性、厚金属电感器集成到集成电路的中间连接层时，厚金属电感器的制造是有问题的。因此，需要由高导电金属形成的高Q因子、厚金属电感器，以及与用于形成集成电路芯片的电感器的中间连接层制造技术相兼容的方法和集成方案。
发明内容
本发明的第一方面是形成电感器的方法，依次包括：(a)提供半导体衬底；(b)在衬底的上表面上形成介质层；(c)在介质层中形成下沟槽；(d)在介质层的上表面形成抗蚀剂层；(e)在抗蚀剂层中形成上沟槽，上沟槽与下沟槽对准，上沟槽的底部开口到下沟槽；以及(f)用导体完全填充下沟槽并至少部分地填充上沟槽，以形成电感器。
本发明的第二方面是形成电感器的方法，依次包括：(a)提供半导体衬底；(b)在衬底的上表面上形成介质层；(c)在介质层中形成下沟槽；(d)在沟槽中和介质层的上表面上形成保形导电衬里；(e)在导电衬里上形成保形Cu籽晶层；(f)在衬底上形成抗蚀剂层；(g)在抗蚀剂层中形成上沟槽，上沟槽与下沟槽对准，上沟槽的底部开口到下沟槽；(h)电镀铜以完全填充下沟槽并至少部分地填充上沟槽，以形成电感器；(i)除去抗蚀剂层；(j)在所有暴露Cu表面上有选择地形成导电钝化层；以及(k)从覆盖介质层表面的导电衬里的区域有选择地除去Cu籽晶层，并从介质层的表面除去导电衬里。
本发明的第三方面是一种半导体结构，包括：具有上表面、下表面和侧壁的电感器，电感器的下部延伸固定距离进入半导体衬底上形成的介质层，且上部在介质层上延伸；以及电接触电感器的装置。
附图说明
在所附的权利要求书中阐述了本发明的特征。但是通过参考说明性实施例的详细描述同时结合附图阅读时将更透彻地理解发明本身，其中：
图1是根据本发明的第一实施例的电感器和接触焊盘的俯视图；
图2是根据本发明的第二实施例的电感器和接触焊盘的俯视图；
图3是根据本发明的第三实施例的电感器和接触焊盘的俯视图；
图4A至4F示出了本发明的第一、第二和第三实施例所共有的制造步骤的部分剖面图；
图5A至5F示出了本发明的第一和第二实施例所共有的图4A至4F所示步骤之后的制造步骤的部分剖面图；
图5G示出了用于本发明的第二实施例，在图5A至5F所示步骤之后的制造步骤的部分剖面图；以及
图6A至6G示出了用于本发明的第三实施例，在图4A至4F所示步骤之后的制造步骤的部分剖面图。
具体实施方式
图1是根据本发明的第一实施例的电感器和接触焊盘的俯视图。在图1中，集成电路芯片100A包括具有整体过孔(integral via)110A和110B的电感器105，整体过孔110A和110B用于互连到集成电路芯片内的布线级(未示出)。尽管电感器105图示为螺旋形电感器，但是本发明也可应用其它形状的电感器。集成电路芯片100A还包括用于互连到集成电路芯片内的布线级(未示出)的过孔120底部中的I/O接线端焊盘115，以及在I/O接线端焊盘115的顶部形成并覆盖过孔120的导电钝化层125。
图2是根据本发明的第二实施例的电感器和接触焊盘的俯视图。在图2中，集成电路芯片100B包括具有整体过孔110A和110B的电感器105，整体过孔110A和110B用于互连到集成电路芯片内的布线级(未示出)。尽管电感器105图示为螺旋形电感器，但是本发明也可应用其它形状的电感器。集成电路芯片100B还包括I/O接线端焊盘115、导电钝化层125、焊盘限制冶金(PLM)层130以及焊料球135，其中I/O接线端焊盘115在用于互连到集成电路芯片内的布线级(未示出)的过孔120的底部中，导电钝化层125在I/O接线端焊盘115的顶部形成并覆盖过孔120，焊料球135在导电钝化层125上形成。焊料球也是公知的坍塌得到控制芯片连接(C4)球、C4焊料球和焊料凸起。对于本发明，术语焊料球可以用术语焊料柱代替。焊料柱是Pb或Pb/Sn合金的柱体，且本发明也可应用焊料柱互连技术。
图3是根据本发明的第三实施例的电感器和接触焊盘的俯视图。在图3中，集成电路芯片100C包括具有整体过孔110A和110B的电感器105，整体过孔110A和110B用于互连到集成电路芯片内的布线级(未示出)。尽管电感器105图示为螺旋形电感器，但是本发明也可应用其它形状的电感器。集成电路芯片100C还包括I/O接线端焊盘115、导电钝化涂层凸起焊盘140、PLM层130以及焊料球135，其中I/O接线端焊盘115在用于互连到集成电路芯片内的布线级(未示出)的过孔120的底部中，导电钝化涂层凸起焊盘140在过孔120的顶部形成并覆盖过孔120，焊料球135在导电钝化层125上形成。PLM层130完全处于凸起焊盘140上。
图4A至4F示出了本发明的第一、第二和第三实施例所共有的制造步骤的部分剖面图。图4A至4F沿图1的线S1-S1、图2的线S2-S2或图3的线S3-S3。
在图4A中，半导体衬底200包括I/O接线端焊盘115和下通(underpass)布线205A和205B。I/O接线端焊盘115的上表面210和下通布线205A和205B的上表面215A和215B分别与衬底200的上表面220共面。下通布线205A和205B以及I/O接线端焊盘115与其它布线级(未示出)中的布线电连接并最终电连接衬底200内的有源器件。下通布线205A和205B提供到电感器105的电连接(参见图1、2或3)。在一个例子中，I/O接线端焊盘115和下通布线205A和205B包括TaN/Ta衬里(首先形成TaN层)和Cu芯，并通过镶嵌或双镶嵌工艺形成；图4A中所示的部分衬底200包括SiO2。TaN/Ta衬里可以被除去或用由其它材料如W、Ti和TiN构成的衬里替换。
在镶嵌工艺中，在介质层中蚀刻沟槽，在沟槽的底部和侧壁以及介质层的上表面上淀积最佳的导电保形衬里和导电籽晶层。然后在籽晶层上淀积或电镀芯导体，填充沟槽。最后，执行化学机械抛光步骤，从介质层的上表面除去所有衬里、籽晶层和芯导体并留下导体填充的沟槽，沟槽的上表面与介质层的上表面共面。在双镶嵌工艺中，在形成衬里或芯导体之前在沟槽的底部形成开口到下布线级的过孔。
在图4B中，在衬底200的上表面220以及分别在下通布线205A和205B和I/O接线端焊盘115的上表面215A和215B和210上形成第一介质层225。在第一介质层225的上表面235上形成第二介质层230。在第二介质层230的上表面245上形成第三介质层240。在一个例子中，第一介质层225是约350至1050厚的Si3N4，第二介质层230是约1500至5000厚的SiO2，第三介质层240是约2000至6000厚的Si3N4。
实际上本发明可以只使用例如SiO2或Si3N4的单介质层或例如Si3N4上SiO2的双层代替三个介质层225，230和240。
在图4C中，除去在下通布线205A和205B以及I/O接线端焊盘115上对准的部分第三介质层240，露出第二介质层230的上表面245。在图4D中，除去在下通布线205A和205B以及I/O接线端焊盘115上对准的部分第二介质层230和第一介质层225，分别形成沟槽250A和250B以及过孔120，并分别露出下通布线205A和205B以及I/O接线端焊盘115的上表面215A，215B和210。此外，向下除去部分第三介质层240和部分第二介质层230到深度D1，以形成沟槽260。
应当理解沟槽250A，250B和260事实上是一个互连的螺旋形沟槽，其中将形成电感器105(参见图1、2和3)，且沟槽250A和250B表明在其中形成过孔110A和110B(参见图1、2和3)的部分螺旋形沟槽。在剖面图中，为了避免与此时正在描述的部分螺旋形沟槽混淆，沟槽250A，250B和260仅仅表现为分开的沟槽，将使用“分开”沟槽术语。
在沟槽260中的第二介质层230的精确去除深度D1不是关键性的，只要在沟槽260中留下足够的第二介质层230，以在沟槽250A和250B以及过孔120中除去介质层225时保护介质层225。在一个例子中，D1为约2500至7500。D2是沟槽260的深度，以及D3是沟槽250A和250B以及过孔120的深度。沟槽260与沟槽250A和250B以及过孔120之间的深度差是D3-D2。
图4C和4D所示的步骤可以通过几种方法来完成。在第一种方法中，施加第一光致抗蚀剂层，执行第一光刻工艺，执行选择性蚀刻上述例子中SiO2上的Si3N4的第一反应离子蚀刻(RIE)工艺，以在第三介质层240中限定沟槽250A和250B，如图4C所示。然后，除去第一抗蚀剂层，施加第二抗蚀剂层，执行第二光刻工艺，随后执行选择性蚀刻上述例子中SiO2上的Si3N4的第二RIE工艺，以在第二介质层和第三介质层240中完全开口沟槽250A和250B和过孔120，以及蚀刻沟槽260中的第二介质层230到D1深度，如图4D所示。然后除去第二抗蚀剂层。
在第二方法中，施加一层双色调抗蚀剂层(层叠或复合的正/负抗蚀剂)，并执行使用双色调光掩膜的光刻步骤，以完全除去在将要形成沟槽250A和250B以及过孔120处的抗蚀剂层，并只部分地除去在将要形成沟槽260处的抗蚀剂层(向下减薄抗蚀剂层)。然后执行单个RIE蚀刻，以形成图4D所示的结构(图4C被跳越)。然后除去双色调抗蚀剂层。在任何一种情况中，可以执行清除蚀刻，例如使用稀释的HF的湿蚀刻。
在图4E中，在第三介质层240的上表面270上以及在沟槽250A、250B和260以及过孔120的侧壁和底部上淀积保形衬里265。然后在衬里265的上表面280上淀积保形籽晶层275。在一个例子中，衬里265是在约10至1000的TaN上淀积的约200至5000的Ta，以及籽晶层275为约100至1500的Cu，都通过物理汽相淀积(PVD)或电离的物理汽相淀积(IPVD)形成。
在图4F中，执行CMP工艺，以从接触第三介质层265的上表面270的衬里265除去籽晶层275，但是在沟槽250A、250B和260以及过孔120的侧壁和底部上保留籽晶层。在CMP之后可以进行选择性清除蚀刻。在籽晶层275是Cu的例子中，稀释的草酸/HF蚀刻剂可以用于清除蚀刻。也可以执行选择性的Cu清除蚀刻。
在第二方法中，不执行前述的CMP工艺，以及籽晶层275保留在衬里265顶部的各处。在如下所述的后续步骤中将除去籽晶层275。
这些构成了本发明的所有实施例所共有的部分电感器制造。应当注意尽管使用第一介质层225、第二介质层230和第三介质层240描述了本发明，但是实际上本发明可以使用更多或更少的介质层。例如，可以使用单介质层或双介质层代替上文描述的三介质层。
图5A至5F示出了本发明的第一和第二实施例所共有的图4A至4F所示步骤之后的制造步骤的部分剖面图。图5A至5F在第一实施例的情况中沿图1的线S1-S1，或在第二实施例的情况中沿图2的线S2-S2的截面。
在图5A中，形成并构图抗蚀剂层285，暴露沟槽250A、250B和260的底部和侧壁上的籽晶层275，但是保护过孔120。抗蚀剂层285具有厚度D4。构图的抗蚀剂层285用于增加沟槽250A、250B和260的深度。在一个例子中，D4为约8至20微米厚。在一个例子中，抗蚀剂层285可以是任意常规的旋涂抗蚀剂。在第二例子中，D4为约20至50微米。在约20微米以上，可以使用由Dupont(Wilmington De.)制造的Riston或其它轧涂的抗蚀剂。D4的值是控制如图5B所示和下文描述的将要形成的电感器105的厚度(参见图2)的一个因素。
在图5B中，通过使用籽晶层275作为阴极的电镀，用厚度为D5的金属部分地填充沟槽250A、250B和260，以形成电感器105。厚度D5是控制电感器105的厚度的另一个因素。注意籽晶层275的各个岛被衬里265电连接，衬里265有效地是覆盖层，即在整个衬底200上延伸的保形、导电的涂层。通常，当金属到达抗蚀剂层285的填充沟槽260的约1至2微米内时，停止电镀工艺，以使抗蚀剂层的后续去除更容易。可以溢出沟槽然后CMP过量金属。在一个例子中，电感器105由电镀的Cu形成。在Volant等人的美国专利6,368,484中描述了示例性的Cu电镀工艺，因此将其全部内容引入作为参考。在一个例子中，D5为约5至50微米。
在图5C中，除去抗蚀剂层285(参见图5B)。电感器105的线圈的宽度W1和间隔S1不受本发明限制。W1和S1受如下的限制：在下端处用特定的光刻工艺(抗蚀剂系统、掩膜技术和曝光工具和波长)可印刷的最小线/间隔，以及在上端处电感器可获得的集成区域(real estate)的量。在一个例子中，W1为约2至30微米，以及S1为约2至20微米。
在第二方法中，现在从例如通过湿蚀刻暴露的区域除去籽晶层275。在一个例子中，湿蚀刻是硫酸、过硫酸铵和水的混合物。Cu的蚀刻率必须足够慢，以在没有实质性蚀刻或底切电感器105或其它电镀的Cu结构的条件下完成籽晶层275的可控制去除。
在图5D中，在籽晶层275的所有暴露表面上但是不在暴露的衬里265上有选择地电镀第一导电钝化层290。在第一导电钝化层290的所有暴露表面上但是不在暴露的衬里265上有选择地电镀第二导电钝化层295。在一个例子中，第一导电钝化层290是约2000至6000厚的Ni，第二导电钝化层295是约1200至4000厚的Au。也可以使用单层导电钝化层。第一导电钝化层290和第二导电钝化层295相当于图1、2和3所示且在上文中描述的导电钝化层125。
在图5E中，除去所有暴露的衬里265。在衬里265是TaN/Ta和第二导电钝化层295是Au的例子中，可以使用基于氟的RIE。
在图5F中，施加并光刻构图覆盖有机钝化层300，以露出I/O接线端焊盘115上的接触焊盘305。在一个例子中，覆盖有机钝化层300是聚酰亚胺。聚酰亚胺层一般通过涂覆聚酰亚胺前体然后通过加热将前体转变为固化的聚酰亚胺来提供。可获得以商业名称Pyralin提供的市场上可获得的聚酰亚胺前体(聚酰胺酸)或由DuPont(Wilmington，De.)制造的各种聚酰亚胺前体。这些聚酰亚胺前体包括许多等级，包括商业名称PI-2555，PI2545，PI-2560，PI-5878，PIH61454和PI-2540。这些聚酰亚胺前体的一些是均苯四甲酸二酐一氧化二苯胺(oxydianline)(PMA-ODA)聚酰亚胺前体。固化的聚酰亚胺层为约0.4至5微米厚。接触焊盘305可以用作引线接合焊盘。在引线接合中，Al或Au引线被超声波焊接或接合到接触焊盘。这些构成了本发明的第一实施例的制造。
图5G示出了用于本发明的第二实施例，在图5A至5F所示步骤之后的制造步骤的部分剖面图。图5G是沿图2的线S2-S2的截面。在图5G中，形成PLM层130，以电接触凸起接触焊盘305，以及在PLM层130上形成焊料球135。可以通过整个掩膜电镀C4工艺形成PLM 130和焊料球135。整个掩膜电镀C4工艺是公知的技术，但是简要地涉及蒸发或溅射PLM和籽晶层，在晶片上形成构图的光掩膜，电镀Pb或Pb/Sn合金，剥离光掩膜并蚀刻除去露出的PLM和籽晶层。在Uzoh等人的美国专利6,297,140和美国专利6,251,428中描述了示例性的C4电镀工艺，因此将两者全部引入作为参考。在整个电镀C4工艺的一个例子中，PLM层130包括TiW/CrCu/Cu的三层和由Pb或Pb/Sn合金构成的焊料球135。在后蒸发或后电镀回流退火之后示出了焊料球135。在一个例子中，TiW层为约250至2000厚，CrCu层为约100至2000厚，以及Cu层为约1000至20,000厚。这些构成了本发明的第二实施例的制造。
因为电感器105(参见图5G)显著地高于接触焊盘305，所以蒸发C4工艺不能用于形成图5G的PLM 130和焊料球135，因为蒸发C4工艺中使用的钼掩膜距接触焊盘很远，以使下面的掩膜蒸发量无法忍受。本发明的第三实施例提供了允许使用蒸发C4工艺的焊盘结构。
图6A至6G示出了用于本发明的第三实施例，在图4A至4F所示步骤之后的制造步骤的部分剖面图。图6A至6G是沿图3的线S3-S3的截面。
在图6A中，形成并构图抗蚀剂层285，露出沟槽250A、250B和260以及过孔120的底部和侧壁上的籽晶层275。抗蚀剂层285的成分和厚度在上文已作了描述。
在图6B中，通过使用籽晶层275作为阴极的电镀，用金属部分地填充沟槽250A、250B和260以及过孔120，以形成电感器105和凸起焊盘140。注意籽晶层275的各个岛通过衬里265电连接，衬里265有效地是覆盖层，即在整个衬底200上延伸的保形、导电的涂层。通常，当金属到达抗蚀剂层285的上表面约1至2微米内时，停止电镀工艺，以使抗蚀剂层的后续去除更容易。可以溢出沟槽然后CMP过量金属。电感器105的成分和厚度在上文已作了描述。
在图6C中，除去抗蚀剂层285(参见图6B)。电感器105的线圈的宽度W1和间隔S1在上文已作了描述。
在第二方法中，现在从如上所述暴露区域除去籽晶层275。
在图6D中，在电感器105和凸起焊盘140的所有暴露表面上但是不在暴露的衬里265上有选择地电镀第一导电钝化层290。在第一导电钝化层290的所有暴露表面上但是不在暴露的衬里265上有选择地电镀第二导电钝化层295。第一钝化290和第二钝化层295的成分和厚度在上文已作了描述。
在图6E中，除去所有暴露的衬里265。在衬里265是TaN/Ta和第二导电钝化层295是Au的例子中，可以使用基于氟的RIE。
在图6F中，施加并光刻构图覆盖有机钝化层300，以露出I/O接线端焊盘115上的接触焊盘310。上文已经描述了覆盖有机钝化层300的成分。此时，在本发明的第三实施例的制造中，制造可以被改变，在本发明的第四实施例中，如上所述施加聚酰亚胺或其它钝化涂层，以及凸起接触焊盘310用作引线接合焊盘或用于悬臂柱连接如带自动接合(TAB)封装的接合焊盘。
继续本发明的第三实施例，在图6G中，在凸起接触焊盘310上形成PLM层130，在PLM层130上形成焊料球135。通过整个掩膜电镀C4或蒸发C4工艺形成PLM 130和焊料球135。因为凸起接触焊盘310的高度，现在可以使用蒸发的C4工艺，由于钼蒸发掩膜与凸起接触焊盘310足够靠近，避免了掩膜远离焊盘时的如上所述的问题。蒸发C4工艺是公知的技术，但是涉及将钼掩膜放置接近半导体晶片，首先通过掩膜中的孔蒸发或溅射PLM，然后通过掩膜中相同的孔蒸发Pb或Pb/Sn合金，然后除去掩膜。在蒸发C4工艺的一个例子中，PLM层130包括Cr/CrCu/Au的三层和由Pb或Pb/Sn合金构成的焊料球135。在一个例子中，Cr层为约100至1000厚，Cu层为约100至2000厚，以及Au层为约100至1,000厚。整个掩膜电镀C4工艺和材料在上文已作了描述。这些构成了本发明的第三实施例的制造。
已示出本发明的所有实施例来制造具有约等于或大于40的Q因子和具有约等于或大于0.5nH的电感的电感器。
因此，本发明提供不仅提供由高导电性金属形成的高Q因子、厚金属电感器，而且提供用于形成与集成电路芯片的中间连接层制造技术相兼容的方法和集成方案。
为了理解本发明上面给出了本发明的实施例的描述。但是应当理解本发明不局限于在此描述的具体实施例，而是对于所属领域的技术人员来说在不脱离本发明的范围的条件下能进行各种修改、调整和替换。例如，尽管本发明描述了形成由TaN/Ta的衬里、Cu籽晶层以及Cu芯形成的电感器，但是可以替换为其它导电材料。
因此下列权利要求书旨在覆盖属于本发明的真实精神和范围内的所有这种修改和变化。

Claims (61)

1.一种形成电感器的方法，依次包括：
(a)提供半导体衬底；
(b)在所述衬底的上表面上形成介质层；
(c)在所述的介质层中形成下沟槽；
(d)在所述介质层的上表面上形成抗蚀剂层；
(e)在所述抗蚀剂层中形成上沟槽，所述上沟槽与所述下沟槽对准，所述上沟槽的底部开口到所述下沟槽；以及
(f)用导体完全填充所述下沟槽并至少部分地填充所述上沟槽，以形成所述电感器。
2.根据权利要求1的方法，还包括：
在所述介质层中形成到所述衬底中的I/O接线端焊盘的过孔。
3.根据权利要求2的方法，还包括形成通过所述过孔电接触所述I/O接线端焊盘的引线接合焊盘。
4.根据权利要求2的方法，还包括形成通过所述过孔接触所述I/O接线端焊盘的焊料球连接。
5.根据权利要求4的方法，其中所述形成所述焊料球连接的步骤包括在所述I/O接线端焊盘上电镀一种或多种金属。
6.根据权利要求1的方法，其中：
步骤(c)包括在所述介质层中形成过孔，所述过孔的底部开口到所述衬底中的I/O接线端焊盘；
步骤(d)包括在所述抗蚀剂层中形成沟槽，所述沟槽与所述过孔对准，所述抗蚀剂层中的所述沟槽的底部开口到所述过孔；以及
步骤(f)包括用所述导体完全填充所述过孔并至少部分地填充所述沟槽，以形成凸起接触焊盘。
7.根据权利要求6的方法，还包括形成接触所述凸起接触焊盘的焊料球连接。
8.根据权利要求7的方法，其中所述形成所述焊料球连接的步骤包括通过与所述衬底对准的掩膜蒸发一种或多种金属。
9.根据权利要求7的方法，其中所述形成所述焊料球连接的步骤包括在所述I/O接线端焊盘上电镀一种或多种金属。
10.根据权利要求1的方法，其中形成所述下沟槽进入所述介质层预定距离。
11.根据权利要求10的方法，其中：
步骤(c)包括形成到所述衬底中的下通连接布线的过孔，所述过孔在所述下沟槽的下表面中形成；以及
步骤(f)包括用所述导体完全填充所述过孔。
12.根据权利要求1的方法，还包括：
(g)除去所述抗蚀剂层并在所述电感器上形成导电钝化层。
13.根据权利要求1的方法，其中所述上和下沟槽是螺旋形沟槽。
14.根据权利要求1的方法，其中所述导体包括Cu或TaN/Ta衬里以及Cu芯。
15.一种形成电感器的方法，依次包括：
(a)提供半导体衬底；
(b)在所述衬底的上表面上形成介质层；
(c)在所述介质层中形成下沟槽；
(d)在所述下沟槽中和所述介质层的上表面上形成保形导电衬里；
(e)在所述导电衬里上形成保形Cu籽晶层；
(f)在所述衬底上形成抗蚀剂层；
(g)在所述抗蚀剂层中形成上沟槽，所述上沟槽与所述下沟槽对准，所述上沟槽的底部开口到所述下沟槽；
(h)电镀Cu以完全填充所述下沟槽并至少部分地填充所述上沟槽，以形成所述电感器；
(i)除去所述抗蚀剂层；
(j)在所有暴露Cu表面上有选择地形成导电钝化层；以及
(k)从覆盖所述介质层的所述表面的所述导电衬里的区域有选择地除去所述Cu籽晶层，并从所述介质层的所述表面除去所述导电衬里。
16.根据权利要求15的方法，
还包括在步骤(e)之后从覆盖所述介质层的所述上表面的所述导电衬里的区域除去所述Cu籽晶层，并在所述下沟槽的侧壁和下表面上的所述导电衬里上保留所述籽晶层；以及
其中步骤(k)不包括从覆盖所述介质层的所述上表面的所述导电层的所述区域除去所述籽晶层。
17.根据权利要求15的方法，还包括：
在所述介质层中形成到所述衬底中的I/O接线端焊盘的过孔。
18.如权利要求17的方法，还包括：
在所述介质层中形成过孔，所述过孔与所述I/O接线端对准；
在所述的衬底上形成聚酰亚胺层，所述聚酰亚胺层与所述介质层中的所述过孔对准；以及
在所述聚酰亚胺层中形成过孔，所述聚酰亚胺层中的所述过孔与所述I/O接线端对准并限定引线接合焊盘。
19.根据权利要求17的方法，还包括形成通过所述聚酰亚胺层和所述介质层中的过孔接触所述I/O接线端焊盘的焊料球连接。
20.根据权利要求19的方法，其中所述形成所述焊料球连接的步骤包括蒸发或溅射焊盘限制冶金层和籽晶层，并电镀Pb层或Pb/Sn合金层。
21.根据权利要求15的方法，其中
步骤(c)包括在所述介质层中形成到所述衬底中的I/O接线端焊盘的过孔；
步骤(d)包括在所述介质层中的所述过孔中形成保形导电衬里；
步骤(g)包括在所述抗蚀剂层中形成沟槽，所述沟槽与所述介质层中的所述过孔对准，所述沟槽的底部开口到所述介质层中的所述过孔；以及
步骤(h)包括电镀Cu以完全填充所述介质层中的所述过孔并至少部分地填充所述沟槽，以形成凸起接触焊盘。
22.根据权利要求21的方法，还包括形成接触所述凸起接触焊盘的焊料球连接。
23.根据权利要求22的方法，其中所述形成所述焊料球连接的步骤包括通过与所述衬底对准的掩膜蒸发或溅射焊盘限制冶金层和Pb层或Pb/Sn合金层。
24.根据权利要求22的方法，其中所述形成所述焊料球连接部分包括溅射焊盘限制冶金层和籽晶层以及电镀Pb层或Pb/Sn合金层。
25.根据权利要求15的方法，其中形成所述下沟槽进入所述介质层预定距离。
26.根据权利要求25的方法，其中
步骤(c)包括形成到所述衬底中的下通连接布线的过孔，所述过孔在所述下沟槽的下表面中形成；以及
步骤(h)包括电镀Cu以完全填充所述下沟槽的所述下表面中的所述过孔。
27.根据权利要求15的方法，其中所述导电钝化层包括Ni层或Ni层上Au层。
28。根据权利要求15的方法，其中所述上和下沟槽是螺旋形沟槽，以及所述电感器是螺旋形电感器。
29.根据权利要求15的方法，其中所述介质层包括与SiO2层的上表面接触的Si3N4上层，所述SiO2层与Si3N4下层的上表面接触。
30.根据权利要求15的方法，其中步骤(h)电镀Cu到至少5微米的深度。
31.一种半导体结构，包括：
具有上表面、下表面和侧壁的电感器，所述电感器的下部延伸固定距离进入半导体衬底上形成的介质层中，且上部在所述介质层上延伸；以及
电接触所述电感器的装置。
32.根据权利要求31的结构，其中所述电感器的所述下部包括导电衬里和芯导体，以及所述电感器的所述上部包括所述芯导体。
33.根据权利要求32的结构，其中所述芯导体是Cu，以及所述衬里包括TaN和Ta的双层。
34.根据权利要求32的结构，其中所述上部还包括在所述电感器的所述上部的上表面和侧壁上的导电钝化层。
35.根据权利要求34的结构，其中所述导电钝化层包括Ni层或Ni层上Au层。
36.根据权利要求31的结构，其中所述电感器具有大于约5微米的由所述侧壁限定的高度。
37.根据权利要求31的结构，其中所述下部延伸进入所述介质层小于3微米的距离。
38.根据权利要求31的结构，其中用于接触所述电感器的所述装置包括从所述电感器的所述底部延伸通过所述介质层并电接触所述衬底中的串通冶金的整体过孔。
39.根据权利要求38的结构，其中所述过孔上的所述电感器的所述上表面比不在所述过孔上的所述电感器的所述上表面的部分更靠近所述介质层的上表面。
40.根据权利要求31的结构，其中所述电感器平行于螺旋形线圈中的所述介质层的上表面延伸。
41.根据权利要求40的结构，其中所述电感器为约2至30微米宽，且所述螺旋形线圈的相邻线圈间隔约2至20微米。
42.根据权利要求31的结构，其中所述电感器具有大于约0.5nH的电感。
43.根据权利要求31的结构，其中所述电感器具有大于约25的Q因子。
44.根据权利要求31的结构，其中所述电感器具有大于约40的Q因子。
45.根据权利要求31的结构，还包括接触焊盘，该接触焊盘包括在所述介质层中形成的过孔，所述过孔暴露所述衬底中的至少部分I/O接线端焊盘，所述过孔的侧壁和至少部分所述I/O接线端焊盘被导电衬里上的保形籽晶层上的钝化层覆盖。
46.根据权利要求45的结构，其中所述导电衬里包括TaN和Ta的双层，所述籽晶层包括Cu，以及所述钝化层包括Ni层或Ni层上Au层。
47.权利要求46的结构，还包括导电接合到所述接触焊盘的Al或Au布线。
48.根据权利要求46的结构，还包括所述钝化层上的焊盘限制冶金层和所述焊盘限制冶金上的焊料球。
49.根据权利要求48的结构，其中所述焊盘限制冶金包括选自Cr层、CrCu层、Au层、Cu层和TiW层的一层或多层，以及所述焊料球包括Pb或Pb/Sn合金。
50.根据权利要求45的结构，其中所述电感器的所述上表面处于与所述接触焊盘的上表面不同的平面。
51.根据权利要求45的结构，其中所述电感器的上表面相对于所述介质层的上表面高于所述接触焊盘的所述上表面。
52.根据权利要求31的结构，还包括
在所述衬底中形成的I/O接线端焊盘；以及
与所述I/O接线端焊盘电接触的凸起接触焊盘，所述凸起接触焊盘具有上表面、下表面和侧壁，所述电感器的下部延伸所述固定距离进入半导体衬底上形成的所述介质层中，且上部在所述介质层上延伸。
53.根据权利要求52的结构，其中所述凸起接触焊盘的所述下部包括导电衬里和芯导体，以及所述凸起接触焊盘的所述上部包括所述芯导体。
54.根据权利要求53的结构，其中所述芯导体是Cu，以及所述衬里包括TaN和Ta的双层。
55.根据权利要求53的结构，其中所述上部还包括所述凸起接触焊盘的所述上部的所述上表面和侧壁上的导电钝化层。
56.根据权利要求55的结构，其中所述钝化层包括Ni层或Ni层上Au层。
57.根据权利要求56的结构，还包括导电接合到所述凸起接触焊盘的Al或Au布线。
58.根据权利要求56的结构，还包括所述钝化层上的焊盘限制冶金层和所述焊盘限制冶金上的焊料球。
59.根据权利要求58的结构，其中所述焊盘限制冶金包括选自Cr层、CrCu层、Au层、Cu层和TiW层的一层或多层，以及所述焊料球包括Pb或Pb/Sn合金。
60.根据权利要求52的结构，其中所述电感器的所述上表面处于与所述凸起接触焊盘的上表面不同的平面。
61.根据权利要求52的结构，其中所述电感器的上表面相对于所述介质层的上表面高于所述凸起接触焊盘的所述上表面。
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