CN109155309A - 具有背侧集成式电感组件的半导体裸片 - Google Patents

具有背侧集成式电感组件的半导体裸片 Download PDF

Info

Publication number
CN109155309A
CN109155309A CN201780028562.9A CN201780028562A CN109155309A CN 109155309 A CN109155309 A CN 109155309A CN 201780028562 A CN201780028562 A CN 201780028562A CN 109155309 A CN109155309 A CN 109155309A
Authority
CN
China
Prior art keywords
substrate
active circuit
induction structure
layer
coil
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201780028562.9A
Other languages
English (en)
Other versions
CN109155309B (zh
Inventor
本杰明·史塔生·库克
罗伯托·嘉姆彼罗·马索利尼
丹尼尔·卡罗瑟斯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of CN109155309A publication Critical patent/CN109155309A/zh
Application granted granted Critical
Publication of CN109155309B publication Critical patent/CN109155309B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/10—Inductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H01L21/30655—Plasma etching; Reactive-ion etching comprising alternated and repeated etching and passivation steps, e.g. Bosch process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H01L27/0694—Integrated circuits having a three-dimensional layout comprising components formed on opposite sides of a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/40227—Connecting the strap to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73255—Bump and strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73257—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81205—Ultrasonic bonding
    • H01L2224/81207—Thermosonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Plasma & Fusion (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

在所描述的实例中，一种集成电路IC(300)包含电路衬底(301)，所述电路衬底(301)具有前侧表面(320)和相对背侧表面。有源电路位于所述前侧表面(320)上。电感结构(310)位于深沟槽内，所述深沟槽在电路衬底(301)中形成于所述背侧表面下方。所述电感结构(310)耦合(343、344)到所述有源电路。

Description

具有背侧集成式电感组件的半导体裸片
技术领域
这涉及集成电路的制造，以及更具体地说，涉及电感组件在半导体裸片的背侧上的制造。
背景技术
有时，在集成电路(IC)内实施的电路需要电感组件。电感组件可通过在IC的金属层中的一或多个上形成线圈制造而成；然而，这种组件的电感局限于相对低的值。然而，考虑到每平方典型金属层的极高电阻，形成在IC的金属层中的电感器的品质因数可能有限。通常，这种电感器可仅用于超高频(UHF)电路，例如300MHz-3GHz频率范围。此外，其可能会造成显著开关损耗。
当前，例如开关模式DC-DC转换器等硅IC使用共同封装的离散电感器，所述共同封装的离散电感器大而笨重，从而造成封装复杂性，且可占据封装成本的很大百分比。
发明内容
在所描述的实例中，集成电路(IC)包含电路衬底，所述电路衬底具有前侧表面和相对背侧表面。有源电路位于前侧表面上。电感结构位于深沟槽内，所述深沟槽在电路衬底中形成于背侧表面下方。电感结构耦合到有源电路。
附图说明
图1是制造在IC的背侧上的实例电感器的图示。
图2是制造在IC的背侧上的实例耦合电感器的图示。
图3到5说明将背侧电感器连接到IC的有源电路的各种方式。
图6A到6G说明一种用于在IC的背侧上形成电感组件的方法。
图7A到7B说明替代实施例，其中使用打印机沉积晶种层。
图8A到8B说明实例背侧电感器的模拟结果。
图9说明电感器形成在多个衬底层中的另一实施例。
图10是包含具有背侧电感器的IC的实例系统的框图。
图11是包含具有使用多个金属化层形成的背侧电感器的IC的实例系统的框图。
具体实施方式
出于一致性，在图中相似元件由相似附图标记标示。
硅IC的广泛组合要求电感器，所述电感器由于有限大小、电流容量和在金属层集成式电感器内可获得的效率而无法集成在金属堆叠内。可要求无法在IC的金属层内实施的电感器的功能可包含：滤波输出电压和电流；存储循环递送的能量；提供一种从两个或多于两个电压域移动能量的高效方式；执行辅助功能，例如提供绝热栅极驱动器和零电压转变；等。
大部分IC制造在硅衬底上，其中硅衬底的大部分通常仅需要来以机械方式支撑在硅衬底的表面上形成的有源装置。在本文中所描述的方法中，电感器或者两个或多于两个耦合电感器可形成在未使用的块状硅衬底内。实例实施例可用于实施各种功能，例如上文所描述的那些。
图1是制造在电路衬底101的背侧上的实例螺旋电感器110的图示。在此实例中，电感器110具有外部端点111和内部端点112。在此实例中，衬底101是硅裸片，所述硅裸片形成集成电路且包含形成在衬底101的另一侧上的有源电路。实例实施例可通过以下方式将电感器并入到未使用的裸片硅中：将沟槽蚀刻到硅的背侧中，且使用经蚀刻沟槽区域来实施高密度、高质量因数(Q)电感器。品质因数Q是电感器的效率的度量；高Q电感器指示电感器将是高效的低损耗电感器。
实例实施例本质上将电感器110集成到硅衬底101中。这意味着通过在硅晶片上进行三维(3D)后处理，将可能具有共同封装的方案而无需复杂且昂贵的封装技术，例如裸片上芯片、SIP等。
实例实施例的大小可小于其它已知方案。而非将硅IC和电感器并列放置，这将实现“竖直”集成，从而节省了总方案硅面积。
前一方案可包含层压空气磁芯电感器或玻璃纤维印刷电路板(PCB)，例如FR4级PCB材料。另一前一方案可包含闭合磁芯芯片电感器。不幸的是，闭合磁芯电感器受磁芯饱和困扰。因此，其中需要极大峰值电流的应用程序对于闭合磁芯电感器可能不可行。
实例实施例可得益于具有长得多的铜迹线以向相同电感提供更低DCR(直流电阻)，且因此得益于高Q。长的铜迹线可允许极大峰值电流用于需要大的峰值电流的应用程序。长的铜迹线还可通过提供更好的配置以实现邻近效应而提高ACR(交流电阻)。
如下文中所描述，一种用于在块状硅衬底中的沟槽中形成电感器的过程可为廉价过程。
图2是制造在IC衬底201的背侧上的实例耦合电感器的图示。在此实例中，第一螺旋形线圈210包围第二螺旋形线圈212。此配置允许由线圈中的一个产生的磁场与另一线圈耦合且在另一线圈中产生电流。线圈210具有端点213、214，且线圈212具有端点215、216。下文中描述将线圈端点处的接触点耦合到电路衬底的另一侧上的有源电路的各种方式。
在另一实施例中，两个线圈可内插以实现改进的耦合。
在另一实施例中，第一线圈可形成在第一衬底层中，且接着第二衬底层可形成在第一衬底层上，且第二线圈接着可形成在第二衬底层中的沟槽中，如下文中所描述。
虽然在图1和2中说明圆形螺旋形线圈，但其它实施例可使用其它形状，例如卵形、矩形等。
图3是实例IC 300的横截面视图，其说明一种将背侧电感器310连接到IC 300的有源电路的方式。IC 300包含块状硅衬底301，其中电感器310形成在沟槽中，如下文中所描述。
外延(epi)硅层320可形成在衬底301的一侧上。厚的epi层可有利于功率半导体和基于MEMS的传感器和致动器。“厚的”是相对术语。当今，大于20pm的epi膜被视为厚的，但膜的厚度的开发目标可多达～150μm。无掺杂厚的epi膜的电绝缘品质可向功率半导体提供益处。所述电绝缘品质实现具有更大R(断开)值的更高电压，且促成更高切换速度和减小的装置占用空间。可使用已知制造技术在epi层320中形成各种晶体管。
接着可使用已知或稍后建立的过程在例如二氧化硅等绝缘层之间形成例如铜等金属的多个层以形成多层互连330，所述多层互连330与各种晶体管连接以形成有源电路。
在此实例中，IC 300被制造为“倒装芯片”。倒装芯片是一种用于利用已经沉积到芯片焊盘上的焊料凸块342将例如IC芯片和微机电系统(MEMS)等半导体装置互连到外部电路的方法。焊料凸块可在最终晶片处理步骤期间沉积在晶片的顶侧上的芯片焊盘上。为了将芯片安装到封装衬底340(例如，引线框架、电路板或者另一芯片或晶片)，所述芯片被翻转，从而使得其顶侧面向下，且被对准成使得其焊盘与引线框架340的外部电路上的匹配焊盘341对准，且接着焊料回焊以完成互连。这与导线接合形成对比，在导线接合中芯片被直立安装且导线用于将芯片焊盘互连到外部线路或引线框架。
处理倒装芯片类似于常规IC制造，其中具有几个额外步骤。在接近制造过程结束时，使附接焊盘金属化以使其更易于接收焊料。这通常由若干处理构成。最近，使用一种过程，在所述过程中金属柱形成在每个金属化的附接焊盘上以延长接触长度。接着可在每个金属化焊盘上沉积小的焊料点。替代地，可将焊料点放置在引线框架上。接着通常从晶片切掉芯片。
为了将倒装芯片附接到电路中，芯片被倒转以将焊料点向下带到底层引线框架或电路板上的连接器上。接着通常使用热超声接合或替代地回焊过程重新熔融焊料以产生电连接。
在此实施例中，导线接合过程可用于将电感线圈310耦合到IC 300的epi层320中的有源电路。在此实例中，导线接合343将线圈310的外侧端点311耦合到封装衬底340上的接触焊盘345。类似地，导线接合344将线圈310的内侧端点312耦合到封装衬底340上的接触焊盘346。铜或其它类型的金属迹线接着可将接触焊盘345、346耦合到其它接触焊盘341且由此耦合到epi层320内的有源电路。
在另一实例中，接合夹具可用于将电感线圈310耦合到IC 300的epi层320中的有源电路。接合夹具大于接合导线且提供大得多的载流容量。
图4是实例IC 400的横截面视图，其说明一种将背侧电感器410连接到IC 400的有源电路的方式。IC 400包含块状硅衬底401，其中电感器410形成在沟槽中，如下文中所描述。
如上文所描述，epi层420可形成在块状衬底401的一个表面上。各种晶体管可制造在epi层420中以形成由多层互连430互连的有源电路。
在此实例中，硅裸片直立安装在封装衬底440上，所述封装衬底440可为引线框架或其它类型的衬底，例如电路板。焊料凸块443可用于将线圈410的外部末端耦合到衬底440上的焊盘。类似地，焊料凸块444可用于将线圈410的内部末端耦合到衬底440上的焊盘。
导线接合441、441接着可从衬底440上的引线耦合到互连层430上的焊盘446且由此耦合到具有epi层420的晶体管。类似地，额外导线接合(未示出)可从互连层530中的其它焊盘耦合到衬底440以便向/从epi层420中的有源电路路由其它信号。
图5是实例IC 500的横截面视图，其说明一种将背侧电感器510连接到IC 500的有源电路的方式。IC 500包含块状硅衬底501，其中电感器510形成在沟槽中，如下文中所描述。
如上文所描述，epi层520可形成在块状衬底501的一个表面上。各种晶体管可制造在epi层520中以形成由多层互连530互连的有源电路。
在此实例中，“硅穿孔(TSV)”用于将背侧电感器510与epi层520中的有源电路互连。举例来说，TSV 541可用于将线圈510的外侧末端耦合到互连层530中的焊盘且由此耦合到epi层530中的有源电路。类似地，TSV 542可用于将线圈510的内侧末端耦合到互连层530中的焊盘且由此耦合到epi层530中的有源电路。
在一些实施例中，额外TSV，例如TSV 543中的任一个，可用于将电感器510的各种回路上的额外接触点连接到epi层530中的有源电路。举例来说，这可允许使用开关晶体管针对各种需要配置线圈。各种实施方案可包含：通过实现更少或更多匝调谐线圈、并行配置匝等。
在一些实施例中，可使用倒装芯片技术封装IC 500以完成epi层520中的有源电路与引线框架或衬底之间的剩余连接，类似于图3。在其它实施例中，IC 500可以常规自顶向上配置安装在引线框架或衬底上，其中接合导线可用于完成epi层520中的有源电路与引线框架或衬底之间的剩余连接，类似于图4。其它实施例可使用其它已知或稍后建立的封装和互连技术来互连到IC 500，而TSV用于将一或多个背侧线圈连接到衬底的前表面上的有源电路。
图6A到6G是硅晶片601的一部分的横截面视图，其说明一种用于在IC的背侧上形成电感组件的方法，如上文所描述。可在前侧已经被处理以制造集成电路阵列之后对硅晶片的背侧执行所述方法。替代地，可首先形成背侧电感组件，且接着可在硅晶片的前表面上制造有源电路。
存在用于在硅晶片上制造半导体电路的常规过程。通常，在单个硅晶片上制造数百个IC裸片。接着可使用测试探针测试完成的电路以启动监视个别电路裸片。接着可使用已知或稍后建立的过程将晶片切割成个别裸片，附接到引线框架或其它衬底、进行封装和最终测试。
图6A到6F仅说明硅晶片601的背侧。为简单起见未示出前侧上的电路，或尚可能不存在。图6A说明硅晶片601的形成衬底的一部分。将二氧化硅的层650沉积在衬底601的背表面上。在二氧化硅层650上方涂覆抗蚀剂层652且可使用已知或稍后建立的光刻过程使所述抗蚀剂层652图案化以形成用于下一步深度硅蚀刻的掩模。可使掩模图案化以形成螺旋形或其它形状的沟槽，或用于一或多个背侧电感器的多个螺旋，例如图1和2中所示出。
图6B说明可使用若干过程中的一个形成在衬底601的块状硅中的实例沟槽，所述若干过程例如深度反应性离子蚀刻或博世(Bosch)硅蚀刻。首先，可使用光掩模层652执行硬掩模层650的化学蚀刻。以德国公司Robert Bosch GmbH命名的博世过程也被称为脉冲或时分多路传输蚀刻。博世过程在两种模式之间反复地交替以实现几乎竖直的结构。第一模式是标准的几乎各向同性等离子体蚀刻。等离子体包含从几乎竖直方向上侵蚀晶片的离子。六氟化硫[SF6]通常用于硅。第二模式是化学惰性钝化层的沉积。举例来说，C4F8(八氟环丁烷)气体产生类似于特氟龙的物质。
每个阶段持续若干秒。表面上的硬掩模650和沟槽的侧面上的钝化层保护整个衬底不受进一步化学侵蚀且防止进一步蚀刻。然而，在蚀刻阶段期间，轰击衬底的方向性离子侵蚀沟槽底部的钝化层，同时使侧面大体上不受影响。离子与沟槽底部的钝化层碰撞且将钝化层溅射出来，从而使沟槽底部的衬底暴露于化学蚀刻剂。这些蚀刻/沉积步骤被重复许多次，从而导致大量极小各向同性蚀刻步骤仅发生在蚀刻凹坑底部。举例来说，为了在硅晶片中蚀刻500μm深沟槽，可能需要100到1000次蚀刻/沉积步骤。二阶段过程可使侧壁例如以约100到500nm的幅度起伏。可调节周期时间：短周期产生更光滑的壁，且长周期产生更高蚀刻速率。
举例来说，对于大致750μm厚的硅衬底，用于背侧电感器的实施例的沟槽654可被蚀刻到25到500μm的深度。可在沟槽的深度对线圈的直径和衬底的厚度进行取舍以便维持用于衬底的机械强度的适当块状材料。
图6C说明在清洗晶片、剥离光刻抗蚀剂层652和移除在形成沟槽654期间使用的钝化层聚合物之后的衬底601。
图6D说明在沟槽654内侧上形成电介质表面隔离655之后的衬底601。各种化合物可用于形成电介质表面隔离655，例如：A1203、氮化硅、二氧化硅或其它非导电电介质材料的原子层沉积(ALD)。
图6E说明在衬底601和沟槽654的表面上方形成金属晶种层656之后的衬底601。金属晶种层656可使用例如原子层沉积等已知或稍后建立的过程选自各种金属化合物，例如：氮化钛(TiN)、钛钨(TiW)等。
图6F说明在使用电镀过程形成铜填充层657之后的衬底601，其中镀铜黏附到金属晶种层656。
图6G说明在背侧研磨过程用于移除金属板657的表面部分以及掩模层650以在衬底601的背侧上形成平滑表面658之后几乎完成的IC 600。
包含各种晶体管和互连层630的epi层620还在图6G中说明为在衬底601的前侧上。如上文所描述，epi层620和互连层630中的有源电路可在形成背侧电感器654之前或之后制造。
背侧电感器与epi层620中的有源电路之间的连接可以各种方式完成，例如图3、4或5中说明的那些。
图7A说明替代实施例，其中使用打印机沉积晶种层756代替图6E中所说明的金属晶种层656。图7A说明将包含金属纳米粒子的一系列小滴761沉积到沟槽654中的喷墨打印机760。喷墨打印机或类似打印机可“打印”各种聚合物材料以制造三维结构。举例来说，参见2014年9月4日的维基百科“3D打印”。打印实现快速和低成本地沉积厚的电介质和金属层，例如100μm到1000μm厚，同时还实现精细特征大小，例如20um特征大小。
墨水可包含用以匹配流变性和表面张力的一种溶剂或若干溶剂，和金属纳米粒子。举例来说，纳米颗粒的大小可在2到100nm的范围内。墨水还可包含例如聚乙烯吡咯啶酮(PVP)等分散剂或被分散带电以防止颗粒附聚。墨水还可包含例如环氧聚合物等粘合剂，和其它已知或稍后建立的墨水添加剂。
接着可在溶剂或分散剂在其中蒸发的溶剂或分散剂类墨水的情况下固化从墨水留下的膜残余物。固化可为热的(50到250C或更高)、UV、红外、闪光灯、或与正使用的墨水兼容的另一形式。
在此实例中，形成晶种层756的金属纳米粒子可为铜、TiN或TiW。
图7B说明在使用电镀过程形成铜填充层757之后的衬底701，其中镀铜黏附到金属晶种层756。在此实例中，因为电镀过程仅黏附到沟槽654底部的晶种层，所以没有镀铜沉积在衬底601的表面上。因此，在此实施例中无需如图6G中所说明的背侧研磨过程。
在另一实施例中，可使用喷墨过程用铜充满整个沟槽654。
图8A到8B说明类似于上文所描述的那些的实例背侧电感器的模拟结果。在此模拟中，电感器具有5mm的直径且具有含两个匝的螺旋形线圈。模拟沟槽是150um深和70um宽，同时具有150um沟槽间隔。如图8A中所说明，在10MHz下，电感大致是18nH。如图8B中所说明，在10MHz下，Q大致是16。DC电阻大致是36mOhm。
图8A到8B说明背侧电感器的性能在1到100MHz的频率范围内相当地稳定。
图9说明IC 900的另一实施例，其中电感器形成在多个衬底层中。在此实例中，电感器910可制造在如上文所描述的第一衬底层901中且使用例如TSV 941、942等TSV互连到epi层920和互连层930中的有源电路。举例来说，可使用一或多个TSV 943形成额外连接。
在此实施例中，具有衬底层961的第二晶片可接合到第一衬底层901。举例来说，绝缘层960(例如二氧化硅)可形成在两个晶片上，且接着两个晶片可与绝缘层堆叠在一起且接合在炉中以形成单个晶片。
第二电感器911接着可形成在第二衬底层961中，如上文所描述。第二电感器911可经由凸块944、945耦合到引线框架或其它衬底940且由此使用与焊盘947的导线接合946耦合到epi层920中的有源电路，例如上文结合图4所描述。
在另一实施例中，IC 900可封装为倒装芯片，例如结合图3所描述。
系统实例
图10是包含具有背侧电感器的IC 1001的实例系统1000的框图。在此实例中，有源电路1020耦合到电感器1010，所述电感器1010形成在IC 1001的背侧上。举例来说，电感器1010可使用上文结合图3到5所描述的技术中的任一种耦合到有源电路1020。
系统1000可使用电感器1010以用于各种功能，例如：滤波输出电压和电流；存储循环递送的能量；提供一种从两个或多于两个电压域移动能量的高效方式；执行辅助功能，例如提供绝热栅极驱动器和零电压转变；等。
在一些实施例中，可包含耦合到有源电路1022的第二电感器1012。电感器1012还可形成在IC 1001的背侧上，如上文更详细地描述。举例来说，电感器1012可使用上文结合图3到5所描述的技术中的任一种耦合到有源电路1022。
在此实例中，电感器1010经配置以电感耦合到电感器1012。在另一实例中，可存在电感器中的仅一个。
而且，例如，系统1000可使用电感器1010和1012两者以提供变压器隔离。
系统1000可包含额外IC和安装在系统衬底1002上的其它组件以使用已知或稍后建立的技术提供特定功能。举例来说，系统衬底1002可为印刷电路板。
图11是包含IC 1100的实例系统的框图，所述IC 1100具有使用可产生多个金属化层1170、1172的3D打印在衬底1101中形成的背侧电感器。有源电路可制造在有源层1120中的衬底1101的前侧上，如上文所描述。在此实例中，可如上文所描述制造螺旋形沟槽1110。接着可如参考图7A、晶种层756更详细描述地对铜晶种层进行3D打印。接着可使用电镀过程制造铜填充层1170，如参考图7B、填充层757更详细地描述。在此实例中，当沟槽1110仅被部分地填充时可停止填充层1170。
接着可在沟槽1110内3D打印绝缘层1171以覆盖铜填充层1170且使铜填充层1170绝缘。接着，可以类似方式制造第二晶种层和填充层1172。在此实例中，可在沟槽1110内3D打印另一绝缘层1173以覆盖铜填充层1172且使铜填充层1172绝缘。可通过对导电柱进行3D打印来提供接触焊盘(例如焊盘1174、1175)。替代地，铜填充层1172可延伸到衬底1101的表面，类似于图7B中的铜填充层757。
取决于每个铜填充层1170、1172的经选择厚度和衬底1101中的沟槽1110的深度，可以此方式制造电感线圈的两个或多于两个层。在此实例中，说明两个单独线圈1170和1172。举例来说，硅衬底1101可大致是300um厚，而每个铜填充层1170、1172大致是100μm厚。TSV 1176、1177可被提供来将下部线圈1170连接到层1120中的有源电路，如参考图5更详细地描述，而接合导线、接合夹具等可用于将线圈1172耦合到层1120中的有源电路，如参考图3、4更详细地描述。在此实例中，电感结构1170、1172具有大致1mm的半径且耦合到有源层1120中的以大致5MHz的频率切换的开关电路。
在另一实例中，由铜填充层1170形成的线圈可与形成在铜填充层1172中的线圈串联连接以通过对两个线圈之间的接触进行3D打印来形成单个线圈。
其它实施例
本文中已经描述了形成在硅衬底中的背侧电感器的实施例，但可使用其它类型的半导体衬底实施形成在半导体衬底的背侧上且与半导体衬底的前侧上的有源电路互连的一或多个电感器的其它实施例，所述其它类型的半导体衬底例如锗、碳、锑、砷化镓、氮化镓等。在另一实施例中，可使用例如玻璃或蓝宝石等非半导体衬底。
在另一实施例中，IC可基于“绝缘体上硅”技术，且在使用块状绝缘体时背侧电感器可形成在绝缘层中。举例来说，在“蓝宝石上硅”技术中，绝缘体可为蓝宝石。在此情况下，一或多个背侧电感器可形成在蓝宝石衬底中。对于硅-绝缘体-硅技术，一或多个背侧电感器可形成在衬底的块状硅部分中。
本文中描述铜用于形成背侧电感器的导电线圈，但其它导电金属、化合物或聚合物可用于形成线圈，例如：银、金、锡、碳、石墨、多晶硅等。
本文中描述用于形成线圈的电镀过程，但其它实施例可使用旋涂浆料填充沟槽来形成线圈。用于金属沉积的其它已知或稍后建立的技术可用于填充沟槽。
本文中描述其中形成电路晶体管的厚的epi层，但取决于用于形成有源电路的半导体过程，其它实施例可使用薄的epi层，或不使用epi层。在任何情况下，如本文中所使用，术语“位于前侧表面上的有源电路”是指可(或可不)形成在epi层中的电路。而且，例如，所述位于前侧表面上的有源电路是指可由一或多个互连层和一或多个额外保护层覆盖的电路。
本文中描述圆形螺旋形沟槽，但其它实施例可使用其它配置用于背侧线圈，例如卵形、正方形/矩形等。
在不脱离所描述的功能性的情况下，数字系统中的组件可用不同名称提及和/或可通过本文中未示出的方式组合。在本说明书中，术语“耦合”及其派生词意味着间接、直接、光学和/或无线电连接。因此，如果第一个装置耦合到第二个装置，那么所述连接可通过直接电连接、通过其它装置和连接的间接电连接、通过光学电连接和/或通过无线电连接。而且，在术语“耦合”参考耦合两个线圈使用的情况下，所述用途是指电磁耦合。
尽管本文中可以顺序方式呈现和描述方法步骤，但可省略、重复、同时执行、和/或以与图中所示出和/或本文中所描述的次序不同的次序执行所示出和描述的步骤中的一或多个。因此，实例实施例不限于图中所示出和/或本文中所描述的步骤的具体次序。
对所描述的实施例的修改是可能的，且在权利要求书的范围内的其它实施例是可能的。

Claims (20)

1.一种集成电路IC，其包括：
电路衬底，其具有前侧和相对背侧；
有源电路，其位于所述前侧上；以及
电感结构，其嵌入于深沟槽内，所述深沟槽在所述电路衬底中形成于所述背侧上。
2.根据权利要求1所述的IC，其进一步包含在所述电路衬底中嵌入于所述背侧上的多个电感结构，所述多个电感结构经配置以彼此电感耦合。
3.根据权利要求1所述的IC，其中所述电感结构通过所述电路衬底中的硅穿孔连接到所述有源电路。
4.根据权利要求1所述的IC，其进一步包含封装衬底，其中所述电路衬底安装在所述封装衬底上，使得所述有源电路的接触焊盘凸点接合到封装衬底上的引线，且其中所述电感结构经由从所述引线到所述电感结构上的接触点的导线接合连接到所述有源电路。
5.根据权利要求1所述的IC，其进一步包含封装衬底，其中所述电路衬底安装在所述封装衬底上，使得所述电感结构上的接触点凸点接合到所述封装衬底上的引线，且其中导线接合将所述有源电路耦合到所述引线且由此耦合到所述电感结构。
6.根据权利要求1所述的IC，其中所述深沟槽具有在大致25到500um的范围内的深度。
7.根据权利要求1所述的IC，其中所述深沟槽的深度为宽度的至少四倍。
8.根据权利要求2所述的IC，其中所述电路衬底包含通过绝缘层分开的第一衬底层和第二衬底层，其中所述多个电感结构中的第一电感结构形成在所述第一衬底层中，且其中所述多个电感结构中的第二电感结构形成在所述第二衬底层中。
9.根据权利要求1所述的IC，其中所述电路衬底是绝缘体上硅衬底，且其中所述沟槽形成在所述电路衬底的绝缘体部分中。
10.根据权利要求4所述的IC，其中所述封装衬底是引线框架。
11.一种系统，其包括：
系统衬底；以及
集成电路IC，其安装在所述系统衬底上，其中所述IC包含：
电路衬底，其具有前侧表面和相对背侧表面；
有源电路，其位于所述前侧表面上；以及
电感结构，其位于深沟槽内，所述深沟槽在所述电路衬底中形成于所述背侧表面下方，其中所述电感结构耦合到所述有源电路。
12.根据权利要求11所述的系统，其进一步包含封装衬底，其中所述电感结构经由所述封装衬底耦合到所述有源电路。
13.一种用于制造具有集成式电感组件的集成电路的方法，所述方法包括：
在所述集成电路IC的电路衬底的前侧上制造有源电路；
将深沟槽蚀刻到所述电路衬底的背侧中；
用导电材料填充所述沟槽以形成线圈；以及
将所述线圈耦合到所述有源电路。
14.根据权利要求13所述的方法，其中蚀刻深沟槽形成用于经配置以彼此电感耦合的多个线圈的多个深沟槽。
15.根据权利要求13所述的方法，其进一步包含形成硅穿孔TSV以将所述线圈耦合到所述有源电路。
16.根据权利要求13所述的方法，其进一步包含：
将所述电路衬底安装在封装衬底上，使得所述有源电路的接触焊盘凸点接合到所述封装衬底上的引线；以及
经由从所述引线到所述电感结构上的接触点的导线接合将所述电感结构连接到所述有源电路。
17.根据权利要求13所述的方法，其进一步包含：
将所述电路衬底安装在封装衬底上，使得所述电感结构上的接触点凸点接合到所述封装衬底上的引线；以及
用导线接合将所述有源电路耦合到所述引线且由此耦合到所述电感结构。
18.根据权利要求13所述的方法，其中所述深沟槽被蚀刻到在大致25到500um的范围内的深度。
19.根据权利要求14所述的方法，其中所述电路衬底包含通过绝缘层分开的第一衬底层和第二衬底层，且其中所述多个线圈中的第一线圈形成在所述第一衬底层中；且所述方法进一步包含：
将第二深沟槽蚀刻到所述第二衬底层中；
用导电材料填充所述第二沟槽以形成第二线圈；以及
将所述第二线圈耦合到所述有源电路。
20.根据权利要求13所述的方法，其中所述电路衬底是绝缘体上硅衬底，且其中所述沟槽在所述电路衬底的绝缘体部分中被蚀刻。
CN201780028562.9A 2016-05-11 2017-05-11 具有背侧集成式电感组件的半导体裸片 Active CN109155309B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/152,518 US10032850B2 (en) 2016-05-11 2016-05-11 Semiconductor die with back-side integrated inductive component
US15/152,518 2016-05-11
PCT/US2017/032247 WO2017197173A1 (en) 2016-05-11 2017-05-11 Semiconductor die with backside integrated inductive component

Publications (2)

Publication Number Publication Date
CN109155309A true CN109155309A (zh) 2019-01-04
CN109155309B CN109155309B (zh) 2023-10-27

Family

ID=60267615

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201780028562.9A Active CN109155309B (zh) 2016-05-11 2017-05-11 具有背侧集成式电感组件的半导体裸片

Country Status (4)

Country Link
US (3) US10032850B2 (zh)
EP (1) EP3455880A4 (zh)
CN (1) CN109155309B (zh)
WO (1) WO2017197173A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180323254A1 (en) * 2016-05-11 2018-11-08 Texas Instruments Incorporated Semiconductor die with back-side integrated inductive component
CN110098739A (zh) * 2019-05-08 2019-08-06 宁波大学 一种基于片上电感器的dc-dc降压转换电路

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10872950B2 (en) * 2016-10-04 2020-12-22 Nanohenry Inc. Method for growing very thick thermal local silicon oxide structures and silicon oxide embedded spiral inductors
US11501908B2 (en) 2016-10-04 2022-11-15 Nanohenry, Inc. Miniature inductors and related circuit components and methods of making same
US20180323369A1 (en) 2017-05-02 2018-11-08 Micron Technology, Inc. Inductors with through-substrate via cores
US10121739B1 (en) 2017-05-02 2018-11-06 Micron Technology, Inc. Multi-die inductors with coupled through-substrate via cores
US10872843B2 (en) 2017-05-02 2020-12-22 Micron Technology, Inc. Semiconductor devices with back-side coils for wireless signal and power coupling
US20180323253A1 (en) * 2017-05-02 2018-11-08 Micron Technology, Inc. Semiconductor devices with through-substrate coils for wireless signal and power coupling
US10134671B1 (en) 2017-05-02 2018-11-20 Micron Technology, Inc. 3D interconnect multi-die inductors with through-substrate via cores
US10756161B2 (en) * 2018-06-27 2020-08-25 Intel Corporation Package-embedded thin-film capacitors, package-integral magnetic inductors, and methods of assembling same
US11101211B2 (en) 2019-09-26 2021-08-24 International Business Machines Corporation Semiconductor device with backside inductor using through silicon vias

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040041243A1 (en) * 2001-09-21 2004-03-04 Tsuyoshi Ogawa Thin film circuit board device and its manufacturing method
US20050099259A1 (en) * 2003-09-30 2005-05-12 Harris Edward B. Inductor formed in an integrated circuit
CN1649087A (zh) * 2004-01-29 2005-08-03 国际商业机器公司 形成电感器的方法以及半导体结构
US20050176215A1 (en) * 2004-02-09 2005-08-11 Samsung Electronics, Co., Ltd. Trench structure having a void and inductor including the trench structure
CN101110431A (zh) * 2006-07-18 2008-01-23 国际商业机器公司 具有高q晶片背面电感器的半导体集成电路器件及其制造方法
CN102176450A (zh) * 2011-03-22 2011-09-07 南通富士通微电子股份有限公司 高密度系统级封装结构
CN102956629A (zh) * 2011-08-17 2013-03-06 英特赛尔美国有限公司 背对背堆叠芯片
CN103229298A (zh) * 2010-11-18 2013-07-31 斯兰纳私人集团有限公司 具有电容性隔离的单片集成电路
CN104051334A (zh) * 2013-03-14 2014-09-17 联合科技(股份有限)公司 半导体封装和封装半导体装置的方法
CN104051392A (zh) * 2013-03-15 2014-09-17 日月光半导体制造股份有限公司 半导体晶片、半导体工艺和半导体封装
WO2015128479A1 (en) * 2014-02-28 2015-09-03 Lfoundry S.R.L. Method of fabricating a semiconductor device and semiconductor product

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6847105B2 (en) 2001-09-21 2005-01-25 Micron Technology, Inc. Bumping technology in stacked die configurations
US6989578B2 (en) 2003-07-31 2006-01-24 Taiwan Semiconductor Manufacturing Company Inductor Q value improvement
US7436281B2 (en) * 2004-07-30 2008-10-14 Texas Instruments Incorporated Method to improve inductance with a high-permeability slotted plate core in an integrated circuit
JP2008545274A (ja) 2005-06-30 2008-12-11 フェアチャイルド セミコンダクター コーポレイション 半導体ダイ・パッケージ及びその製造方法
CN101730918B (zh) * 2007-05-08 2013-03-27 斯卡尼梅特里科斯有限公司 超高速信号传送/接收
KR101452548B1 (ko) 2007-06-20 2014-10-21 스카이워크스 솔루션즈, 인코포레이티드 후면 수동 디바이스 집적을 이용하는 반도체 다이
US7842580B2 (en) * 2008-05-19 2010-11-30 International Business Machines Corporation Structure and method for buried inductors for ultra-high resistivity wafers for SOI/RF SiGe applications
JP5578797B2 (ja) * 2009-03-13 2014-08-27 ルネサスエレクトロニクス株式会社 半導体装置
US20120018892A1 (en) * 2010-07-22 2012-01-26 Mehdi Frederik Soltan Semiconductor device with inductor and flip-chip
CN102376693B (zh) 2010-08-23 2016-05-11 香港科技大学 单片磁感应器件
WO2013098929A1 (ja) * 2011-12-26 2013-07-04 株式会社ザイキューブ 半導体チップ及びそれを搭載した半導体モジュール
US20160149122A1 (en) * 2013-06-14 2016-05-26 The Trustees Of Dartmouth College Methods For Fabricating Magnetic Devices And Associated Systems And Devices
US9953892B2 (en) * 2015-11-04 2018-04-24 Taiwan Semiconductor Manufacturing Company, Ltd. Polymer based-semiconductor structure with cavity
US10032850B2 (en) * 2016-05-11 2018-07-24 Texas Instruments Incorporated Semiconductor die with back-side integrated inductive component

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040041243A1 (en) * 2001-09-21 2004-03-04 Tsuyoshi Ogawa Thin film circuit board device and its manufacturing method
US20050099259A1 (en) * 2003-09-30 2005-05-12 Harris Edward B. Inductor formed in an integrated circuit
CN1649087A (zh) * 2004-01-29 2005-08-03 国际商业机器公司 形成电感器的方法以及半导体结构
US20050176215A1 (en) * 2004-02-09 2005-08-11 Samsung Electronics, Co., Ltd. Trench structure having a void and inductor including the trench structure
CN1722364A (zh) * 2004-02-09 2006-01-18 三星电子株式会社 具有空腔的沟槽结构以及包括沟槽结构的电感器
CN101110431A (zh) * 2006-07-18 2008-01-23 国际商业机器公司 具有高q晶片背面电感器的半导体集成电路器件及其制造方法
CN103229298A (zh) * 2010-11-18 2013-07-31 斯兰纳私人集团有限公司 具有电容性隔离的单片集成电路
CN102176450A (zh) * 2011-03-22 2011-09-07 南通富士通微电子股份有限公司 高密度系统级封装结构
CN102956629A (zh) * 2011-08-17 2013-03-06 英特赛尔美国有限公司 背对背堆叠芯片
CN104051334A (zh) * 2013-03-14 2014-09-17 联合科技(股份有限)公司 半导体封装和封装半导体装置的方法
CN104051392A (zh) * 2013-03-15 2014-09-17 日月光半导体制造股份有限公司 半导体晶片、半导体工艺和半导体封装
WO2015128479A1 (en) * 2014-02-28 2015-09-03 Lfoundry S.R.L. Method of fabricating a semiconductor device and semiconductor product

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180323254A1 (en) * 2016-05-11 2018-11-08 Texas Instruments Incorporated Semiconductor die with back-side integrated inductive component
US10692964B2 (en) * 2016-05-11 2020-06-23 Texas Instruments Incorporated Semiconductor die with back-side integrated inductive component
US11133375B2 (en) 2016-05-11 2021-09-28 Texas Instruments Incorporated Semiconductor substrate with integrated inductive component
CN110098739A (zh) * 2019-05-08 2019-08-06 宁波大学 一种基于片上电感器的dc-dc降压转换电路

Also Published As

Publication number Publication date
US10692964B2 (en) 2020-06-23
US20170330930A1 (en) 2017-11-16
US20200321430A1 (en) 2020-10-08
EP3455880A4 (en) 2019-05-15
EP3455880A1 (en) 2019-03-20
CN109155309B (zh) 2023-10-27
US20180323254A1 (en) 2018-11-08
WO2017197173A1 (en) 2017-11-16
US10032850B2 (en) 2018-07-24
US11133375B2 (en) 2021-09-28

Similar Documents

Publication Publication Date Title
CN109155309A (zh) 具有背侧集成式电感组件的半导体裸片
CN103579205B (zh) 集成系统和制作该集成系统的方法
US11984246B2 (en) Vertical inductor for WLCSP
US9269654B2 (en) Semiconductor device and method of manufacture thereof
US10008318B2 (en) System and method for integrated inductor
US8592944B2 (en) Semiconductor electronic device with an integrated device with an integrated galvanic isolator element and related assembly process
KR101581971B1 (ko) 플립 칩 반도체 부품 패키징 방법 및 플립 칩 반도체 부품 패키지
Fischer et al. Unconventional applications of wire bonding create opportunities for microsystem integration
CN101483149B (zh) 一种硅通孔互连结构的制备方法
CN107437453B (zh) 用于在info封装件上的无线充电结构的堆叠的线圈及其形成方法
US20130187255A1 (en) Power inductors in silicon
CN110085523A (zh) 半导体器件以及其制造方法
TW201131592A (en) Inductors and methods for integrated circuits
KR20100115735A (ko) 플립 칩 실장을 이용하는 웨이퍼 레벨 패키징
Wang et al. A novel integrated power inductor in silicon substrate for ultra-compact power supplies
CN103972217A (zh) 集成无源电容扇出型晶圆级封装结构及制作方法
WO2009118694A1 (en) Integrated 3d high density and high quality inductive element
CN101783331A (zh) 系统级封装结构及封装方法
US11908886B2 (en) Power converter embodied in a semiconductor substrate member

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant