CN102087996A - 顶层和次顶层金属均加厚的集成电路制作方法及叠层电感 - Google Patents
顶层和次顶层金属均加厚的集成电路制作方法及叠层电感 Download PDFInfo
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Abstract
本发明公开了顶层和次顶层金属均加厚的集成电路制作方法及叠层电感;该方法包括:制作多层金属,其中顶层和次顶层金属的厚度均大于2.8微米。本发明通过加厚顶层和次顶层金属的厚度,有效降低了顶层和次顶层金属的电阻率,从而提高了片上电感的Q值。
Description
技术领域
本发明涉及微电子领域,具体是一种采用集成电路制作方法及应用其制作的堆叠结构的叠层电感。
背景技术
目前,在集成电路中包含了大量的无源器件,片上电感就是其中十分重要的一种,片上电感是射频CMOS/BiCMOS集成电路的重要元件之一。在通常的无线产品中,电感元件对总的射频性能有很重要的影响。因此对这些电感元件的设计和分析也得到了广泛的研究。电感作为射频电路的核心部件,它通常可以影响到整个电路的整体性能。目前,高品质因数的片上电感广泛应用在压控振荡器,低噪声放大器等射频电路模块中。叠层的片上电感在很大程度减少了芯片面积,降低了生产成本。
上面所述的电感器件的电感品质因数Q值是衡量电感器件的主要参数。其是指电感器在某一频率的交流电压下工作时,所呈现的感抗与其等效损耗电阻之比。电感器的Q值越高,其损耗越小,效率越高。
其计算公式为:
Q表示品质因数,w表示频率,L表示某一频率下的电感值,Rs表示某一频率下的电阻值。
如图1所示,传统的射频集成电路制作方法一般采用顶层金属加厚(一般厚度大于2.8微米)的做法来降低顶层金属的电阻率。这样利用加厚的顶层金属来制作片上电感,就可以提高片上电感的品质因数Q值。顶层下面几层金属一般都采用薄金属(一般厚度小于1um)方法。和顶层的厚金属相比,下面几层薄金属的电阻率更高。射频集成电路制作方法中,片上电感的制作通常都需要用到至少两层金属,特别是堆叠式的电感,这时次顶层金属相对高的电阻率就成为制约片上电感Q值提高的主要因素。
发明内容
本发明所要解决的技术问题是提供一种顶层和次顶层金属均加厚的集成电路制作方法,其可以在同样面积的条件下,降低次顶层金属的电阻率,进一步提高片上电感的Q值。
为解决以上技术问题,本发明提供了一种顶层和次顶层金属均加厚的集成电路制作方法;其特征在于,包括:制作多层金属,其中顶层和次顶层金属的厚度均大于2.8微米。
本发明的有益效果在于:通过加厚顶层和次顶层金属的厚度,有效降低了顶层和次顶层金属的电阻率,从而提高了片上电感的Q值。
本发明还提供了利用上述的顶层和次顶层金属均加厚的集成电路制作方法制作的叠层电感;其为多层结构,包括:上下层金属线圈,上下层金属线圈的厚度均大于2.8微米;所述金属线圈上有电感端口;所述上下层金属线圈通过层间通孔互连。
附图说明
下面结合附图和具体实施方式对本发明作进一步详细说明。
图1是现有叠层电感的剖面示意图;
图2是本发明实施例所述叠层电感的剖面示意图;
图3是本发明实施例所述叠层电感的立体图。
具体实施方式
本发明所述的顶层和次顶层金属均加厚的集成电路制作方法及叠层电感;其为多层结构,包括:上下层金属线圈,上下层金属线圈的厚度均大于2.8微米;所述金属线圈上有电感端口;所述上下层金属线圈通过层间通孔互连。
更详细的,本发明所述的顶层和次顶层金属均加厚的集成电路制作方法制作的叠层电感平面结构(以两层金属、三圈八角形电感为例)见图2,立体结构见图3。从图3的立体图中可以看出,上下两层电感的金属走线厚度一致均大于2.8微米,上下两层金属的宽度相等且位置重合。所述电感从一个电感端口开始,在第一层金属线圈上螺线绕到最里端,后通过层间通孔连接到另一层金属线圈;另一层金属线圈再螺线绕致最外端。
本发明所述结构(见附图2)顶层和次顶层金属均为厚金属(一般大于2.8微米),在不需要增加方法步骤的前提下,降低次顶层金属的电阻率,进一步提高片上电感特别是堆叠式电感的Q值,利用堆叠式电感在同样面积下具有比单层电感更高感值的特性(高两倍多),显著降低射频集成电路的面积。
例如,以两圈叠层电感为例同样尺寸下,本发明所述的低频电感值L=2.3nH,Q=8.6,而对应的传统的只有顶层加厚的射频方法下L=2.3nH,Q=4.8。可以看到两层均加厚的结构显著提高了电感的Q值。
图例中上下层金属宽度和厚度一致,这种结构可以充分利用层间金属之间的互感(每一圈金属在另一层金属层上都有对应的金属),厚度一致(都为厚金属)可以降低下层金属的电阻率,提高电感的品质因数Q,实际制作过程中,可以采用上下金属不等宽的方法。
本发明所述的顶层和次顶层金属均加厚的集成电路制作方法及叠层电感,所述电感可以为单端叠层电感或者差分叠层电感,也可以为其它结构的叠层电感。所述金属线圈可以呈顺时针螺旋也可以为逆时针。金属线圈为八角形或方形或圆形或其他形状。
本发明所述的结构不限于两层电感,其他多层电感也可是适用。本发明优先适用于上层金属线圈为顶层金属,下层金属线圈为次顶层金属的情况,但其他多层的电感的其他金属层也可以适用。
本发明并不限于上文讨论的实施方式。以上对具体实施方式的描述旨在于为了描述和说明本发明涉及的技术方案。基于本发明启示的显而易见的变换或替代也应当被认为落入本发明的保护范围。以上的具体实施方式用来揭示本发明的最佳实施结构,以使得本领域的普通技术人员能够应用本发明的多种实施方式以及多种替代方式来达到本发明的目的。
Claims (7)
1.一种顶层和次顶层金属均加厚的集成电路制作方法;其特征在于,包括:制作多层金属,其中顶层和次顶层金属的厚度均大于2.8微米。
2.利用如权利要求1所述的顶层和次顶层金属均加厚的集成电路制作方法制作的叠层电感;其特征在于,其为多层结构,包括:
上下层金属线圈,上下层金属线圈的厚度均大于2.8微米;
所述金属线圈上有电感端口;
所述上下层金属线圈通过层间通孔互连。
3.如权利要求2所述的顶层和次顶层金属均加厚的集成电路制作方法制作的叠层电感;其特征在于,所述电感从一个电感端口开始,在第一层金属线圈上螺线绕到最里端,后通过层间通孔连接到另一层金属线圈;另一层金属线圈再螺线绕致最外端。
4.如权利要求2所述的顶层和次顶层金属均加厚的集成电路制作方法制作的叠层电感,其特征在于,所述上下层金属线圈的线宽相等或者不相等。
5.如权利要求2所述的顶层和次顶层金属均加厚的集成电路制作方法制作的叠层电感,其特征在于,所述金属线圈为上下两层。
6.如权利要求2所述的顶层和次顶层金属均加厚的集成电路制作方法制作的叠层电感,其特征在于,所述金属线圈为八角形或方形或圆形。
7.如权利要求2所述的顶层和次顶层金属均加厚的集成电路制作方法制作的叠层电感,其特征在于,所述金属线圈呈顺时针螺旋或逆时针旋转。
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CN2009102019088A CN102087996A (zh) | 2009-12-08 | 2009-12-08 | 顶层和次顶层金属均加厚的集成电路制作方法及叠层电感 |
US12/960,065 US20110133876A1 (en) | 2009-12-08 | 2010-12-03 | Manufacture method for IC process with TOP and TOP-1 metal layers thickened and stacked inductor manufactured by this method |
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WO2020098185A1 (zh) * | 2018-11-16 | 2020-05-22 | 安徽安努奇科技有限公司 | 频分器 |
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CN104347586B (zh) * | 2014-09-15 | 2017-06-06 | 武汉新芯集成电路制造有限公司 | 集成电感电容的电路结构 |
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US20050190035A1 (en) * | 2004-02-27 | 2005-09-01 | Wang Albert Z. | Compact inductor with stacked via magnetic cores for integrated circuits |
CN1812020A (zh) * | 2006-02-16 | 2006-08-02 | 上海交通大学 | 基于非晶FeCuNbCrSiB磁性薄膜的螺线管微电感器件的制作方法 |
CN1889265A (zh) * | 2006-07-20 | 2007-01-03 | 上海交通大学 | 硅基多层螺旋差分电感 |
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US7068138B2 (en) * | 2004-01-29 | 2006-06-27 | International Business Machines Corporation | High Q factor integrated circuit inductor |
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US20050190035A1 (en) * | 2004-02-27 | 2005-09-01 | Wang Albert Z. | Compact inductor with stacked via magnetic cores for integrated circuits |
CN1812020A (zh) * | 2006-02-16 | 2006-08-02 | 上海交通大学 | 基于非晶FeCuNbCrSiB磁性薄膜的螺线管微电感器件的制作方法 |
CN1889265A (zh) * | 2006-07-20 | 2007-01-03 | 上海交通大学 | 硅基多层螺旋差分电感 |
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WO2020098185A1 (zh) * | 2018-11-16 | 2020-05-22 | 安徽安努奇科技有限公司 | 频分器 |
US11190160B2 (en) | 2018-11-16 | 2021-11-30 | Anhui Anuki Technologies Co., Ltd. | Frequency multiplexer |
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