TWI351747B - High q factor integrated circuit inductor - Google Patents

High q factor integrated circuit inductor Download PDF

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Publication number
TWI351747B
TWI351747B TW094100050A TW94100050A TWI351747B TW I351747 B TWI351747 B TW I351747B TW 094100050 A TW094100050 A TW 094100050A TW 94100050 A TW94100050 A TW 94100050A TW I351747 B TWI351747 B TW I351747B
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Taiwan
Prior art keywords
layer
forming
trench
dielectric layer
pad
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TW094100050A
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English (en)
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TW200537671A (en
Inventor
Daniel C Edelstein
Panayotis C Andricacos
John M Cotte
Hariklia Deligianni
John H Magerlein
Kevin S Petrarca
Kenneth J Stein
Richard P Volant
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Ibm
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Publication of TW200537671A publication Critical patent/TW200537671A/zh
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Publication of TWI351747B publication Critical patent/TWI351747B/zh

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Description

九、發明說明： 【發明所屬之技術領域】 ^^明係，於積體電路’特別是，有關值 ❹結構、製料Q值魏器結構3 方法及將问Q值之電感盗結構整合至積體電路製程的方 法0 【先前技術】 許夕用於射頻(RF)應用上的積體電路都會使用電 器。電感器通常在積體電路晶片的表面上或其附近，以相 對較厚的金屬製成。當積體電路操作的jyp頻率增加時， 除非電感器的Q值也增加，否則功率消耗將會^加;電 感器的Q值可定義為Q=Es/H ’其中Es是儲存於電感器 之反應部分的總能量，E1是損失於電感器之反應部&的 總能量。電感器的Q值亦可表示為q=W0L/R，其中w0 疋共振頻率，L疋電感值，R是電感器的電阻。第二等式 的含義為：Q會隨著R減少而增加。 使用高導電率金屬、寬金屬線或厚金屬線來製造電感 器可以降低電感器的電阻。然而’使用寬金屬線的電感器 卻會佔用大量的積體電路晶片表面，且通常也會大幅限制 積體電路用以配置電感器的合適區域。尤其在使用高導電 率金屬以及在後續整合高導電率、厚金屬電感器和積體電 路的互連層(interconnection)時’厚金屬電感器的製造很 有問題。因此，需要以高導電率金屬形成高Q值 '厚金 屬電感器，以及用以形成積體電路晶片之電感器的互連層 4IBM04153TW.doc 7 製造技術的方法與整合方案。 【發明内容】 幻的第一方面為形成電感器的方法，此方法按所 面二⑻提供—半導體基板；（b)在^t基板的一頂 Χϊί 電屬；(c)在此介電層中形成—下方溝渠；(d) 面上形成一阻抗層；(e)在此阻抗層中 ^成-上方絲’此±謂渠和τ方溝騎齊此上方溝 j「底騎下謂渠觸啟；及_—導體完全填充下 方溝渠及至少部分填充上方賴則彡成電感器。 本發明的第一方面為形成一電感器的方法，此方法按 所列順序包含：（a)提供一半導體基板；（b)在此基板的一 ^面上形成一介電層；（C)在此介電層中形成一下方溝 渠；（d)在此下方溝渠中及介電層之一頂面之上形成一共 形導電襯塾(conformal conductive liner) ; (e)在此導電襯塾 之上形成一共形銅(Cu)晶種層(seed layer) ; (f)在基板上形 成一阻抗層；（g)在此阻抗層中形成一上方溝渠，此上^ 溝渠和下方溝渠對齊’此上方溝渠的一底部對下方溝渠為 開啟·’ (h)電鑛(electroplate)Cu以完全填充下方溝渠及至少 部分填充上方溝渠以形成電感器；⑴移除阻抗層；①在所 有暴露的Cu表面之上，選擇性地形成—導電保護層 (conductive passivation layer);及(k)自導電襯塾覆蓋介電 層的表面之區域，選擇性地移除該Cu晶種層，以及自介 電層的表面移除導電襯墊。 本發明的第三方面為一半導體結構，該結構包含：— 4IBM04153TW.doc 8 及上述的導電保護層125。 圖5E>中’移除所有暴露的襯墊265。在襯墊265為 TaN/Ta及第二導電保護層295為Au的例子中，可以使用 基於氟的RIE。 Q 5F中塗上一毯狀有機保護層300，並以微影蚀 刻的方式將其圖案化，以在！/〇端墊115之上露出一接觸 墊305。在一例子中，毯狀有機保護層3〇〇為聚醯亞胺 (polyimide)。聚醯亞胺層通常藉由以下方式提供：以一聚 醯亞胺前，物質(precursor)覆蓋後，再利用加熱將前驅物 質轉換為熟化的(cured)聚醯亞胺。市場上可購得的聚醯亞 胺前驅物質(聚醯胺酸）或由杜邦(德拉威州威明頓)所製 ，的各種的聚醯亞胺前驅物質，以商名rPyralin」皆可購 得。這些聚醯亞胺前驅物質有許多等級，其商名包含： PI-2555、PI2545、PI-2560、PI-5878、PIH-61454、及 PI-2540 皆可購得。部分係為 pyromdletic dianhydridewydianliiie (PMA-ODA)聚醯亞胺前驅物質。熟化的聚醯亞胺層約〇 4 至5微米厚。接觸墊305可用作線路連接墊。在線路接合 中，以超音波的方式將鋁(Α1)或Au線路焊接或接合至接 觸墊。在此總結本發明第一實施例的製造。 圖5G係用以描述在本發明苐二實施例中，圖5A至 5F所描述的製造步驟之後續步驟的部分橫截面圖。圖5G 截取自圖2的直線S2-S2。圖5G中，形成plm層130 以電性地接觸凸起接觸墊305，並在PLM層130上形成 焊球135。利用一穿通遮罩電鍍C4製程(through mask 4IBM04153TW.doc 17

Claims (1)

  1. 案號：94100050 100年6月16曰修正-替換頁 十、申請專利範圍： 1·一種形成一電感器(inductor)的方法，該方法按所列順序包 含： ⑻提供一半導體基板(substrate); (b) 在該半導體基板的一頂面上形成一介電層(dielectric layer)； (c) 在該介電層中形成一下方溝渠(1〇wertrench); (d) 在該介電層的一頂面上形成一阻抗層(resistlayer); (e) 在該阻抗層中形成一上方溝渠(Upper壮邱也），該上方溝 渠和該下方溝渠對齊，該上方溝渠的一底部對該下方 溝渠是開啟；及 (f) 以一導體(conductor)完全填充該下方溝渠及至少部分 填充該上方溝渠以形成該電感器。 2. 如請求項1所述之該方法，更包含： 在該介電層中形成一介層窗(via)，至該半導體基板上之 一 I/O 端墊(terminal pad)。 3. 如請求項2所述之該方法，更包含形成一線路連接墊 (wirebondpad)，透過該介層窗而電性接觸該1/〇端塾。 4. 如請求項2所述之該方法，更包含形成一焊球連接(s〇lder ball connection) ’透過該介層窗而接觸該i/o端塾。 5. 如請求項4所述之該方法，其中該形成該焊球連接包含電 鑛(electroplate)—個或更多金屬在該1/〇端墊之上。 4 旧 M04153TW.doc 23 1351747 案號：94100050 100年6月16曰修正·替換頁 6’如凊求項1所述之該方法，其中· 启驟(C)包含在該介電層中形成一介層窗，該介層窗的-_ ^該半導體基板中一 I/O端墊為開啟； ^驟⑷包含在該阻抗層中形成—溝渠，該溝渠和該介層 =切及該阻抗層中之該溝渠的一底部對該介層窗為開 ^驟(〇包含以該導體完全填充該介層窗及至少部分填 兄I溝渠，以形成一凸起(raised)接觸墊(contact pad)。、 7. =請求項6所述之該方法，更包含形成一焊球連接 該凸起接觸墊。 8. 如啼求項7所述之該方法，其中該形成該焊球連接包 板對齊的一遮罩—蒸鍵―- 9. 如請求項7所述之該方法，其中該形成該焊球連接 鍍一個或更多金屬在該I/O端塾之上。 10. 如請求項1所述之該方法，其甲該下方溝渠形成 層的一預定距離。 ° 11·如請求項ίο所述之該方法，其中： 步驟⑹包含在該半導體基板中形成介層窗，至下穿連接 線路(underpass connection wires)，該介層窗形成於該 渠的一底面上；以及 、以卜万溝 步驟(0包含以該導體完全填充該介層窗。 4 旧 M04153TW.doc 24 1351747 案號：94100050 100年6月16曰修正·替換頁 12. 如請求項1所述之該方法，更包含： (g)移除該阻抗層及在該電感器之上形成一導電保護層 (conductive passivation layer)。 13. 如请求項1所述之該方法，其中該上方及下方溝渠係為螺 旋形(spiral)溝渠。 14. 如請求項1所述之該方法，其中該導體包含銅(Cu)或一氮 化钽/鈕(TaN/Ta)襯墊(liner)及一 Cu核心。 15. —種形成一電感器的方法，該方法按所列順序包含： (a) 提供一半導體基板； (b) 在該半導體基板的一頂面上形成一介電層； (c) 在該介電層中形成一下方溝渠； (d) 在該下方溝渠中及該介電層之一頂面之上形成一共 形(conformal)之導電襯墊； (e) 在該導電襯墊之上形成一共形之Cu晶種層(seed layer)； (f) 在該半導體基板上形成一阻抗層； (g) 在該阻抗層中形成一上方溝渠Γ該上方溝渠和該下方 溝渠對齊，該上方溝渠的一底部對該下方溝渠為開 啟； (h) 電鑛Cu以完全填充該下方溝渠及至少部分填充該上 方溝渠，以形成該電感器； (0 移除該阻抗層； (j)在所有暴露的Cu表面之上，選擇性地形成一導電保 4IBM04153TW.doc 25 1351747 案號：94100050 100年6月16曰修正-替換頁 護層；及 (k)自該導電襯墊覆蓋該介電層之該表面的區域，選擇性 地移除該CU晶種層，以及自該介電層的該表面，移 除該導電襯整。 16. 如請求項15所述之該方法： 更包含在步驟(e)後，自該導電襯墊覆蓋該介電層之該頂 面的區域’移除該Cu晶種層，以及在該下方溝渠之側壁及 一底面上，留下該Cu晶種層；以及 其中步驟(k)不包含自該導電襯墊覆蓋該介電層之該頂 面的該區域，移除該Cu晶種層。 17. 如請求項15所述之該方法，更包含： 在該介電層中形成一介層窗，至該半導體基板上之一 I/O端墊。 18. 如請求項17所述之該方法，更包含： 在該介電層中形成一介層窗，該介層窗和該1/〇端墊對 齊； 在該半導體基板之上形成一聚醯亞胺層(p〇lyimide layer) ’該聚酿亞胺層和該介電層中的該介層窗對齊；以及 在該聚醯亞胺層中形成一介層窗，該聚醯亞胺層中的該 介層窗和該I/O端墊對齊且定義一線路連接墊。 19. 如請求項18所述之該方法，更包含在該聚醯亞胺層及該介 電層中，形成一焊球連接，透過該介層窗接觸該J/Q端墊。 4IBM04153TW.doc 26 案號：94100050 100年6月16日修正-替換頁 20. 如凊求項19所叙財法，其巾娜絲焊輕接包含蒸 鍍或濺鍍(sputter)-墊限制冶金層㈣㈣㈣⑽她奶 layer)及一晶種層，及電鍍一 pb層一 pb/Sn合金層。 21. 如請求項15所述之該方法，其中： 步驟(c)包含在該介電層中形成一介層窗，至該基板之 一 I/O端塾； 步驟(d)包含在s玄介電層的該介層窗中，形成一共形導 電襯塾； 八 步驟(g)包含在該阻抗層中形成一溝渠，該溝渠和該介 電層中的該介層窗對齊，該溝渠的一底部對該介電層中的該 介層窗為開啟；及 ° 步驟(h)包含電鍍Cu以完全填充該介電層中的該介層 窗及至少部分填充該溝渠，以形成一凸起接觸墊。 曰 22. 如請求項21所述之該方法，更包含形成一焊球連接，接觸 該凸起接觸塾的。 23. 如請求項22所述之該方法，其中該形成該焊球連接包含： 透過和該半導體基板對齊的一遮罩，蒸鍍或賤鑛—塾限制冶 金層及一 Pb層或一 Pb/Sn合金層。 口 24. 如請求項22所述之該方法，其中該形成該焊球連接包含： 濺鍍一墊限制冶金層及一晶種層，及電鍍一 Pb層—Pb/Sn 合金層。 25. 如請求項15所述之該方法，其中該下方溝渠形成到該介電 4IBM04153TW.doc 27 1351747 % 案號：94100050 100年6月16日修正_替換頁 參 層的一預定距離。 26.如請求項25所述之該方法，其中： i 步驟(c)包含在該半導體基板中形成介層窗，至下穿連接 線路’該介層窗形成於該下方溝渠的一底面中；以及 步驟(h)包含電鍍（^ ’以完全填充在該下方溝渠之該底 面中的該介層窗。 27^如％求項I5所述之該方法，其巾該導電保護層包含一錄 例)層或在一 Ni層之上的一金(Au)層。 28.如二青求項15戶斤叙該方法，其中該上方及下方溝渠為螺旋 形溝渠’且該電感器為一螺旋形電感器。 之該方法，其中該介電層包含—上聊4 面’MSi02層接觸-下方_4層 的頂面。 所述之該方法，其中步驟(h)電鍵Cu到至少 4IBM04153TW.doc 28
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