WO2020215225A1 - 电路板及其制作方法 - Google Patents

电路板及其制作方法 Download PDF

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Publication number
WO2020215225A1
WO2020215225A1 PCT/CN2019/083965 CN2019083965W WO2020215225A1 WO 2020215225 A1 WO2020215225 A1 WO 2020215225A1 CN 2019083965 W CN2019083965 W CN 2019083965W WO 2020215225 A1 WO2020215225 A1 WO 2020215225A1
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WIPO (PCT)
Prior art keywords
substrate
circuit board
hole
conductive
groove
Prior art date
Application number
PCT/CN2019/083965
Other languages
English (en)
French (fr)
Inventor
何明展
胡先钦
沈芾云
徐筱婷
魏永超
Original Assignee
庆鼎精密电子（淮安）有限公司
鹏鼎控股(深圳)股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 庆鼎精密电子（淮安）有限公司, 鹏鼎控股(深圳)股份有限公司 filed Critical 庆鼎精密电子（淮安）有限公司
Priority to CN201980006124.1A priority Critical patent/CN112205082B/zh
Priority to US16/767,870 priority patent/US11212922B2/en
Priority to PCT/CN2019/083965 priority patent/WO2020215225A1/zh
Publication of WO2020215225A1 publication Critical patent/WO2020215225A1/zh
Priority to US17/527,320 priority patent/US11665833B2/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113—Via provided in pad; Pad over filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/04—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/107—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H05K3/4617—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar single-sided circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0338—Layered conductor, e.g. layered metal substrate, layered finish layer, layered thin film adhesion layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0347—Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0388—Other aspects of conductors
    • H05K2201/0394—Conductor crossing over a hole in the substrate or a gap between two separate substrate parts
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09036—Recesses or grooves in insulating substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09563—Metal filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H05K3/0035—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material of blind holes, i.e. having a metal layer at the bottom
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates

Definitions

  • the invention relates to a circuit board and a manufacturing method thereof.
  • the subtractive method and the improved semi-additive method are less capable of making fine circuit layers, and the cost of the semi-additive method is higher.
  • a method for manufacturing a circuit board includes the following steps:
  • a groove is formed on the peelable film and the substrate by laser ablation.
  • the groove includes a concave portion located at the conductive hole, and the hole diameter of the concave portion is larger than that of the conductive hole.
  • the aperture of the hole exposes part of the conductor;
  • a seed layer is formed on the side wall and bottom wall of the groove
  • a circuit layer is fabricated in the groove to obtain a circuit board unit, the circuit layer includes a connection pad located in the recessed portion, and the shape of the connection pad is a conductive bump, which surrounds and electrically Connect the conductor;
  • step (1) Repeat step (1) to step (8) at least once;
  • step (5) the side walls and the bottom wall of the groove are processed by a plasma surface treatment machine.
  • the seed layer is formed by chemical vapor deposition or physical vapor deposition.
  • the method further includes the step of forming a gold layer on the surface of the circuit layer.
  • step (1) one side of the substrate is connected to the carrier through a separable membrane.
  • a circuit board includes at least two stacked circuit board units.
  • Each of the circuit board units includes a substrate and a circuit layer.
  • the substrate is provided with a conductive hole through which a conductive body is provided.
  • a groove is provided on one side of the substrate, the groove includes a concave portion located at the conductive hole, and the hole diameter of the concave portion is larger than the hole diameter of the conductive hole to expose part of the conductor,
  • the circuit layer includes a connecting pad located in the recessed portion, and the connecting pad is in the shape of a conductive bump, which surrounds and electrically connects the conductor.
  • the circuit layer is located in the groove, and the conductive hole is electrically connected to the circuit layers of two adjacent circuit board units.
  • the surface of the circuit layer is provided with a gold layer.
  • a method for manufacturing a circuit board includes the following steps:
  • a groove is formed on both sides of the two peelable films and the substrate by laser ablation.
  • the groove includes a concave portion located at the conductive hole, and the hole diameter of the concave portion is larger than that of the conductive hole.
  • the aperture of the conductive hole exposes part of the conductor;
  • a circuit layer is respectively made in the two grooves to obtain a circuit board, the circuit layer includes a connection pad located in the recess, and the shape of the connection pad is a conductive protrusion, which surrounds and is electrically connected The conductor.
  • a circuit board includes a substrate and two circuit layers.
  • the substrate is provided with a conductive hole through which a conductor is provided. Both sides of the substrate are respectively provided with grooves.
  • Each circuit layer Are respectively provided in a corresponding one of the grooves, the grooves include a recessed portion, the recessed portion is located at the conductive hole, and the hole diameter of the recessed portion is larger than the hole diameter of the conductive hole, part of the conductive body
  • the circuit layer includes a connection pad located in the recessed portion, the connection pad is in the shape of a conductive bump, and the conductive hole electrically connects the two circuit layers.
  • the circuit board manufacturing method of the present invention is simple and has low manufacturing cost.
  • the circuit board of the manufactured circuit board is formed in the groove, and the groove is formed by laser ablation, so the line width of the circuit layer is stable and the accuracy is high.
  • the connection pads of the circuit board of the present invention are conductive bumps to improve the conductive yield.
  • FIG. 1 is a cross-sectional view of a through hole formed on a substrate according to the first embodiment of the present invention.
  • FIG. 2 is a cross-sectional view of the through hole of the structure shown in FIG. 1 being filled with conductors.
  • FIG. 3 is a cross-sectional view of the substrate with the structure shown in FIG. 2 covered with a peelable film.
  • FIG. 4 is a cross-sectional view of the peelable film of the structure shown in FIG. 3 and grooves formed on the cover layer.
  • FIG. 5 is a cross-sectional view of the structure shown in FIG. 4 with the peelable film removed.
  • FIG. 6 is a cross-sectional view of a seed layer formed on the groove of the structure shown in FIG. 5.
  • FIG. 7 is a cross-sectional view of a circuit layer formed in the groove of the structure shown in FIG. 6.
  • FIG. 8 is a cross-sectional view of the structure shown in FIG. 7 with the separable membrane and carrier plate removed.
  • FIG. 9 is a cross-sectional view of a gold layer formed on the circuit layer of the structure shown in FIG. 8.
  • FIG. 10 is a cross-sectional view of the circuit board of Embodiment 1 and Embodiment 3 of the present invention.
  • FIG. 11 is a cross-sectional view of a through hole formed on a substrate according to the second embodiment of the present invention.
  • Fig. 12 is a cross-sectional view of the substrate shown in Fig. 11 after a groove is formed.
  • FIG. 13 is a cross-sectional view of a circuit board according to Embodiment 2 and Embodiment 4 of the present invention.
  • an element when an element is considered to be “connected” to another element, it may be directly connected to another element or a centrally arranged element may exist at the same time.
  • an element When an element is considered to be “disposed on” another element, it can be directly disposed on another element or a centrally disposed element may also exist at the same time.
  • Embodiment 1 of the present invention provides a circuit board manufacturing method, which includes the following steps.
  • a substrate 10 is provided, and holes 11 are formed on the substrate 10.
  • one side of the substrate 10 is connected to a carrier 102 through a separable membrane 101 for ease of processing, but it is not limited to this. In other embodiments, the separable membrane 101 and the carrier may be omitted. ⁇ 102 ⁇ Board 102.
  • the substrate 10 is a low-dielectric resin material, preferably a polyester polymer substrate or a polyether polymer substrate, such as polyether ether ketone (PEEK), liquid crystal polymer (Liquid Crystal Polymer) , LCP) etc.
  • PEEK polyether ether ketone
  • LCP liquid crystal polymer
  • the through hole 11 is formed by laser processing. It is understood that in other embodiments, the through hole 11 may also be formed by mechanical processing.
  • a conductive body 111 is filled into the through hole 11 to form a conductive hole 12.
  • the conductor 111 is a conductive material such as conductive paste.
  • a peelable film 13 is provided to cover one side of the substrate 10.
  • the peelable film 13 covers the side of the substrate 10 away from the carrier 102.
  • the peelable film 13 is a resin material, such as polyimide (PI), polyethylene terephthalate (PET), and polyethylene naphthalate (PEN). )Wait.
  • PI polyimide
  • PET polyethylene terephthalate
  • PEN polyethylene naphthalate
  • a groove 15 is formed on the peelable film 13 and the substrate 10 by laser ablation.
  • the groove 15 includes a recess 151.
  • the concave portion 151 is located at the conductive hole 12, and the hole diameter of the concave portion 151 is larger than the hole diameter of the conductive hole 12 to expose part of the conductive body 111.
  • the groove 15 is formed by laser ablation to accurately control the line width and stability and facilitate impedance control tolerance.
  • an excimer laser is used to finely adjust the opening size of the groove 15.
  • the side walls and bottom walls of the groove 15 are processed by a plasma surface treatment machine to achieve the effects of removing residues formed after laser ablation, improving roughness and activation.
  • sandblasting can also be performed.
  • the peelable film 13 is removed.
  • a seed layer 16 is formed on the sidewall and bottom wall of the groove 15.
  • the seed layer 16 is formed by chemical vapor deposition (Chemical Vapor Deposition, CVD) or physical vapor deposition (Physical Vapor Deposition, PVD).
  • the thickness of the seed layer 16 ranges from 0.08 ⁇ m to 2 ⁇ m.
  • the seed layer 16 can be made of nickel, copper, gold, graphite, titanium, silver and other materials.
  • a circuit layer 20 is formed in the groove 15 to obtain the circuit board unit 100.
  • the circuit layer 20 includes a connection pad 21 formed in the recess 151.
  • the shape of the connection pad 21 is a conductive bump, which surrounds and electrically connects the conductor 111.
  • the circuit layer 20 can be formed by chemical plating, electroplating, sputtering or ion plating. It can be understood that, during electroplating, the wiring layer 20 is connected to the electroplating power source by adding leads.
  • the ninth step referring to FIG. 8, remove the separable membrane 101 and the carrier 102.
  • the ninth step is omitted.
  • a gold layer 22 is formed on the surface of the circuit layer 20.
  • the gold layer 22 is formed by tin (immersion tin). In other embodiments, it may also be silver or other soft metals.
  • the gold layer 22 is used to ensure the reliability of conduction between the multilayer circuit board units 100 in the subsequent steps. It can be understood that in other embodiments, the tenth step may be omitted.
  • Eleventh step repeat the first to tenth steps at least once.
  • circuit board units 100 are pressed together to obtain a circuit board 200.
  • the second embodiment of the present invention provides a circuit board manufacturing method, which includes:
  • a substrate 10 is provided, and holes 11 are formed on the substrate 10.
  • a conductive body 111 is filled into the through hole 11 to form a conductive hole 12.
  • two peelable films 13 are provided to cover the opposite sides of the substrate 10.
  • grooves 15 are formed on both sides of the two peelable films 13 and the substrate 10 by laser ablation.
  • the groove 15 includes a recess 151.
  • the concave portion 151 is located at the conductive hole 12, and the hole diameter of the concave portion 151 is larger than the hole diameter of the conductive hole 12.
  • the peelable film 13 is removed.
  • a seed layer is formed on the side walls and bottom walls of the two grooves 15.
  • a circuit layer 20 is respectively formed in the two grooves 15 to obtain a circuit board 300.
  • Each of the circuit layers 20 includes a connection pad 21 located in the recess 151.
  • the shape of the connecting pad 21 is a conductive bump, and the two circuit layers 20 are electrically connected through the conductor 111.
  • the third embodiment of the present invention provides a circuit board 200.
  • the circuit board 200 includes at least two circuit board units 100 stacked on each other.
  • Each circuit board unit 100 includes a substrate 10 and a circuit layer 20.
  • the substrate 10 is provided with conductive holes 12 therethrough.
  • the conductive hole 12 is provided with a conductive body 111.
  • a groove 15 is provided on one side of the substrate 10.
  • the groove 15 includes a recess 151.
  • the concave portion 151 is located at the conductive hole 12, and the hole diameter of the concave portion 151 is larger than the hole diameter of the conductive hole 12 to form a stepped hole structure, exposing part of the conductor 111.
  • the circuit layer 20 is located in the groove 15.
  • the circuit layer 20 includes a connection pad 21 located in the recess 151.
  • the shape of the connection pad 21 is a conductive bump, and the connection pad 21 surrounds and is electrically connected to the conductor 111.
  • the surface of the circuit layer 20 is provided with a gold layer 22.
  • the gold layer 22 is made of metal such as tin or silver.
  • the fourth embodiment of the present invention provides a circuit board 300.
  • the circuit board 300 includes a substrate 10 and two circuit layers 20 provided on both sides of the substrate 10.
  • the substrate 10 is provided with conductive holes 12 therethrough.
  • the conductive hole 12 is provided with a conductive body 111.
  • the two sides of the substrate 10 are respectively provided with grooves 15.
  • the groove 15 includes a recess 151.
  • the concave portion 151 is located at the conductive hole 12, and the hole diameter of the concave portion 151 is larger than the hole diameter of the conductive hole 12.
  • Each of the circuit layers 20 is respectively arranged in a corresponding one of the grooves 15.
  • Each of the circuit layers 20 includes a connection pad 21 located in the recess 151.
  • the two circuit layers 20 are electrically connected through the conductor 111.
  • the manufacturing method of the circuit board of the present invention is simple and has low manufacturing cost.
  • the circuit board 200/300 of the manufactured circuit board is formed in the groove 15 and the groove 15 is formed by laser ablation, so the line width of the circuit layer 20 is stable. And the accuracy is high.
  • the connection pad 21 of the circuit board 200/300 of the present invention is a conductive bump to improve the conductive yield.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

一种电路板(100、300)及其制作方法，所述方法包括：(1)提供一基板(10)，在基板(10)上形成通孔；(2)向通孔(11)填充导电体(111)形成导电孔(12)；(3)提供可剥离膜(13)，将其覆盖基板(10)；(4)通过激光形成凹槽(15)，凹槽(15)包括凹陷部(151)；(5)对凹槽(15)的槽壁表面处理；(6)去除可剥离膜(13)；(7)形成种子层(16)；(8)制作线路层(20)以得到电路板单元(100)，线路层(20)包括连接垫(21)，连接垫(21)的形状为一导电凸起，其环绕电连接导电体(111)；(9)重复执行步骤(1)至步骤(8)至少一次；及(10)压合电路板单元(100)。

Description

电路板及其制作方法 技术领域
本发明涉及一种电路板及其制作方法。
背景技术
随着信号传递的频率增加及输入/输出接口的增多，对电路板的信号传输损耗及线路层可靠性提出了更高的要求。传统的线路层制作方式中，减成法及改良型半加成法制作精细线路层的能力较差，半加成法的成本较高。
发明内容
鉴于以上内容，有必要提供一种电路板及其制作方法以解决上述问题。
一种电路板制作方法，其包括以下步骤：
(1)提供一基板，在所述基板上开孔以形成通孔；
(2)向所述通孔填充导电体以形成导电孔；
(3)提供一可剥离膜，将其覆盖于所述基板的一侧；
(4)通过激光烧蚀在所述可剥离膜及基板上形成凹槽，所述凹槽包括凹陷部，所述凹陷部位于所述导电孔处，且所述凹陷部的孔径大于所述导电孔的孔径将部分所述导电体露出；
(5)对所述凹槽的侧壁及底壁进行表面处理以提高粗糙度；
(6)去除所述可剥离膜；
(7)在所述凹槽的侧壁及底壁上形成种子层；
(8)在所述凹槽中制作线路层以得到电路板单元，所述线路 层包括位于所述凹陷部中的连接垫，所述连接垫的形狀为一导电凸起，其环绕并电性连接所述导电体；
(9)重复执行步骤(1)至步骤(8)至少一次；及
(10)压合至少两个所述电路板单元。
进一步地，在步骤(5)中，通过等离子表面处理机对所述凹槽的侧壁及底壁进行处理。
进一步地，在步骤(7)中，通过化学气相沉积或物理气相沉积形成所述种子层。
进一步地，在步骤(8)之后及步骤(9)之前，还包括步骤：在所述线路层的表面形成化金层。
进一步地，在步驟(1)中，所述基板的一侧通过可分离膜与载板连接。
一种电路板，包括至少两个叠设的电路板单元，每个所述电路板单元包括基板及线路层，所述基板贯穿设有导电孔，所述导电孔内设有导电体，所述基板的一侧设有凹槽，所述凹槽包括凹陷部，所述凹陷部位于所述导电孔处，且所述凹陷部的孔径大于所述导电孔的孔径将部分所述导电体露出，所述线路层包括位于所述凹陷部中的连接垫，所述连接垫的形状为一导电凸起，其环绕并电性连接所述导电体。所述线路层位于所述凹槽中，所述导电孔电性连接相邻两电路板单元的线路层。
进一步地，所述线路层的表面设有化金层。
一种电路板制作方法，其包括以下步骤：
提供一基板，在所述基板上开孔以形成通孔；
向所述通孔填充导电体以形成导电孔；
提供两可剥离膜，分别覆盖于所述基板的相对两侧；
通过激光烧蚀在两个所述可剥离膜及基板的两侧分别形成凹 槽，所述凹槽包括凹陷部，所述凹陷部位于所述导电孔处，且所述凹陷部的孔径大于所述导电孔的孔径将部分所述导电体露出；
对所述凹槽的侧壁及底壁进行表面处理以提高粗糙度；
去除所述可剥离膜；
在两个所述凹槽的侧壁及底壁上形成种子层；
在两个所述凹槽中分别制作线路层以得到电路板，所述线路层包括位于所述凹陷部中的连接垫，所述连接垫的形状为一导电凸起，其环绕并电性连接所述导电体。
一种电路板，包括基板及两个线路层，所述基板贯穿设有导电孔，所述导电孔内设有导电体，所述基板的两侧分别设有凹槽，每个所述线路层分别设于相应一个所述凹槽中，所述凹槽包括凹陷部，所述凹陷部位于所述导电孔处，且所述凹陷部的孔径大于所述导电孔的孔径将部分所述导电体露出，所述线路层包括位于所述凹陷部中的连接垫，所述连接垫的形状为一导电凸起，所述导电孔电性连接两个所述线路层。本发明的电路板制作方法较为简便，且制作成本低，制得的电路板的线路形成于凹槽中，凹槽通过激光烧蚀形成，因此线路层的线宽稳定，且精度较高。本发明的电路板的连接垫为导电凸起以提高导电良率。
附图说明
图1是本发明实施方式一的基板上形成通孔的剖视图。
图2是图1所示结构的通孔中填充导电体的剖视图。
图3是图2所示结构的基板上覆盖可剥离膜的剖视图。
图4是图3所示结构的可剥离膜及覆盖层上形成凹槽的剖视图。
图5是图4所示结构去除可剥离膜的剖视图。
图6是图5所示结构的凹槽上形成种子层的剖视图。
图7是图6所示结构的凹槽中形成线路层的剖视图。
图8是图7所示结构去除可分离膜与载板的剖视图。
图9是图8所示结构的线路层上形成化金层的剖视图。
图10是本发明实施方式一及实施方式三的电路板的剖视图。
图11是本发明实施方式二的基板上形成通孔的剖视图。
图12是图11所示基板在形成凹槽后的剖视图。
图13是本发明实施方式二及实施方式四的电路板的剖视图。
主要元件符号说明
电路板                          200、300
电路板单元                      100
基板                            10
可分离膜                        101
载板                            102
通孔                            11
导电体                          111
导电孔                          12
可剥离膜                        13
凹槽                            15
凹陷部                          151
种子层                          16
线路层                          20
连接垫                          21
化金层                          22
如下具体实施方式将结合上述附图进一步说明本发明。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
需要说明的是，当一个元件被认为是“连接”另一个元件，它可以是直接连接到另一个元件或者可能同时存在居中设置的元件。当一个元件被认为是“设置在”另一个元件，它可以是直接设置在另一个元件上或者可能同时存在居中设置的元件。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
请参阅图1至图10，本发明实施例一提供一种电路板制作方法，其包括以下步骤。
第一步，请参见图1，提供一基板10，在所述基板10上开孔以形成通孔11。
在本实施方式中，所述基板10的一侧通过可分离膜101与一载板102连接，以便于加工，但不限于此，在其他实施例中，可以省略所述可分离膜101及载板102。
所述基板10为低介电树脂材料，优选为聚酯类高分子基材或聚醚类高分子基材，如聚醚醚酮(Poly Ether Ether Ketone，PEEK)、液晶聚合物(Liquid Crystal Polymer，LCP)等。
在本实施方式中，所述通孔11通过激光加工形成，可以理解，在其他实施例中，所述通孔11还可以通过机械加工形成。
第二步，请参见图2，向所述通孔11填充导电体111以形成导电孔12。
所述导电体111为导电膏等导电材料。
第三步，请参见图3，提供一可剥离膜13，将其覆盖于所述基板10的一侧。
在本实施方式中，所述可剥离膜13覆盖于所述基板10背离所述载板102的一侧。
所述可剥离膜13为树脂材料，如聚酰亚胺(polyimide，PI)、聚对苯二甲酸乙二醇酯(Polyethylene Terephthalate，PET)以及聚萘二甲酸乙二醇酯(Polyethylene Naphthalate，PEN)等。
第四步，请参见图4，通过激光烧蚀在所述可剥离膜13及基板10上形成凹槽15。
其中，所述凹槽15包括凹陷部151。凹陷部151位于导电孔12处，且凹陷部151的孔径大于导电孔12的孔径以将部分导电体111露出。
通过激光烧蚀形成所述凹槽15以精准控制线宽及稳定性并利于阻抗控制公差大小。优选采用准分子激光以精致调节凹槽15的开口大小。
第五步，对所述凹槽15的侧壁及底壁进行表面处理以提高粗糙度。
在本实施方式中，通过等离子表面处理机对凹槽15的侧壁及 底壁进行处理，以达到清除激光烧蚀后形成的残渣、提高粗糙度以及活化的效果。
可以理解，在其他实施例中，还可以进行喷砂处理。
第六步，请参见图5，去除所述可剥离膜13。
第七步，请参见图6，在所述凹槽15的侧壁及底壁上形成种子层16。
在本实施方式中，通过化学气相沉积(Chemical Vapor Deposition，CVD)或物理气相沉积(Physical Vapor Deposition，PVD)形成所述种子层16。所述种子层16的厚度范围为0.08微米至2微米。所述种子层16可以为镍、铜、金、石墨、钛、银等材质。
由于所述凹槽15的侧壁及底壁具有较高的粗糙度，其容易形成种子层16，而其他部位难以形成种子层16。
第八步，请参见图7，在所述凹槽15中制作线路层20以得到电路板单元100。
所述线路层20包括形成于所述凹陷部151中的连接垫21。所述连接垫21的形状为一导电凸起，其环绕并电性连接所述导电体111。
所述线路层20可以通过化镀、电镀、溅镀或离子镀等方式形成。可以理解，在电镀时，通过添加引线的方式，将线路层20与电镀电源连通。
第九步，请参见图8，去除所述可分离膜101与载板102。
可以理解，在其他实施例中，若省略所述可分离膜101及载板102，则省略第九步。
第十步，请参见图9，在所述线路层20的表面形成化金层22。
所述化金层22通过化锡(沉锡)的方式形成，在其他实施方式 中，也可以为化银或其他软金属。所述化金层22用于保障后续步骤中多层电路板单元100之间的导电的可靠性。可以理解，在其他实施例中，可以省略第十步。
第十一步，重复执行第一步至第十步至少一次。
第十二步，请参见图10，将至少两个电路板单元100压合得到电路板200。
请参见图11至图13，本发明实施例二提供一种电路板制作方法，其包括：
第一步，请参见图11，提供一基板10，在所述基板10上开孔以形成通孔11。
第二步，向所述通孔11填充导电体111以形成导电孔12。
第三步，提供两可剥离膜13，将其覆盖于所述基板10的相对两侧。
第四步，请参见图12，通过激光烧蚀在两个所述可剥离膜13及基板10的两侧分别形成凹槽15。
所述凹槽15包括凹陷部151。凹陷部151位于导电孔12处，且凹陷部151的孔径大于导电孔12的孔径。
第五步，对所述凹槽15的侧壁及底壁进行表面处理以提高粗糙度。
第六步，去除所述可剥离膜13。
第七步，在两个所述凹槽15的侧壁及底壁上形成种子层。
第八步，请参见图13，在两个所述凹槽15中分别制作线路层20以得到电路板300。
每个所述线路层20包括位于所述凹陷部151中的连接垫21。所述连接垫21的形状为一导电凸起，两个所述线路层20通过所述导电体111电性连通。
请参阅图10，本发明实施例三提供一种电路板200。所述电路板200包括至少两个叠设的电路板单元100。每个所述电路板单元100包括基板10及线路层20。
所述基板10贯穿设有导电孔12。所述导电孔12内设有导电体111。
所述基板10的一侧设有凹槽15。所述凹槽15包括凹陷部151。凹陷部151位于导电孔12处，且凹陷部151的孔径大于导电孔12的孔径以形成一台阶孔结构，将部分所述导电体111露出。
所述线路层20位于所述凹槽15中。所述线路层20包括位于所述凹陷部151中的连接垫21。所述连接垫21的形状为一导电凸起，所述连接垫21环绕并电性连接所述导电体111。
在本实施例中，所述线路层20的表面设有化金层22。所述化金层22为锡或银等金属。
请参阅图13，本发明实施例四提供一种电路板300。所述电路板300包括基板10及设于所述基板10两侧的两个线路层20。
所述基板10贯穿设有导电孔12。所述导电孔12内设有导电体111。
所述基板10的两侧分别设有凹槽15。所述凹槽15包括凹陷部151。凹陷部151位于导电孔12处，且凹陷部151的孔径大于导电孔12的孔径。
每个所述线路层20分别设于相应一个所述凹槽15中。每个所述线路层20包括位于所述凹陷部151中的连接垫21。两个所述线路层20通过所述导电体111电性连通。
本发明的电路板制作方法较为简便，且制作成本低，制得的电路板200/300的线路形成于凹槽15中，凹槽15通过激光烧蚀形成，因此线路层20的线宽稳定，且精度较高。本发明的电路板200/300 的连接垫21为导电凸起以提高导电良率。
另外，本领域技术人员还可在本发明精神内做其它变化，当然，这些依据本发明精神所做的变化，都应包含在本发明所要求保护的范围。

Claims (9)

  1. 一种电路板制作方法，其包括以下步骤：
    (1)提供一基板，在所述基板上开孔以形成通孔；
    (2)向所述通孔填充导电体以形成导电孔；
    (3)提供一可剥离膜，将其覆盖于所述基板的一侧；
    (4)通过激光烧蚀在所述可剥离膜及基板上形成凹槽，所述凹槽包括凹陷部，所述凹陷部位于所述导电孔处，且所述凹陷部的孔径大于所述导电孔的孔径将部分所述导电体露出；
    (5)对所述凹槽的侧壁及底壁进行表面处理以提高粗糙度；
    (6)去除所述可剥离膜；
    (7)在所述凹槽的侧壁及底壁上形成种子层；
    (8)在所述凹槽中制作线路层以得到电路板单元，所述线路层包括位于所述凹陷部中的连接垫，所述连接垫的形状为一导电凸起，其环绕并电性连接所述导电体；
    (9)重复执行步骤(1)至步骤(8)至少一次；及
    (10)压合至少两个所述电路板单元。
  2. 如权利要求1所述的电路板制作方法，其特征在于：在步骤(5)中，通过等离子表面处理机对所述凹槽的侧壁及底壁进行处理。
  3. 如权利要求1所述的电路板制作方法，其特征在于：在步骤(7)中，通过化学气相沉积或物理气相沉积形成所述种子层。
  4. 如权利要求1所述的电路板制作方法，其特征在于：在步骤(8)之后及步骤(9)之前，还包括步骤：在所述线路层的表面形成化金层。
  5. 如权利要求1所述的电路板制作方法，其特征在于：在步驟(1)中，所述基板的一侧通过可分离膜与载板连接。
  6. 一种电路板，其特征在于：包括至少两个叠设的电路板单元，每个所述电路板单元包括基板及线路层，所述基板贯穿设有导电孔，所述导电孔内设有导电体，所述基板的一侧设有凹槽，所述凹槽包括凹陷部，所述凹陷部位于所述导电孔处，且所述凹陷部的孔径大于所述导电孔的孔径将部分所述导电体露出，所述线路层包括位于所述凹陷部中的连接垫，所述连接垫的形状为一导电凸起，其环绕并电性连接所述导电体。所述线路层位于所述凹槽中，所述导电孔电性连接相邻两电路板单元的线路层。
  7. 如权利要求6所述的电路板，其特征在于：所述线路层的表面设有化金层。
  8. 一种电路板制作方法，其包括以下步骤：
    提供一基板，在所述基板上开孔以形成通孔；
    向所述通孔填充导电体以形成导电孔；
    提供两可剥离膜，分别覆盖于所述基板的相对两侧；
    通过激光烧蚀在两个所述可剥离膜及基板的两侧分别形成凹槽，所述凹槽包括凹陷部，所述凹陷部位于所述导电孔处，且所述凹陷部的孔径大于所述导电孔的孔径将部分所述导电体露出；
    对所述凹槽的侧壁及底壁进行表面处理以提高粗糙度；
    去除所述可剥离膜；
    在两个所述凹槽的侧壁及底壁上形成种子层；
    在两个所述凹槽中分别制作线路层以得到电路板，所述线路层包括位于所述凹陷部中的连接垫，所述连接垫的形状为一导电凸起，其环绕并电性连接所述导电体。
  9. 一种电路板，包括基板及两个线路层，其特征在于：所述基板贯穿设有导电孔，所述导电孔内设有导电体，所述基板的两侧分别设有凹槽，每个所述线路层分别设于相应一个所述凹槽中，所 述凹槽包括凹陷部，所述凹陷部位于所述导电孔处，且所述凹陷部的孔径大于所述导电孔的孔径将部分所述导电体露出，所述线路层包括位于所述凹陷部中的连接垫，所述连接垫的形状为一导电凸起，所述导电孔电性连接两个所述线路层。
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US20210235590A1 (en) 2021-07-29
US11212922B2 (en) 2021-12-28

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