TWI327367B - Semiconductor substrate structure and method for fabricating the same - Google Patents

Description

1327367 IX. Description of the invention: [Technical field to which the invention pertains] Method, particularly semi-conductive The present invention relates to a semiconductor substrate structure and its fabrication

Refers to a structure suitable for a substrate having good electrical properties, heat dissipation and dimensional stability, and a method for fabricating the same. [Prior Art] With the booming development of the electronics industry, electronic products are gradually entering the multi-functional, high-performance R&D trend #, in order to meet the semiconductor package building (integratl〇n) and miniaturization (Miniaturizatl〇n) The package requirements are electrically connected to each other by multiple active and passive components or circuits. The circuit board carrying the semiconductor chip is increased in line density under the same circuit board unit by matching the high circuit density integrated circuit (4)-(rc) requirements. To connect a larger number of electronic components. 15 The through holes in the conventional semiconductor substrate or printed circuit board (pngted: mng board; PWB) are all plugged with resin or green paint, etc., and then the subsequent buildup structure is continued. In the conventional structure, please refer to Figs. 1A & 1B, which are cross-sectional views of a conventional semiconductor substrate structure. As shown in FIG. 1A, the semiconductor substrate has a core plate Ua, a line 2 layer 12, and a plating via hole 13 (Plating Through Hole). The wiring layer 12 is formed on both sides of the surface of the core board a, and the plating vias 13 are formed in the core board 11a to electrically conduct the wiring layers 12 on both sides of the core board 11a. Further, as shown in FIG. 1B, it is a four-layer semiconductor substrate structure having a core board lib' inner layer wiring layer 12a, an outer layer wiring layer 12b, and a first plating via hole.

5 1327367 13a, a second plating via 13b and a conductive via 15. Wherein, the first electrical plating via 13& can conduct the inner wiring layer 12a on both sides of the core board iib, and the second plating via hole complements the outer circuit layer on both sides of the semiconductor substrate

• 12b' and the conductive blind via 15 is used to turn on the inner wiring layer 12a and the outer wiring layer 5b. Here, the electroplated via hole 13 as shown in FIG. 1A or the first electroplated via hole 13a and the second electroplated via hole 13b as shown in FIG. 1B are each an insulating stud 14 plug hole, but filled with an insulating resin. 14 o'clock is the use of screen printing. Plug-in technology, although this technology is more common and convenient, there are still many shortcomings and points.] If its operators need to accumulate considerable operational experience, then H) practice, every - The screen version needs to make different screens for different plug apertures, and the through-hole size is too small to make the resin or green paint unable to be filled, so the production efficiency is poor, and the through-hole size cannot be made too small to cause plugging. Difficult, so the size of the through hole must be large, the substrate wiring density is reduced, and the process and wiring design of the thin circuit cannot be made; in addition, the thermal expansion coefficient of the plug material is not matched with the metal hole conduction] Substrate reliability issues. In addition, there are copper foils (not shown) on both sides of the core board provided by Li, and when the fabrication is completed, the copper box remains on the structure of the semiconductor substrate, and the high temperature is error-free. Because of its poor ductility, it is easy to generate the problem of "village reliability ^: -20 [Invention] In view of this, the present invention provides a semiconductor substrate structure, the structure comprising: a core plate; at least one first conductive pillar, Formed in the 'heart plate' and the first conductive pillar extends at least the -first circuit layer on both sides of the core plate; at least - the second conductive pillar is formed in the core plate: 1327367 and At least the second circuit layer is formed on the core and the surface of the board. According to the above structure, the periphery formed by the bottom of the circuit layer and the core of the first conductive pillar of the present invention includes a first conductive layer. The semiconductor substrate structure according to the present invention described above can be produced, for example, by the following steps, but is not limited thereto. Wood = This 'The present invention also provides a method for fabricating a semiconductor substrate structure, and the steps include: first, providing a core plate. Next, at this core = a plurality of vias are formed. A conductive layer is formed on the surface of the core plate and the inner wall of the through hole. After I1, the first conductive layer 2 is formed on the surface of the core plate and in the through hole. Finally, the first metal layer of the portion of the rice portion and the first conductive layer of the lower layer and the lower layer are formed so that the first metal layer respectively forms at least one first conductive pillar and at least one second conductive pillar in the through holes. And the surface of the core board forms a first-circuit layer and a second circuit layer, wherein the first circuit layer is formed on both sides of the first conductive pillar. 15 The present invention further provides a semiconductor substrate structure of the present invention. The structure includes: a core plate; at least one second conductive pillar formed in the core plate; and at least one The third circuit layer is formed on a portion of the surface of the second conductive pillar and the surface of the core plate. Therefore, in this structure, the best metal ductility can be obtained, and the reliability quality of the fine circuit can be improved. According to the above structure, the periphery formed between the second conductive pillar and the core plate further includes a first conductive layer, and the bottom of the third circuit layer further includes a first conductive layer. Similarly, the semiconductor substrate structure according to the present invention described above can be produced, for example, by the following steps, but not limited thereto. Therefore, the present invention further provides a method of fabricating a semiconductor substrate structure, the method comprising: first, providing a core board. Then at least one through hole is formed in the core plate. Further, a first conductive layer is formed on the surface of the core plate and the inner wall of the through hole. Then, a first metal layer is formed on the surface of the core plate and the first conductive layer in the through hole. Then, the first metal layer and the first conductive layer covering the underlying layer are removed by etching on the surface of the core plate, and the first metal layer in the through hole forms a second conductive pillar. Then, a second conductive layer can be formed on the surface of the core board. A pattern 10 photoresist layer is formed on the second conductive layer, and a plurality of resist layer openings are formed in the resist layer. A second metal layer can then be formed in the opening of the resist layer. Finally, the resist layer and the second conductive layer underlying it are removed, and the second metal layer serves as a third wiring layer. In the above invention, the core board is not limited to any material, and may be, for example, ABF (Ajinomoto Build-up Film), Benzocyclo-buthene (BCB), liquid crystal polymer (Liquid • Crystal Polymer; LCP), Polyimide (PI), Poly(phenylene ether; PPE), Poly(tetra-fluoroethylene), FR4, FR5, Double Photosensitive or non-photosensitive organic resin such as cis-butyl hydrazine/Bismaleimide Triazine (BT), aromatic polyamide (Aramide), or a mixture of epoxy resin and glass fiber group. In the present invention, the core plate may also be a steel foil substrate (CCL) or a circuit board having a multi-layer circuit layer and a surface laminated with a backing steel foil (RCC), wherein -r^ is called 7367 holes. The hole may be in the form of a mechanically drilled or laser drilled first conductive layer and a second conductive layer, the current conducting path required for the main process, the first conductive layer and the second genus, the alloy or the stacked layers Made up of metal, or can be: Can:! =: If it is composed of a metal, an alloy or a stack of several layers of metal, 10 15 20 is composed of tin, nickel, chromium, titanium, copper-chromium alloy and tin-lead alloy. And physical deposition and chemical deposition - cut = ' Preferably, the physical deposition method is the method of money plating and steaming scorpion for sedimentation is non-electrical ore. If the conductive high-spectrum is used as the % electric layer, then it is formed by spraying: ::::=polyacetylene, polyaniline-; outside, medium-T: metal layer is formed by using electric ore. The material which can be used for the first metal layer is preferably a feed metal, a tin-copper alloy, a copper-chromium alloy material, and a copper metal as the first metal layer. In all of the inventions, the first-line layer and the second circuit layer are made of the same material through the first-metal layer. In another structure of the present invention, the third circuit layer, the resistive layer is formed into a second metal layer by an electroplating process, and the third circuit layer of the third circuit layer of the third circuit layer of the 杪? The material is all over the surface:: the surface is formed - the material of the metal layer

9 1327367 The same material. However, the material used in the second metal layer in the present invention may be one of a group consisting of copper, m, n copper-chromium alloy, and tin-alloy. Preferably, copper can be used. Furthermore, in the foregoing, the resist layer material applicable to the resist layer used in the present invention may preferably be = ' and the photosensitive material may be at least one selected from the group consisting of dry film (忉f(四)) and liquid two Further, in the present invention, the formation of the resist layer is not limited, and the substrate can be printed, spin-coated, bonded, or the like in the above-described manner. ίο 15 The package substrate structure of the present invention and In the manufacturing method, the 2-way build-up structure can be formed on the surface of the core board having the first line layer and the second line: layer or can be formed on the surface of the core board having the third line layer. The structure includes a dielectric layer, a build-up wiring layer on at least one of the eight electrical layers, and a plurality of conductive blind vias. &'" Medium, substrate structure: =: τ buildup ·::== part of the board The second circuit layer, or the circuit layer. X, in the foregoing package substrate structure, the surface of the circuit-added structure can be further formed as follows: the second:: grease package substrate structure, and the material of the solder resist layer is Jiake is a semiconductor substrate for sensitization and its manufacturing method. The electricity is not only the production yield of Meisheng, but also reduced to 20 1327367. The conductive pillar formed by the invention can have good electrical properties, and the thermal expansion coefficient and electrical conductivity of the plugged material can be avoided. The problem of mismatched metal in the via hole of the mine can make the process capability and wiring design of the fine line more.

[Embodiment J] The present invention is described by way of a specific embodiment, and is familiar with this. 蓺 又 又 丄 丄 不 不 不 不 不 不 不 不 不 不 不 不 不 不 不 不 = = = = = = = = = = = The present invention may also be practiced or applied by the method of = 10 ==, and the details in the present specification are also based on different points and applications without departing from the modifications and variations of the invention. The drawings in the various embodiments are simplified. However, the figure only shows the components related to the present invention, and the components shown therein are not designed in a continuous manner. The actual number of components in the actual implementation is a two-selective design. Its component layout type is possible. Referring to FIG. 2, which is a cross-sectional view of a semiconductor substrate structure of the present invention, a core board 2, at least a first conductive pillar 24, at least a second conductor 20:=4 21 and at least one Two circuit layers 244. The first conductive pillars 2 41 are shaped in the core plate 21 and the first conductive pillars 241 extend at least the wiring layer 243 to the core to read the two side surfaces. In addition, the third conductive pillar=into the core board 2i' and the second circuit layer (4) is formed on the core board, the first conductive pillar 241 and the extended first-layer layer/secondary conductive pillar 242 thereof The material used for the second wiring layer 244 is the same as the phase 11 1327367, and copper is used in this embodiment. In this embodiment, a copper pig base plate (CPP) is used as the base of the core plate 21, and has a thin metal layer 21a on the surface, that is, a copper foil, and the thickness can be about . In addition, in this embodiment, a first conductive layer 23 may be formed on the bottom of the first circuit layer 243 and the periphery of the first conductive pillar 241 and the core plate 21. Similarly, the first conductive layer 23 is formed simultaneously at the bottom of the second wiring layer 244, the periphery of the second conductive pillar 242 and the core θ core plate 21'. This first conductive layer 23 is mainly used for conducting the current conduction path required for the electroplating process. Therefore, the material that can be used for the first conductive layer 23 is a conductive material such as a copper or conductive germanium molecule. In the present embodiment, the first conductive layer 23 is made of copper. Example 2 The materials used in this example were the same as those of Example 1. This embodiment can fabricate a semiconductor substrate structure as shown in Fig. 2. Please refer to FIG. 3 to FIG. 3E as a cross-sectional view showing the manufacturing process of the semiconductor substrate structure of the present invention. As shown in Fig. 3A, a core plate 21 is provided having a thin metal layer 2 la, such as a copper foil, and having a thickness of about 2 to 12 μm. Then, as shown in Fig. 3, the core board is formed by mechanical drilling or laser to form a plurality of dream through holes 22, but when using the technique of laser drilling, the degumming is required - (De-smea The operation is performed to remove the slag remaining in the through hole 22 due to the drilling. - 2 〇 Then, as shown in FIG. 3C, a first conductive is formed on the surface of the core plate 21 and the inner wall of the through hole 22 by electroless plating. Layer 23, and the first conductive layer 23 is mainly used for performing the current conduction path required for the subsequent plating process. Subsequently, plating is performed on the surface of the core plate 21 and the first conductive layer 23 in the through hole 22. The first metal layer 24 is formed to form a junction 12 丄 327367 as shown in FIG. 3D. The material used for the first metal layer 24 is copper. Finally, as shown in FIG. 3E, the pattern is followed. The first metal layer 24 is subjected to a round-line process by wet rice etching or dry etching to remove a portion of the first metal layer 24, and will also cover the desired metal layer. - the first conductive layer 23 under the metal layer 24 and the thin metal layer 21a are removed and become apparent The core plate 21 is such that the first metal layer 24 is formed in the through hole 22. The first conductive pillar 241 and the at least one second conductive pillar 242 are respectively formed, and a first circuit layer 243 and a surface are formed on the surface of the core board 21 The second circuit layer 44 is formed on the two sides of the first conductive pillar 241. Thus, the semiconductor substrate structure of the present embodiment is obtained. Embodiment 3 The material used in this embodiment can be combined with the embodiment. The material of i is the same. Please refer to FIG. 4, which is a cross-sectional view of the structure of the semiconductor substrate of the present embodiment. As shown in FIG. 4, it includes a core board 21, at least a second conductive pillar 242, and a third 4th layer. 33, wherein the first conductive pillar 242 is formed in the core board 21, and the third circuit layer 33 is formed on a portion of the surface of the second conductive pillar 242 and the surface of the core board 1 where the material used in the second circuit layer 33 is In addition, in the present embodiment, the first conductive layer 23 can be formed in the periphery formed between the second conductive pillar 242 and the core plate 21, and the bottom layer of the third layer 2 is formed on the bottom layer 33. Forming a second conductive layer 31. The material structure of the conductive layer 23 The same is true, and the second conductive layer 31 can be made of copper or a conductive knife, which is copper in this embodiment. In this structure, the semiconductor substrate structure can be made into a finer line to conform to The requirements of various products. Embodiment 4 13 1327367 The material used in this embodiment can be the same as the material of Example 3.

In this embodiment, the front-end process of the manufacturing process can be implemented as the steps of FIGS. 3A to 3D of Embodiment 2, and the next process is different from Embodiment 2, please refer to FIG. 5A to FIG. 5D, which is the present invention. Figure 5 is a cross-sectional view of the fabrication process of the semiconductor substrate structure. After the structure shown in FIG. 3D is obtained, the first metal layer 24 on the surface of the core board 21 and the first conductive layer 23 covering the surface of the core board 21 are completely removed by wet etching or dry etching, and simultaneously The thin metal layer 2la of the surface of the core board 21 is removed. At this time, the first metal layer 24 in the via hole 22 is still formed to be formed by 1 — - the second conductive pillar 242, and the structure as shown in FIG. 5A can be obtained: the surface of the core panel is not completely smooth after being etched, and Has a roughness (not shown). However, this roughness can be utilized to increase the line bonding capability in subsequent processes. As shown in FIG. 5B, the surface of the core board 21 is formed by using no electro-electricity 19 15 - the second conductive layer 31, and the material used for the second conductive layer 31 may be copper or a conductive polymer for subsequent use. φ motor conduction path control required for electroplating process. The second conductive layer 31 in this embodiment uses copper. Then, as shown in FIG. 5C, a resist layer 32 made of a dry film can be formed on the second conductive layer 31 by a printed '2" method, and the resist layer 32 is formed by a plurality of exposure and development methods. The resist layer opening 32a may be irradiated with ultraviolet light when the exposure is performed, and may be formed by the developer which is generally used in the semiconductor process during development to form a patterned resist layer 32. . " 1327367 Finally, as shown in Fig. 5D, a second metal layer 34 is formed by electrical bonding in the resist opening 32a of Fig. 5C, wherein the second metal layer 34 is made of copper. The resist layer 32 is then removed and the second conductive layer 31 overlying the underlying layer 32 is etched. Therefore, the second metal layer 34 on the surface of the core board 21 and the second conductive layer 31 under it can be used as a third wiring layer 33, and the semiconductor substrate structure of the present invention can be obtained. - Embodiment 5: This embodiment can continue to fabricate another form of > semiconductor substrate structure in accordance with the structure of Embodiment 1. Please refer to Figs. 6A to 6F, which are flowcharts for fabricating the structure of the semi-conductor substrate of this embodiment. First, as shown in Fig. 6A, a semiconductor substrate structure as shown in Fig. 2 is provided. The semiconductor substrate structure is used as a core substrate 20a, and a dielectric layer 41 is laminated on both sides of the surface of the core substrate 20a. The material of the dielectric layer 41 can be, for example, ABF (Ajinomoto Build-up Film), Benzocyclobutene (BCB), Liquid Crystal Polymer (Liquid Crystal).

Polymer ; LCP), Polyimide (PI), Poly(phenylene ether; PPE), Polytetrafluoroethylene (卩〇1丫(^1^&-. fluoroethylene); PTFE) , FR4, FR5, Bismuthimide Triazine (BT), Aromatic Nylon (Aramide)-20, etc., or may be mixed with epoxy resin and glass. A group of materials such as fibers. In the present embodiment, ABF is used as the dielectric layer 41. Next, as shown in FIG. 6B, a blind hole 41a is formed in the dielectric layer 41 by laser drilling, and a 15 1327367 core substrate 2A is formed by mechanical drilling or laser drilling. The through hole 41b of the dielectric layer 41 on both sides of the surface. Then, as shown in Fig. 6C, a third conductive layer 42 is formed on the surface of the dielectric layer 41, the blind via 41a, and the inner wall of the via 41b in an electroless manner. The material used for the third conductive layer 42 may be copper metal. The function 5 of the third conductive layer 42 is mainly for the current conduction path required for the subsequent plating process. Further, as shown in Fig. 6D, a resist layer 43 is formed on the surface of the third conductive layer 42 in a printed manner, and the material thereof may be a dry film. The resist layer 43 is formed by a plurality of barrier openings 43a by exposure and development, and the blind vias 4 and 10 vias 41b are exposed. Finally, as shown in Fig. 6E, an electroplated metal layer is formed by electroplating in the resist opening 43a, the blind via 4 la and the via 41b in Fig. 6D. The material used for the plated metal layer 44 is copper metal. Thereafter, the resist layer 43 and its covered second conductive layer 42 are removed. Therefore, the formed plating metal layer 44 is used as the build-up wiring layer 441, the conductive blind vias 442, and the third conductive pillars 443. The t-conductive aperture 442 and the build-up wiring layer 441 are part of the line build-up structure 45. The conductive via 442 is used to electrically conduct the first circuit layer 243 and the second circuit layer 244 of the core substrate 2A and the build-up circuit layer 44 of the line build-up structure 45. The third conductive pillar 443 is further electrically conductively connected to the build-up wiring layer 441 of the other side surface of the core-20 core substrate 20a and a portion of the second wiring layer 244. Further, after completing the aforementioned line build-up structure 45 As shown by the circle, a solder resist layer 46 is formed on the surface of the line build-up structure 45 to protect the line build-up structure 45'. The material of the solder resist layer 46 is photosensitive ^27367 tree month Hey. The anti-caries layer 46 is formed by a plurality of openings 461' by exposure and development. These openings 461 expose the build-up wiring layer 441 to be electrically connected to the external electronic components as the electrical connection 塾 444'. Therefore, in the present embodiment, the semiconductor substrate structure of the embodiment is used as the core substrate 2A, and the surface of the core substrate 20a is formed with a line build-up structure 45' as a semiconductor substrate structure of a different form. The embodiment is the same as the embodiment 5, but the difference is that, referring to FIG. 7, the core substrate 20b used in the embodiment is the semiconductor substrate structure in the third embodiment, and the remaining steps are the same as the embodiment 5. the same. Here, the conductive blind vias 442 electrically connect the third wiring layer 33 of the core substrate 2〇b and the buildup wiring layer 441 of the wiring buildup structure 45. The third conductive pillar 443 can be electrically electrically connected to the build-up wiring layer 441 and a portion of the third wiring layer 33 of the other side surface of the core substrate 20b. Further, the structure of the semiconductor substrate of this embodiment is completed. 15 In summary, compared with the conductive layer, metal copper layer and insulating resin included in the conventional electroplated via structure, the thermal expansion coefficient of the plug material and the via hole of the electroplated via hole are generated in the process of filling the insulating resin. Reliability issues with metal mismatch. The present invention utilizes a conductive post instead of a plated via that includes only a conductive layer and metallic copper. In this structure, it can have good electric -20 properties, heat dissipation, avoid the problem that the thermal expansion coefficient of the plug material does not match the metal of the plated via hole, and the process capability design of the fine line can be made. According to the semiconductor substrate structure formed in Embodiment 3 and Embodiment 4 of the present invention, since the thin metal layer is completely removed, the obtained 17 U27367 thin wiring line (ie, the third wiring layer) can be optimally obtained. The malleability, the reliability of the quality. The above-described embodiments are merely examples for convenience of description, and the scope of the present invention is determined by the scope of the claims. [Picture of the diagram] Figure 1Α and 1Β are a well-known and quaint view of the structure. Semiconductor Substrate Junction of U-Electrical Through Hole 10 15 20 FIG. 2 is a cross-sectional view showing the structure of a semiconductor substrate of the preferred embodiment of the present invention. Fig. 3A to Fig. 3 are partial cross-sectional views showing the process of the semi-recording plate of the invention according to the fourth embodiment. 4 is a cross-sectional view showing the structure of a +-conductor substrate according to another preferred embodiment of the present invention. FIG. 5 is a cross-sectional view showing the structure of a +-conductor substrate of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. is a cross-sectional view showing the fabrication process of a semiconductor substrate in accordance with still another preferred embodiment of the present invention. 7 is a cross-sectional view showing a structure of a semiconductor substrate according to still another preferred embodiment of the present invention. 0 12 12a circuit layer inner layer circuit layer [main component symbol description Ua, llb, 21 core plate 13 plating via hole 18 1327367 12b outer layer layer 13a first plating Via 13b second plating via 14 insulating resin 15 conductive hole 20a, 20b core substrate 21 core plate 21a metal thin layer 22 via 23 first conductive layer 24 first metal layer 241 first conductive pillar 242 second conductive pillar 243 First circuit layer 244 second circuit layer 31 second conductive layer 32 resist layer 32a resist layer opening 33 third circuit layer 41 dielectric layer 41a blind hole 41b via hole 42 third conductive layer 43 resist layer 43a resist layer opening 44 plating Metal layer 441 build-up circuit layer 442 conductive blind hole 443 second conductive pillar 45 line build-up structure 46 solder resist layer 444 electrical connection pad 34 second metal layer 19

Claims (1)

X. Patent application scope: L-type semiconductor substrate structure, comprising: - a core board; at least one first conductive layer - the conductive pillar system extends at least two J systems = in the core board, and the at least one v- The circuit layer is on both sides of the core board; 5, _ 7 杈 is formed in the core board; and the second circuit layer is formed on the surface of the core board. The semiconductor substrate structure of claim 11, wherein the layer is formed on the bottom of the first circuit layer and the periphery of the fourth column and the core plate. The semiconductor substrate structure according to claim 1, wherein the β-conductive pillar and the extended wiring layer thereof are formed by an electric clock. 4. The semiconductor substrate structure of claim i, wherein the material used in the second circuit layer is copper, tin, nickel, chromium, titanium, steel-alloy, and tin-nuclear alloy. One of the groups formed. 5. The semiconductor substrate structure of claim 1, wherein the material used in the first conductive pillar and the first wiring layer is copper, tin, nickel, chromium, titanium, copper-chromium alloy, and tin. The semiconductor substrate structure of the first aspect of the invention, wherein the semiconductor substrate structure according to claim 1 further comprises a line build-up structure formed on the first circuit layer and the first - the surface of the core board of the circuit layer. 7. The semiconductor substrate structure of claim 6, wherein 20 132736/ The 10 circuit-added structure includes a "electron increase, a build-up circuit layer on the electrical layer, and a plurality of conductive blind holes. Spoons include L? The semiconductor substrate structure of claim 6 is characterized in that the conductive pillars are connected through the line build-up structure and the core layer is connected to the build-up layer of the line build-up structure and formed on the core plate Part of the second circuit layer. a method for fabricating a semiconductor substrate structure, the method comprising: providing a core plate; forming a plurality of through holes in the core plate; forming a first conductive layer on the surface of the core plate and the inner walls of the through holes; Forming a first metal layer on the surface of the core plate and the first conductive layer in the through holes; and " an electrical layer, at least one stack is placed on the dielectric layer Etching the first metal layer and the first conductive layer under the etched portion, so that the first metal layer respectively forms at least one first conductive pillar and at least one second conductive pillar in the through holes, and the The first circuit layer and the second circuit layer are formed on the surface of the core board, wherein the first circuit layer is formed on both sides of the first conductive pillar. -20. The method of fabricating a semiconductor substrate structure according to claim 9, wherein the through hole is formed by mechanical drilling and laser drilling. 11. The method of fabricating a semiconductor substrate structure according to claim 9, wherein the first conductive layer is formed by physical deposition and chemical deposition. 12. The structure of the semiconductor substrate as described in claim U of the patent application 21 1327367 A method of fabricating, wherein the method of physically depositing is sputtering and vapor deposition. 13. The method of fabricating a semiconductor substrate structure according to claim 5, wherein the method of chemical deposition is electroless plating. The method for producing a semiconductor substrate structure according to claim 9, wherein the first metal layer is formed by electroplating. The method of fabricating a semiconductor substrate structure according to claim 9, wherein the method further comprises forming a line build-up structure on the surface of the core plate having the first circuit layer and the second circuit layer. The method for fabricating a semiconductor substrate structure according to claim 15, wherein the circuit build-up structure comprises a dielectric layer, at least one build-up layer disposed on the dielectric layer, and a plurality of layers Conductive blind holes. The method for fabricating a semiconductor substrate structure according to claim 15, further comprising forming at least one third conductive pillar, which is connected to the 15-way build-up structure of the line and the core plate to electrically conduct the line. The build-up wiring layer of the layer structure and a portion of the second wiring layer formed on the core board. 18— a semiconductor substrate structure comprising: a core plate; at least one second conductive pillar formed in the core plate; and 20 at least one third circuit layer formed on a portion of the second conductive pillar surface And the core board surface. 19. The semiconductor substrate structure of claim 18, further comprising: an electrical layer formed by the H-electrode layer and a periphery formed by the second conductive pillar and the core plate 22 1327367; and a second conductive layer , formed at the bottom of the third circuit layer. According to the semiconductor substrate structure described in claim 18, in the middle, the second conductive pillar is formed by electroplating. 5. The semiconductor substrate structure as claimed in claim 18, wherein the material used in the third circuit layer is copper, tin, nickel, chromium, titanium: • copper-chromium alloy and tin-lead alloy. One of the groups formed. For example, the semiconductor substrate structure described in U.S. Patent Application Serial No. U, the material used for the second conductive column is copper, tin, nickel 'chromium, titanium, 10 copper-chromium alloy and tin-lead alloy. One of the groups formed in the group. 23. The semiconductor substrate structure of claim 18, further comprising a line build-up structure formed on the surface of the core plate having the third circuit layer. The semiconductor substrate structure of claim 23, wherein the circuit build-up structure comprises a dielectric layer, at least one build-up circuit layer stacked on the dielectric layer, and a plurality of Conductive blind holes. [25] The semiconductor substrate structure of claim 24, wherein at least a third conductive pillar extends through the line build-up structure and the core plate electrically conducts a far-line buildup structure. The build-up circuit layer and a portion of the third circuit layer formed on the *2〇 core board. a method for fabricating a semiconductor substrate structure, the method comprising: providing a core plate; forming at least one through hole in the core plate; forming a first conductive layer on the surface of the core plate and the inner wall of the through hole; 23 1327367 Forming a first metal layer on the surface of the core plate and the first conductive layer in the through hole; etching the first metal layer on the surface of the core plate and the first conductive layer underlying the core plate Removing, and the first metal piece 5 in the through hole forms a second conductive pillar; θ forms a second conductive layer on the surface of the core plate; and forms a patterned resist layer on the far second conductive layer, And forming a plurality of barrier openings in the resist layer; 10 15 Forming a second metal layer in the opening of the resist layer; and removing the resist layer and the second conductive layer underlying the second metal layer, and the second metal layer serves as a third circuit layer. The method of fabricating a semiconductor substrate structure according to claim 26, wherein the first conductive layer and the second conductive layer are formed by one of physical deposition and chemical deposition. The method of fabricating a semiconductor substrate structure according to claim 27, wherein the method of physically depositing is sputtering and steaming. 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 3. The semiconductor substrate structure of claim 1 wherein the second conductive pillar and the third wiring layer are formed. 31. The method of claim 30, wherein the semiconductor substrate method of claim 1 is included in the core board having the third circuit layer 24 1327367 Build-line build-up structure. The method of fabricating a semiconductor substrate structure as described in claim 31, wherein the wiring layer structure comprises a dielectric layer, at least placed on the "electric layer; A layered circuit layer and a plurality of conductive blind holes. 33. The method of fabricating a semiconductor substrate structure according to claim 31, further comprising forming at least a third (four) column extending through the line build-up structure and the core plate to electrically conduct the line build-up structure The build-up circuit layer and a portion of the third circuit layer formed on the core board. 25