CN101295698A - Flip-chip substrate structure and production method thereof - Google Patents
Flip-chip substrate structure and production method thereof Download PDFInfo
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- CN101295698A CN101295698A CN 200710100958 CN200710100958A CN101295698A CN 101295698 A CN101295698 A CN 101295698A CN 200710100958 CN200710100958 CN 200710100958 CN 200710100958 A CN200710100958 A CN 200710100958A CN 101295698 A CN101295698 A CN 101295698A
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
The invention discloses a structure of a reversed substrate, which includes a line build-up structure, a first welding resistance layer and a second welding resistance layer; the first welding resistance layer is formed on the first side surface of the line build-up structure and is provided with a portiforium so as to expose the metal layer of the first side surface as a first electrical connection pad; wherein, the aperture of the portiforium of the first welding resistance layer is equal to the outer diameter of the first electrical connection pad; the second welding resistance layer is formed on the second side surface of the line build-up structure and is provided with a portiforium so as to expose the line layer of the second side surface as a second electrical connection pad; wherein, the aperture of the portiforium of the second welding resistance layer is less than the outer diameter of the second electrical connection pad; the invention also discloses a manufacture method based on the structure; the structure reaches the goals of lightness, thinness, shortness and smallness by improving the wiring density of the line. The method can simplify the problems of more layers and complex manufacture process.
Description
Technical field
The present invention relates in particular to a kind of structure that is applicable to no through-hole structure, can improves the flip-chip substrate of line layout density about structure of a kind of flip-chip substrate and preparation method thereof, and the manufacture method that reduces the flip-chip substrate of manufacturing process.
Background technology
Flourish along with electronic industry, electronic product also progresses into multi-functional, high performance R﹠D direction.For satisfying the encapsulation requirement of the high integration of semiconductor package part (Integration) and microminiaturized (Miniaturization), the circuit board that provides most main passive devices and circuit to connect, also develop into multi-layer sheet by lamina gradually, so that under limited space, cooperate integrated circuit (Integrated circuit) demand of high electron density by available wiring area on interlayer interconnection technique (Interlayer connection) the expansion circuit board.
The known semiconductor encapsulating structure is that semiconductor chip is pasted on substrate top surface, carries out routing and engages (wire bonding) or flip-chip bonded (Flip chip) encapsulation.Plant in the back side of substrate again with the tin ball electrically connecting, so, though can reach the purpose of high pin number.But when high frequency more uses or during high speed operation, its usefulness that will produce electrical characteristic because of the lead access path is long can't promote, and limits to some extent.In addition, because of conventional package needs linkage interface repeatedly, relatively increase the complexity of manufacturing process.
In the manufacture method of flip-chip substrate, general support plate way is begun by a core substrate, finishes endothecium structure through manufacturing process such as boring, plating, consent, circuit moulding.Finish the multilayer support plate via increasing a layer processing procedure again, shown in Figure 1A to 1E, make multiple-plate method of additional layers.Shown in Figure 1A, at first, prepare a core substrate 11, this core substrate 11 is by the sandwich layer 111 of a tool predetermined thickness and be formed at these sandwich layer 111 lip-deep circuit layers 112 and constituted.Simultaneously, in this sandwich layer 111, be formed with a plurality of plating vias 113.Electrically connect the circuit layer 112 on these sandwich layer 111 surfaces by this.Shown in Figure 1B, this core substrate 11 is implemented to increase a layer manufacturing process, to lay a dielectric layer 12, offer a plurality of openings 13 that are communicated to this circuit layer 112 on this dielectric layer 12 in these core substrate 11 surfaces.Shown in Fig. 1 C, form a conductive layer 14 in these dielectric layer 12 exposed surfaces in modes such as electroless plating or sputters, and on this conductive layer 14, form a patterning resistance layer 15, so that make this resistance layer 15 be formed with a plurality of openings 150 to expose outside the partially conductive layer 14 of desire formation patterned circuit layer.Shown in Fig. 1 D, utilize plating mode in this resistance layer opening, to be formed with patterned circuit layer 16 and conductive blind hole 13a, and make this circuit layer 16 be seen through this conductive blind hole 13a to be electrically conducted to this circuit layer 112, etching removes this resistance layer 15 and partially conductive layer 14 that resistance layer covered then, to form a circuit layer reinforced structure 10a.Shown in Fig. 1 E, similarly, on this first circuit layer reinforced structure 10a outermost surface, also must use same procedure to repeat to form the second circuit layer reinforced structure 10b, form a multilayer support plate 10 progressively to increase layer.
Yet above-mentioned manufacturing process is begun by a core substrate, finishes endothecium structure through manufacturing process such as boring, plating, consent, circuit moulding.Finish the multilayer support plate via increasing a layer manufacturing process again, this way has wiring density low, and the number of plies is many, and the problem that lead is long and impedance is high is used for high frequency substrate is difficult.Again because of the lamination number is many, its manufacturing step not only flow process complexity, spent manufacturing cost is also higher.
Summary of the invention
In view of above-mentioned known shortcoming, main purpose of the present invention is to provide a kind of structure of flip-chip substrate, so that substrate thickness is reduced, to reach compact function.
For reaching above-mentioned purpose, one of the present invention purpose provides a kind of structure of flip-chip substrate, and it comprises: at least one circuit layer reinforced structure, one first welding resisting layer and one second welding resisting layer.This at least one circuit layer reinforced structure, its first side surface is formed with metal level and the circuit layer reinforced structure is electrically conducted, and second side surface is formed with the line layer of circuit layer reinforced structure.First welding resisting layer is formed at first side surface of circuit layer reinforced structure, first welding resisting layer has a plurality of perforates to manifest the metal level of first side surface, with as first electric connection pad, wherein, the first welding resisting layer perforate aperture equals the external diameter of first electric connection pad.Second welding resisting layer, be formed at second side surface of circuit layer reinforced structure, this second welding resisting layer has a plurality of perforates manifesting the line layer of part second side surface, with as second electric connection pad, wherein, the second welding resisting layer perforate aperture is less than the external diameter of second electric connection pad.
Structure according to the flip-chip substrate of the invention described above comprises a plurality of solder projections again, is formed on first electric connection pad and second electric connection pad.
Structure according to the flip-chip substrate of the invention described above wherein, is formed with metal column earlier on the first above-mentioned electric connection pad and second electric connection pad and forms solder projection again.And the material of this metal column preferably can use one of the group that copper, nickel, chromium, titanium, copper/evanohm and tin/lead alloy form person, and more preferably, spendable material is a copper.
According to the structure of the flip-chip substrate of the invention described above, wherein, be formed with etching stopping layer and metal column earlier on above-mentioned first electric connection pad and second electric connection pad after, form solder projection again.
Structure according to the flip-chip substrate of the invention described above comprises a retaining piece again, its be disposed at this second welding resisting layer around the top, in order to avoid the warpage of this substrate.
According to the structure of the flip-chip substrate of the invention described above, the material that this first welding resisting layer and this second welding resisting layer use is also unrestricted, also can be sensing optical activity material identical or inequality, preferably is photosensitive macromolecular material such as green lacquer.
According to the structure of the flip-chip substrate of the invention described above, this circuit layer reinforced structure has a conductive layer at least, and this conductive layer top is formed with an electroplated metal layer.Wherein, this conductive layer is selected from one of the group that is made up of copper, tin, nickel, chromium, titanium, copper-evanohm and tin-lead alloy person.And this conductive layer with conducting polymer as conductive layer, and this conducting polymer is selected from one of the group that is made up of polyacetylene, polyaniline and organic sulfur polymer person.In addition, this electroplated metal layer is the copper layer.
According to the structure of the flip-chip substrate of the invention described above, wherein, the material of first electric connection pad and second electric connection pad preferably can use copper.In addition, this solder projection is not limit and is used any material, preferably is selected from one of copper, tin, lead, silver, nickel, gold, platinum and the formed group of alloy thereof person.
According to the structure of the flip-chip substrate of the invention described above, wherein, the person of one of group that this etching stopping layer chosen from Fe, nickel, chromium, titanium, aluminium, silver, tin, lead and alloy thereof are formed is if use the material that is difficult for oxidation then preferably to can be gold.
Description of drawings
Figure 1A to 1E is the generalized section of the known flip-chip substrate that stratum nucleare is arranged.
Fig. 2 A to 2Q ' is the generalized section of the flip-chip substrate of a preferred embodiment of the present invention.
Fig. 3 A to 3P ' is the generalized section of the flip-chip substrate of another preferred embodiment of the present invention.
Symbol description among the figure
10 multilayer support plates, 11 core substrates
111 sandwich layers, 112 circuit layers
13 electroplate via 13a blind hole
15 resistance layers, 16 patterned circuit layer
201,301 support plates, 202,302 first welding resisting layers
13,150 openings, 204,304 conductive metal layers
205,305 etching stopping layers, 206,306 metal levels
10a, 10b, 207,307, circuit layer reinforced structure
12,208,308 dielectric layers, 14,209,309 conductive layers
210,310 electroplated metal layers, 212,312 second welding resisting layers
214 ' 314 ' first electric connection pads, 214,314 second electric connection pads
215,215 ', 315,315 ' metal column
216,316 solder projections, 217,317 retaining pieces
203,303 first opening 208a, 308a the 3rd opening
213,313 second openings, 218,318 patterning resistance layers
218a, 318a resistance layer opening 207a, 307a first side surface
207b, 307b second side surface
Embodiment
Below by particular specific embodiment explanation embodiments of the present invention, have the knack of people's formula of this skill and can understand other advantage of the present invention and effect easily by the content that this specification disclosed.The present invention also can be implemented or be used by other different specific embodiment, and the every details in this specification also can be based on different viewpoints and application, carries out various modifications and change under the spirit of the present invention not breaking away from.
Embodiment 1
The generalized section of one of them embodiment of structure of flip-chip substrate of the present invention sees also Fig. 2 A to 2Q ' figure.
At first, shown in Fig. 2 A, one support plate 201 is provided, and this support plate is a sheet metal, the preferable copper that can be, then, shown in Fig. 2 B, 201 apply formation one first welding resisting layer 202 on this support plate, form a plurality of first openings 203 in this first welding resisting layer 202 in the mode of exposing, develop again, shown in Fig. 2 C, and these first welding resisting layer, 202 employed materials can be green lacquer.
Respectively at forming one deck conductive metal layer 204, an etching stopping layer 205 and a metal level 206 with plating or electroless-plating mode in regular turn from lower to upper in these first openings 203 of this first welding resisting layer 202, its expression is as Fig. 2 D～2F, wherein, the material that this conductive metal layer 204 and this metal level 206 use is copper, the person of one of group that the material that this etching stopping layer 205 uses is formed as chosen from Fe, nickel, chromium, titanium, aluminium, silver, tin, lead and alloy thereof.
Then, please refer to Fig. 2 G, form a dielectric layer 208 in this metal level 206 and this first welding resisting layer 202 surfaces, and this dielectric layer 208 is selected from ABF (Ajinomoto Build-up Film), BCB (Benzocyclo-buthene), LCP (Liquid Crystal Polymer), PI (Poly-imide), PPE (Poly (phenylene ether)), PTFE (Poly (tetra-fluoroethylene)), FR4, FR5, BT (Bismaleimide Triazine), aramid fiber sensitization or non-sensitization organic resins such as (Aramide), but or the also group that formed of material such as blending epoxy and glass fibre.Make this dielectric layer 208 form a plurality of the 3rd opening 208a again with Laser drill or exposure, development, wherein, at least one the 3rd opening 208a is corresponding to the position of this metal level 206, only when utilize the technology of Laser drill, need carry out de-smear (De-smear) operation again to remove the glue slag that is residued in because of holing in this dielectric layer opening.For another example shown in Fig. 2 H, surface in this dielectric layer 208 and opening 208a thereof forms one deck conductive layer 209, the current conduction path that this conductive layer 209 is electroplated mainly as aftermentioned, it comprises one of the group that formed in copper, tin, nickel, chromium, titanium, copper-evanohm and tin-lead alloy person, and forms with one of sputter, evaporation, electroless-plating and chemical deposition person.In addition, this conductive layer 209 also can comprise conducting polymer, and it is selected from one of the group that is made up of polyacetylene, polyaniline and organic sulfur polymer person, and forms in modes such as rotary coating, ink jet printing, wire mark or impressions.
Then, shown in Fig. 2 I, form a patterning resistance layer 218 on this conductive layer 209, it makes resistance layer form a plurality of resistance layer opening 218a with exposure, visualization way, and wherein, at least one resistance layer opening 218a corresponds to the position of this metal level 206.For another example shown in Fig. 2 J, electroplate one deck electroplated metal layer 210 in these a plurality of resistance layer opening 218a, these electroplated metal layer 210 the bests can be copper, remove this resistance layer 218 again and remove conductive layer 209 that resistance layer covered and must be just like the circuit layer reinforced structure 207 shown in Fig. 2 K with etching mode.
Please refer to Fig. 2 L, can continue to form circuit layer reinforced structure 207 in these circuit layer reinforced structure 207 tops according to actual needs according to aforesaid mode, again with reference to figure 2M, be covered with one deck second welding resisting layer 212 in these at least one circuit layer reinforced structure 207 tops, the material that this second welding resisting layer 212 uses is green lacquer, and this second welding resisting layer 212 forms a plurality of second openings 213 with exposure, the mode of developing, manifesting the circuit of part circuit layer reinforced structure 207, with as second electric connection pad 214.
Then, shown in Fig. 2 N, remove this support plate 201, this conductive metal layer 204 and shown in Fig. 2 O with etching mode, this etching stopping layer 205 of etching is manifesting metal level 206, with as first electric connection pad 214 '
Shown in Fig. 2 P, directly in the electric connection pad (i.e. first electric connection pad 214 ' and second electric connection pad 214) of these at least one circuit layer reinforced structure 207 both sides, form a solder projection 216 for another example, the generation type of this solder projection 216 can be electroplates or printing.Or shown in Fig. 2 P ', need as manufacturing process, then can form a metal column 215 respectively at electroplating on these second openings 213 of this second welding resisting layer 212 earlier, the material that this metal column 215 uses is copper, and electroplate formation one metal column 215 ' in these metal level 206 belows, this metal column 215 ' employed material is a copper, again respectively at this metal column 215,215 ' goes up formation one solder projection 216, the generation type of this solder projection 216 can be electroplates or printing, and the material that this solder projection 216 uses is for being selected from copper, tin, plumbous, silver, nickel, gold, one of platinum and the formed group of alloy thereof person.
At last, shown in Fig. 2 Q and 2Q ', around this second welding resisting layer 212, go up each formation one retaining piece 217 of fitting, and the warpage (warpage) of this retaining piece 217 in order to avoid this substrate.
In view of the above, the invention provides wherein a kind of can be according to aforementioned but be not limited thereto the structure of the flip-chip substrate of method, shown in Fig. 2 P, it mainly comprises, at least one circuit layer reinforced structure 207, one first welding resisting layer 202 and one second welding resisting layer 212.In circuit layer reinforced structure 207, its first side surface 207a is formed with metal level 206 and is electrically conducted with circuit layer reinforced structure 207, and the second side surface 207b is formed with the line layer (promptly the part by electroplated metal layer 210 is formed) of circuit layer reinforced structure 207.First welding resisting layer 202 is formed at the first side surface 207a of circuit layer reinforced structure 207, first welding resisting layer 202 has the metal level 206 of a plurality of perforates (i.e. first opening 203) to manifest the first side surface 207a, with as first electric connection pad 214 ', wherein, first welding resisting layer, 202 perforate apertures equal the external diameter of first electric connection pad 214 '.Second welding resisting layer 212, be formed at the second side surface 207b of circuit layer reinforced structure 207, this second welding resisting layer 212 has a plurality of perforates (i.e. second opening 213) to manifest the line layer of the part second side surface 207b, with as second electric connection pad 214, wherein, second welding resisting layer, 212 perforate apertures are less than the external diameter of second electric connection pad 214.
Embodiment 2
The generalized section of the structure of flip-chip substrate of the present invention another embodiment wherein sees also Fig. 3 A to 3P ' figure.
At first, as shown in Figure 3A, provide a support plate 301, this support plate is a sheet metal, the preferable copper that can be.Then, shown in Fig. 3 B, 301 are covered with one deck first welding resisting layer 302 on this support plate, form a plurality of first openings 303 in this first welding resisting layer 302 in the mode of exposing, develop again, and shown in Fig. 3 C, and these first welding resisting layer, 302 employed materials can be green lacquer.
Respectively at forming a conductive metal layer 304, an etching stopping layer 305 and a metal level 306 with plating or electroless-plating mode in regular turn from lower to upper in these first openings 303 of this first welding resisting layer 302, its expression is as Fig. 3 D～3F, wherein, the material that this conductive metal layer 304 and this metal level 306 use is all copper, and the material that this etching stopping layer 305 uses is the gold that is difficult for oxidation.
Then, please refer to Fig. 3 G, form a dielectric layer 308 in this metal level 306 and this first welding resisting layer 302 surfaces, this dielectric layer 308 is selected from ABF (Ajinomoto Build-up Film), BCB (Benzocyclo-buthene), LCP (Liquid Crystal Polymer), PI (Poly-imide), PPE (Poly (phenylene ether)), PTFE (Poly (tetra-fluoroethylene)), FR4, FR5, BT (Bismaleimide Triazine), aramid fiber sensitization or non-sensitization organic resins such as (Aramide), but or the also group that formed of material such as blending epoxy and glass fibre.Make this dielectric layer 308 form a plurality of the 3rd opening 308a again with Laser drill or exposure, development, wherein, at least one the 3rd opening 308a is corresponding to the position of this conductive metal layer 304, only when utilize the technology of Laser drill, also need carry out de-smear (De-smear) operation to remove the glue slag that is residued in because of holing in this dielectric layer opening.For another example shown in Fig. 3 H, form a conductive layer 309 in this dielectric layer 308 and opening 308a thereof, the current conduction path that this conductive layer 309 is electroplated mainly as aftermentioned, it comprises one of the group that formed in copper, tin, nickel, chromium, titanium, copper-evanohm and tin-lead alloy person, and forms with one of sputter, evaporation, electroless-plating and chemical deposition person.In addition, this conductive layer 209 also can comprise conducting polymer, and it is selected from one of the group that is made up of polyacetylene, polyaniline and organic sulfur polymer person, and forms in modes such as rotary coating, ink jet printing, wire mark or impressions.
Then, shown in Fig. 3 I, on this conductive layer 309, form a patterning resistance layer 318, it makes resistance layer form a plurality of resistance layer opening 318a with exposure, visualization way, wherein, at least one resistance layer opening 318a corresponds to the position of this metal level 306, for another example shown in Fig. 3 J, electroplate one deck electroplated metal layer 310 in these a plurality of resistance layer opening 318a, these electroplated metal layer 310 the bests can be copper, remove resistance layer 318 again and remove conductive layer 309 that resistance layer covered and must be just like the circuit layer reinforced structure 307 shown in Fig. 3 K with etching mode.
Please refer to Fig. 3 L, can continue to form circuit layer reinforced structure 307 in these circuit layer reinforced structure 307 tops according to actual needs according to aforesaid mode, again with reference to figure 3M, be covered with one deck second welding resisting layer 312 in these at least one circuit layer reinforced structure 307 tops, the material that this second welding resisting layer 312 uses is green lacquer, and this second welding resisting layer 312 forms a plurality of second openings 313 with exposure, the mode of developing, manifesting the circuit of part circuit layer reinforced structure 307, with as second electric connection pad 314.
Then, shown in Fig. 3 N, remove this support plate 301, this conductive metal layer 304, manifesting etching stopping layer 305, with as first electric connection pad 314 ' with etching mode.
Shown in Fig. 3 O, directly go up in the electric connection pad (i.e. first electric connection pad 314 ' and second electric connection pad 314) of circuit layer reinforced structure 307 both sides and form a solder projection 316 for another example, the generation type of this solder projection 316 can be electroplates or printing.Or shown in Fig. 3 O ', need as manufacturing process, forming a metal column 315 respectively at electroplating on these second openings 313 of this second welding resisting layer 312, the material that this metal column 315 uses is copper.Form a metal column 315 ' in these etching stopping layer 305 belows again, and the material of this metal column 315 is a copper, again respectively at these metal columns 315,315 ' goes up formation one solder projection 316, the generation type of this solder projection 316 can be electroplates or printing, and the material that this solder projection 316 uses is for being selected from one of copper, tin, lead, silver, nickel, gold, platinum and the formed group of alloy thereof person.
At last, shown in Fig. 3 P and Fig. 3 P ', around this second welding resisting layer 312, go up each formation one retaining piece 317 of fitting, and this retaining piece 317 is in order to avoid the warpage of this substrate.
In view of the above, the present invention can provide wherein a kind of foundation aforementioned but be not limited thereto the structure of the flip-chip substrate of method, and shown in Fig. 3 O ', it mainly comprises, at least one circuit layer reinforced structure 307, one first welding resisting layer 302 and one second welding resisting layer 312.In circuit layer reinforced structure 307, its first side surface 307a is formed with metal level 306 and is electrically conducted with circuit layer reinforced structure 307, and the second side surface 307b is formed with the line layer (promptly the part by electroplated metal layer 310 is formed) of circuit layer reinforced structure 307.First welding resisting layer 302 is formed at the first side surface 307a of circuit layer reinforced structure 307, first welding resisting layer 302 has the metal level 306 of a plurality of perforates (i.e. first opening 303) to manifest the first side surface 307a, with as first electric connection pad 314 ', wherein, first welding resisting layer, 302 perforate apertures equal the external diameter of first electric connection pad 314 '.Second welding resisting layer 312, be formed at the second side surface 307b of circuit layer reinforced structure 307, this second welding resisting layer 312 has a plurality of perforates (i.e. second opening 313) to manifest the line layer of the part second side surface 307b, with as second electric connection pad 314, wherein, second welding resisting layer, 312 perforate apertures are less than the external diameter of second electric connection pad 314.So after etching stopping layer 305 and metal column 315 ' can being formed with on first electric connection pad 314 ' earlier, form solder projection 316 again.Second electric connection pad 314 then can form metal column 315 earlier, forms solder projection 316 again.
In sum, the invention solves in the support plate that generally has core substrate has wiring density low, and the number of plies is too much, problems such as lead length and impedance height, the no through-hole structure of this kind has improved line layout density, reduce manufacturing process, support plate thickness is reduced, and reach compact purpose.
The foregoing description is only given an example for convenience of description, and the interest field that the present invention advocated should be as the criterion so that claim is described certainly, but not only limits to the foregoing description.
Claims (9)
1. the structure of a flip-chip substrate, it comprises:
At least one circuit layer reinforced structure, its first side surface is formed with metal level and the circuit layer reinforced structure is electrically conducted, and second side surface is formed with the line layer of circuit layer reinforced structure;
First welding resisting layer, be formed at first side surface of this circuit layer reinforced structure, this first welding resisting layer has a plurality of perforates manifesting the metal level of first side surface, with as first electric connection pad, wherein, the first welding resisting layer perforate aperture equals the external diameter of first electric connection pad; And
Second welding resisting layer, be formed at second side surface of this circuit layer reinforced structure, this second welding resisting layer has a plurality of perforates manifesting the line layer of part second side surface, with as second electric connection pad, wherein, the second welding resisting layer perforate aperture is less than the external diameter of second electric connection pad.
2. the structure of flip-chip substrate as claimed in claim 1 wherein, also comprises a plurality of solder projections, is formed on this first electric connection pad and second electric connection pad.
3. the structure of flip-chip substrate as claimed in claim 2 wherein, is formed with metal column earlier on this first electric connection pad and second electric connection pad and forms solder projection again.
4. the structure of flip-chip substrate as claimed in claim 2, wherein, be formed with etching stopping layer and metal column earlier on this first electric connection pad and second electric connection pad after, form solder projection again.
5. as the structure of claim 1,2,3 or 4 described flip-chip substrates, wherein, also comprise a retaining piece, it is disposed at the top all around of this second welding resisting layer, in order to avoid the warpage of this substrate.
6. the structure of flip-chip substrate as claimed in claim 1, wherein, this first electric connection pad and second electric connection pad are copper.
7. the structure of flip-chip substrate as claimed in claim 4, wherein, the employed material of this etching stopping layer is a gold.
8. the structure of flip-chip substrate as claimed in claim 3, wherein, the material that this metal column uses is copper.
9. the structure of flip-chip substrate as claimed in claim 2, the material that this solder projection uses is selected from one of copper, tin, lead, silver, nickel, gold, platinum and the formed group of alloy thereof person.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710100958 CN101295698A (en) | 2007-04-28 | 2007-04-28 | Flip-chip substrate structure and production method thereof |
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| CN 200710100958 CN101295698A (en) | 2007-04-28 | 2007-04-28 | Flip-chip substrate structure and production method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102820328A (en) * | 2011-06-09 | 2012-12-12 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
| CN102833945A (en) * | 2011-06-15 | 2012-12-19 | 景硕科技股份有限公司 | Packaging substrate structure |
-
2007
- 2007-04-28 CN CN 200710100958 patent/CN101295698A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102820328A (en) * | 2011-06-09 | 2012-12-12 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
| CN102833945A (en) * | 2011-06-15 | 2012-12-19 | 景硕科技股份有限公司 | Packaging substrate structure |
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Open date: 20081029 |