200837916 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種半導體基板結構及其製作方法，尤 指一種適用於具有良好電性、散熱性及尺寸安定性之半導 5 體基板結構及其製作方法。 【先前技術】 隨著電子產業的蓬勃發展，電子產品亦逐漸邁入多功 能、高性能研發趨勢，為滿足半導體封裝建高積集度 10 (Integration)及微型化（Miniaturization)的封裝需求，以供更 多主動、被動元件或線路互相電性連接，承載半導體晶片 之電路板藉由配合高線路密度之積體電路（Integrated circuit)需求，以在相同電路板單元下提高線路密度以接置 更多數量的電子元件。 15 在目前習知的半導體基板或印刷電路板（printed wiring board ; PWB)中的通孑L，都是利用樹月旨或者是綠漆等 等予以塞孔，接著再繼續後續之增層結構。在習知的結構 中，請參考圖1A及1B，其係為習知的半導體基板結構剖視 圖。如圖1A所示，此半導體基板具有一核心板Π a、一線路 20 層 12以及一電鍍導通孔（Plating Through Hole ; PTH)13。線 路層12係形成於核心板11a表面兩侧，而電鍍導通孔13則形 成於核心板11a内以電性導通核心板11a兩侧的線路層12。 再如圖1B所示，其係為四層半導體基板結構，其具有核心 板lib、内層線路層123、外層線路層121>、第一電鍍導通孔 5 200837916 13a、第二電鍍導通孔13b以及導電盲孔15。其中，第一電 鍍導通孔13a可導通在核心板ub兩侧的内層線路層12a，第 一笔鑛$通孔13b可導通半導體基板兩侧之外層線路層 12b而$龟目孔15則用以導通内層線路層12a與外層線路 5層12b。在此，不論如圖1入所示之電鍍導通孔13或者如圖13 所不之第一電鍍導通孔13a及第二電鍍導通孔13b均以一絕 緣樹脂14塞孔，然而在填充絕緣樹脂14時係利用網版印刷 塞孔的技術，此技術雖然較為普遍且方便但是仍有許多缺 ”、、έ例如.其作業人員需要累積相當之操作經驗後方可熟 10練、每一網版需針對不同塞孔孔徑而製作不同之網版或因 通孔尺寸過小而使樹酯或綠漆無法填充，因此生產效率較 差，且亦使通孔尺寸不能做太小以致發生塞孔困難，故通 孔尺寸須做大，則基板佈線密度下降，而無法作細線路的 製程及佈線設計；此外塞孔材料之熱膨脹係數與電鍍導通 15 =孔壁金屬不匹配亦衍生基板可#度問題。另外，在製作 所所提供的核心板兩側係具有銅落（圖未示），而在製作完成 後其銅箱保留在半導體基板結構上，在高溫無錯之操作環 境下時，因其延展性差易產生斷裂而有可靠度不良的問題。 20 【發明内容】 半導體基板結構，此結 電柱，其係形成於該核 至少一第一線路層於核 係形成於該核心板内； 有鑑於此，本發明係提供一種 構包括：一核心板；至少一第一導 心板内，且該第一導電柱係延伸出 心板兩側表面；至少一第二導電柱 6 200837916 以及至少一第二線路層，形成於核心板表面。 ♦枉Γΐ上Γ的結構，本發明的第—線路層底部及第一導 ，、核心板間所形成之周緣復包括-第-導電層。 依據上述本發明之半導體基板結構，例如可^下述， 但不限於此之步驟製作。 2 ’本發明亦提供_種半導體基板結構的製作方 板內开:1驟包括：首先，提供一核心板。接著，於此核心 數個通孔。再純心板表面及通孔的内壁形成 蛉电層。隨後，於核心板表面及通孔内之第一 :上形成-第一金屬層。最後，蝕刻部 声 «於其下之第-導電層，以使第—金屬層於該 刀別形成至少-第—導電柱及至少_第二導電柱，且核心 t面形成-第-線路層及—第二線路層，其中該第」線 路層形成於第一導電柱的兩侧。 15 20 :僅僅於上述本發明之半導體基板結構，本發明更提供另 種半導體基板結構，此種結構包括：一核心板；至少一 第二導電柱，其係形成於該核心板内；以及至少一第三線 路層，其係形成於部分之該第二導電柱表面及核心板表 面。因此，在此結構中，可得到最佳的金屬延展2，同^ 可提升細線路之可靠度品質。 依據上述的結構中’第二導電柱與核心板間所形成之 周緣復包括一第一導電層，且第三線路層底部復包括一第 一導電層。 同樣地，依據上述本發明之半導體基板結構，例如可 7 200837916 由下述，但不限於此之步驟製作。 因此，本發明又提供一種半導體基板結構的製作方 法，此步驟包括：首先，提供一核心板。接著，於此核心 板内形成至少一通孔。再於核心板表面及通孔的内壁形成 5 一第一導電層。然後，於核心板表面及通孔内之第一導電 層上形成一第一金屬層。接著，於核心板表面以餘刻之方 式將第一金屬層及覆蓋於其下之該第一導電層移除，且通 孔内之第一金屬層係形成一第二導電柱。然後，於核心板 表面可形成一第二導電層。再於第二導電層上形成一圖案 10 化阻層，且此阻層内可形成複數個阻層開口。隨後，於此 等阻層開口内可形成一第二金屬層。最後，移除阻層及覆 蓋於其下之第二導電層，且第二金屬層係可作為一第三線 路層。 在上述本發明中，核心板不限使用任何材料，其係可 15 例如為 ABF(Ajinomoto Build-up Film )、苯拼環丁浠 (Benzocyclo· buthene ; BCB)、液晶高分子聚合物（Liquid Crystal Polymer ; LCP)、聚乙驢胺（Polyimide ; PI)、聚乙烯 醚（Poly(phenylene ether) ; PPE)、聚四氣乙浠 (Poly(tetra-fluoroetliyleiie) ; PTFE)、FR4、FR5、雙順丁醯 20 二酸醢亞胺/三氮拼（Bismaleimide Triazine ; BT)、芳香尼龍 (Aramide)等感光或非感光有機樹脂，或亦可混合環氧樹脂 與玻璃纖維等材質所組成之群組。 在本發明中，該核心板亦可為銅箔基板（CCL)或已具有 多層線路層且表面壓合有背膠銅箔（RCC)之電路板之其中 8 200837916 一者。 孔方3::者形成通孔的方式可為機械鑽孔或雷射鑽 本發明的第—導電層以及第二導 =製程所需之電流傳導路徑，第一導電層及== 導：！2、合金或堆疊數層的金屬所组成，或者又可為 10 15 20 為金屬、合金或堆疊數層的金屬所組成時， 广銅、錫、鎳、路、鈦、銅-鉻合金以及錫_錯合金中 組^群組之—者，且以物理沈積及化學沈積之—者形 二，、中’較佳地’物理沈積的方法係為_及蒸鑛其中 :::、’而化學沈積的方法係為無電電鍍。若以導電高分 作為*電層，則以噴灑（spraying)方式形成，1中 ，分子係選自由聚乙炔、聚苯胺以及有機硫聚合卿且 成之群組之一者。 、 在本發明中，第一金屬層係使用電鍍的方式形成。此 外，第-金屬層可以使用的材料較佳地為銅、錫、鎳、絡、 鈦、銅-鉻合金以及鍚-鉛合金中所組成之群組之一者。更1佳 地’則可以使用銅金屬作為第一金屬層。 本發明中，第一線路層以及第二線路層其係經由第一 金屬層電㈣再經個而形成，因此，制之材料係與第 一金屬層的材料相同。 另外’本發明另-結構中，第三線路層，係經由圖宰 化阻層以電锻製程形成第二金屬層’而於核心板表面形成 弟二線路層，纟，第三線路層的材料係與第二金屬層的材 9 200837916 料相同。然而，本發明中的第二金屬層使用的材料係可為 銅、錫、鎳 '鉻、鈦、銅_鉻合金以及錫_鉛合金所袓二 群組之一者。較佳則可以使用銅。 斤、、且成之 再者’ Witt ’本發明所使用之阻層可為習用微200837916 IX. The invention relates to a semiconductor substrate structure and a manufacturing method thereof, and more particularly to a semiconductive 5-body substrate structure suitable for good electrical properties, heat dissipation and dimensional stability. Its production method. [Prior Art] With the rapid development of the electronics industry, electronic products are gradually entering the trend of multi-functional, high-performance research and development, in order to meet the packaging requirements of semiconductor package building integration 10 and miniaturization. For more active, passive components or circuits to be electrically connected to each other, the circuit board carrying the semiconductor chip is required to increase the line density under the same circuit board unit by connecting with a high circuit density integrated circuit. A large number of electronic components. 15 In the conventional semiconductor substrate or printed wiring board (PWB), the overnight L is filled with a tree or a green paint, etc., and then the subsequent buildup structure is continued. In the conventional structure, please refer to Figs. 1A and 1B, which are cross-sectional views of a conventional semiconductor substrate structure. As shown in FIG. 1A, the semiconductor substrate has a core plate a, a line 20 layer 12, and a plating via hole (PTH) 13. The wiring layer 12 is formed on both sides of the surface of the core board 11a, and the plating vias 13 are formed in the core board 11a to electrically conduct the wiring layers 12 on both sides of the core board 11a. Further, as shown in FIG. 1B, it is a four-layer semiconductor substrate structure having a core board lib, an inner layer wiring layer 123, an outer layer wiring layer 121, a first plating via hole 5 200837916 13a, a second plating via hole 13b, and a conductive Blind hole 15. The first plating via 13a can be electrically connected to the inner layer 12a on both sides of the core board ub. The first penetrating hole 13b can open the outer layer 12b on both sides of the semiconductor substrate and the turtle hole 15 can be used. The inner wiring layer 12a and the outer wiring 5 layer 12b are turned on. Here, the plating via 13 as shown in FIG. 1 or the first plating via 13a and the second plating via 13b as shown in FIG. 13 are each plugged with an insulating resin 14, but the insulating resin 14 is filled. When using the technology of screen printing plug hole, this technology is more common and convenient, but there are still many shortcomings, such as. Its operators need to accumulate considerable operational experience before they can practice 10 training, each screen version needs to be targeted Different screen apertures are used to make different screens or the resin or the green paint cannot be filled because the size of the through holes is too small, so the production efficiency is poor, and the size of the through holes cannot be too small to cause plugging difficulties, so the through holes If the size needs to be large, the substrate wiring density is lowered, and the process and wiring design of the thin circuit cannot be made; in addition, the thermal expansion coefficient of the plug material and the plating conduction 15 = hole wall metal mismatch can also be used to derive the substrate problem. The core board provided by the manufacturer has copper drop (not shown) on both sides, and the copper box remains on the semiconductor substrate structure after the completion of the fabrication, in the high temperature and error-free operating environment, a problem that the ductility is likely to be broken and the reliability is poor. 20 [Invention] The semiconductor substrate structure is formed in the core, at least one first circuit layer is formed in the core layer in the core layer; Therefore, the present invention provides a structure comprising: a core board; at least one first lead plate, and the first conductive post extends from both side surfaces of the core plate; at least one second conductive post 6 200837916 and at least one The second circuit layer is formed on the surface of the core board. ♦ The structure of the upper layer of the cymbal, the bottom of the first circuit layer of the present invention and the first conductor, and the periphery formed by the core board further includes a -first conductive layer. The semiconductor substrate structure of the invention can be fabricated, for example, but is not limited to the steps described herein. 2 'The present invention also provides for the fabrication of a semiconductor substrate structure. The first step includes: first, providing a core board. There are several through holes in the core. The inner surface of the pure core plate and the inner wall of the through hole form a tantalum layer. Then, a first metal layer is formed on the surface of the core plate and the first hole in the through hole. Finally, the etching portionSounding the first conductive layer, such that the first metal layer forms at least a first conductive pillar and at least a second conductive pillar, and the core t surface forms a - first wiring layer and - a second a circuit layer, wherein the first circuit layer is formed on both sides of the first conductive pillar. 15 20: In the above-described semiconductor substrate structure of the present invention, the present invention further provides another semiconductor substrate structure, the structure comprising: a core plate; at least one second conductive column formed in the core plate; and at least A third circuit layer is formed on a portion of the surface of the second conductive pillar and the surface of the core plate. Therefore, in this structure, the best metal extension 2 can be obtained, and the reliability of the fine line can be improved. According to the above structure, the periphery formed by the second conductive pillar and the core plate further comprises a first conductive layer, and the bottom of the third circuit layer further comprises a first conductive layer. Similarly, the semiconductor substrate structure according to the present invention described above can be produced, for example, by the following steps, but is not limited to this step. Therefore, the present invention further provides a method of fabricating a semiconductor substrate structure, the method comprising: first, providing a core board. Next, at least one through hole is formed in the core plate. Further, a first conductive layer is formed on the surface of the core plate and the inner wall of the through hole. Then, a first metal layer is formed on the surface of the core plate and the first conductive layer in the through hole. Then, the first metal layer and the first conductive layer covering the underlying layer are removed on the surface of the core board in a residual manner, and the first metal layer in the through hole forms a second conductive pillar. Then, a second conductive layer can be formed on the surface of the core board. A pattern 10 photoresist layer is formed on the second conductive layer, and a plurality of resist layer openings are formed in the resist layer. Subsequently, a second metal layer can be formed in the opening of the resist layer. Finally, the resist layer and the second conductive layer underlying it are removed, and the second metal layer serves as a third wiring layer. In the above invention, the core plate is not limited to any material, and may be, for example, ABF (Ajinomoto Build-up Film), Benzocyclobut Buthen (BCB), Liquid Crystal Polymer (Liquid Crystal). Polymer; LCP), Polyimide (PI), Poly(phenylene ether; PPE), Poly(tetra-fluoroetliyleiie; PTFE), FR4, FR5, Bishun A photosensitive or non-photosensitive organic resin such as Bismaleimide Triazine (BT) or armine (Aramide), or a combination of epoxy resin and glass fiber. In the present invention, the core board may also be a copper foil substrate (CCL) or a circuit board having a multilayer wiring layer and a surface laminated with a backing copper foil (RCC). Hole 3:: The way to form the through hole can be mechanical drilling or laser drilling. The first conductive layer of the present invention and the second conduction = current conduction path required for the process, the first conductive layer and == guide: 2, alloy or stacked several layers of metal, or 10 15 20 for metal, alloy or stacked layers of metal, copper, tin, nickel, road, titanium, copper-chromium alloy and tin _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The method of deposition is electroless plating. If the conductive high score is used as the * electric layer, it is formed by spraying. In the first embodiment, the molecular system is selected from the group consisting of polyacetylene, polyaniline, and organic sulfur. In the present invention, the first metal layer is formed by electroplating. Further, the material which can be used for the first metal layer is preferably one of a group consisting of copper, tin, nickel, cobalt, titanium, copper-chromium alloy and bismuth-lead alloy. More preferably, copper metal can be used as the first metal layer. In the present invention, the first wiring layer and the second wiring layer are formed by the first metal layer (4), and therefore, the material is made the same as the material of the first metal layer. In addition, in the other structure of the present invention, the third circuit layer forms a second metal layer by an electric forging process via a patterned resist layer, and forms a second circuit layer on the surface of the core plate, and a material of the third circuit layer. It is the same as the material of the second metal layer 9 200837916. However, the material used in the second metal layer in the present invention may be one of two groups of copper, tin, nickel 'chromium, titanium, copper-chromium alloy, and tin-lead alloy. Preferably, copper can be used.斤,和成成, 'Witt' The barrier layer used in the present invention may be a conventional micro
(Ph〇t〇llthGgraphy)製程所適用之阻層材料較佳可為一感I 材料’且此感光材料可為 能弁阻μφ_Γ 由乾膜（dry mm)及液 i f 且，本發明中阻層之形成無限制，較 么可2用印刷、旋轉塗佈、貼合或前述方式之組合。 前述本發明的封裝基板結構及其製作方法中° 括線路增層結構，其係可形成於具有第—線路層及第^ :層之核心板表面或可形成於具有第三線路層之核心：表 面。而此線路增層結構包括有一介電層、至少一疊置 電層上之增層線路層以及複數個導電盲孔。 、 15 20 此外，在前述形成有料增層結構的縣基板 中，復包括至少一第三導電柱，係貫 ❹ ::::剛線路增層結構之增層線路層及= =上之部W二線路層’或者形成於核心板上之部分 =層。X，在前述的封裝基板結構中，完 : 構後’係可再於此等線路增層結構的表面 以、: 性樹脂。 而树層的材料較佳可為感光 基於前述，本發明之半導體基板及其製作方法 代習知以樹脂塞人通孔之方式所形成㈣料通孔，不 可“繁雜的步驟’而且可以提升生產良率以及減少成 10 200837916 二:時避，所形成的導電柱可以具有良好的電性、 X:二材料熱膨脹係數舆電鍍導通孔孔壁全屬 不匹配的問題，更可以做到細線路的製程能力與佈線設;屬 【實施方式】 以下係藉由特定的且靜每〜 式，熟習此技蔽之人亍可由广爾發明之實施方 :务明之其他優點與功效。本發明亦可藉由其他不同 的具體實施例加以施行或岸 ,、 10 15 20 环A认 丁飞應用，本祝明書中的各項細節亦 種i偷 點與應用，在不㈣本發明之精神下進行夂 種修飾與變更。 疋n合 =明之實施例中該等圖式均為簡化之示意圖。惟該 :圖她示與本發明有關之元件，其所顯示之元件非為 貝際貫施時之離樣，J：膏Ρ疚奋士 - 為 例為—選擇性：”:、且：Λ=之爾目、形狀等比 實施例 70件佈局型態可能更複雜。 請參相2,其係為本發料導體基板結構剖視圖。盆 匕括了一核心板21、至少一第一導電柱241、至少一第二導 =2以及至少一第，線路層244。第一導電桂241物 、板21内，且此第一導電柱241係延伸出至少一 =層243於核心、板21兩側表面。此外，第二導電㈣ $成於核心板21内，而第二線路層244係形成於枝心板以 ::在此，第-導電柱241及其所延伸之第1路層243 : —導電柱242以及第二線路層244所使用的材料係為相 11 200837916 同，於本實施例中係使用銅。而本實施例中係以一銅落基 板⑼沖打❿^獲脱如：^^為核心板以之基底’其在 表面具有一金屬薄層21a，即銅箔，且厚度可為約2〜12^瓜。 此外，本實施例亦可在第一線路層243底部以及第一導 5電柱241舆核心板21所形成之周緣形成一第一導電層23。同 樣地，在第二線路層244底部、第二導電柱242與核心板以 所形成之周緣亦形成同時形成此第一導電層23。此第一導 電層2 3主要在於進行電鍍製程時所需的電流傳導路徑之 用。因此，第一導電層23可使用的材料為導電材料，例如 10銅或導包鬲分子。在本實施例中第一導電層23係使用銅。 實施例2 本貫施例使用的材料係可如實施例丨的材料相同。本實 施例係可製造如圖2所示之半導體基板結構。請參考圖3A 至3E係為本务明半導體基板結構製作流程剖視圖。 15 如圖3A所示，提供一核心板21，此核心板表面具有一 金屬薄層21a，例如銅箔，且厚度可為約卜^口瓜。接著，如 圖3B中，係利用機械鑽孔或雷射方式將核心板㈣成複數 個通孔22，惟當利用雷射鑽孔的技術時，]复需進行除膠逢 (De-smear)作業以移除因鑽孔所殘留於通孔22内的膠渣。 2〇 然後’如圖3C所示，於核心板21表面及通孔22内壁以 無電電鍍的方式形成一第一導電層23，而此第一導電層^ 主要在於進行後續電鍍製程時所需的電流傳導路徑之用。 +隨後’於核心板21表面及通孔22内之第一導電層23上以 電鍍的方式形成一第-金屬層24,❿形成如圖3]3所示之結 12 200837916 構。，中，此第-金屬層24使用的材料係為鋼。 最後，如圖3E所示，爾後進行圖案化製程，利用渴式 蝕刻或是乾式姓刻的方式將此第—金屬層24予以圖幸化線 路製程，以移除部分第-金屬層24，同時亦將覆蓋於欲移 5除之第-金屬層24下之第一導電層23以及金屬薄層仏移 除，而顯露出此核心板2卜以使第一金屬層24於通孔加 分別形成至少-第一導電柱241及至少一第二導電柱242, 且核心板21表面形成一第一線路層243及一第二線路層 244其中，第一線路層243形成於第_導電柱“I的兩側。 10因此，而得到本實施例之半導體基板結構。 實施例3 本實施例使用的材料係可與實施例丨的材料相同。請參 考圖4，係為本實施例半導體基板結構之剖簡。如圖*所 示’其包括-核心板2卜至少一第二導電柱如以及一第三 15 f路層33。其中，第二導電柱242則形成於核心板21内，而 第三線路層33係形成於部分之第二導電柱242表面及核心 板21表面。在此，第二線路層33使用的材料係亦為銅。 此外，在本貫施例中，於第二導電柱242與核心板2工間 所形成之周緣内係可形成一第一導電層23。而在第三線路 20層33的底部係形成有一第二導電㈣。第一導電層23的材 2與實施例1相同’而第二導電層31可使用的材料為銅或 T電高分子’在本實施例中係為銅。在此結構中，此種半 $體基板結構可以作更細之線路，以符合各種產品之需求。 實施例4 13 200837916 本實施例使用的材料係可如實施例3的材料相同。另， 在本實施例中，其製造流程的前段製程可如實施例2之圖3A 至3D的步驟實施，而在接下來的製程則與實施例2不同，請 ^固A至，係為本發明半導體基板結構製作流程剖視 在得到如圖3D所示之結構之後，再以濕式蝕刻或乾式 J的方式將核心板21表面的第一金屬層μ及覆蓋於其下 =第:導電層23完全移除以及同時會移除核心板21表面之 金屬薄層2U。此時’仍然保留通孔22内的第一金屬層24以 形成一第二導電柱242，而可得到如圖5八所示的結構。核心 板21表面經過兹刻之後不會完全光滑，而具有—粗棱度（圖 未:）。然而，可利用此粗糙度增加在後續製程中之線路結 合能力。 15 20 接者’如圖5B所示，於此核心板21表面利用無電電鍛 :形成一第二導電層31，且此第二導電層31使用的材料 導電高分子，以作為進行後續電鑛製程時所需的 ' /;’L、¥路搜之用。在本實施例中的第二導電層31係使用 銅0 方所示’於第二導電層31上可利用印刷的 "/成—以乾膜做成的阻層32，且此阻層32係利 以及顯影之方式形成複數個阻層開口仏，當在進行曝光時 使用的光_可以為以料光照射，而顯影時則可二以一 般使用於半導體製程的顯影劑，而形成本發阻 32a’進而得到—圖案化阻層％。 層開口 14 200837916 最後，如圖5D所示，於圖5C中之阻層開口 32&内以電鍍 的方式形成一第二金屬層34，其中，此第二金屬層34使用 的材料係為銅。爾後移除阻層32及蝕刻覆蓋於此阻層32下 之第二導電層31。因此，核心板21表面的第二金屬層料及 5其下之第二導電層31係可作為一第三線路層33，而可得到 本發明之半導體基板結構。 實施例5(Ph〇t〇llthGgraphy) The resist material suitable for the process may preferably be a sensible material I and the photographic material may be 弁 μ μφ_Γ from dry film and liquid if and, in the present invention, the resist layer The formation is not limited, and it can be used by printing, spin coating, lamination or a combination of the foregoing. The package substrate structure of the present invention and the manufacturing method thereof include a line build-up structure, which may be formed on the surface of the core board having the first circuit layer and the second layer or may be formed on the core having the third circuit layer: surface. The line build-up structure includes a dielectric layer, at least one build-up circuit layer on the stacked electrical layer, and a plurality of conductive blind vias. Further, in the above-mentioned county substrate on which the material-added layer structure is formed, at least one third conductive column is further included, and the layered layer of the ::::-added circuit layer and the upper part of the upper layer W The second circuit layer 'or part of the layer formed on the core board. X, in the above-mentioned package substrate structure, the structure of the circuit build-up structure can be further: The material of the tree layer is preferably sensitized based on the foregoing. The semiconductor substrate of the present invention and the method for fabricating the same are conventionally formed by means of a resin plug hole (4) through-hole, which is not a "complex step" and can improve production. Yield and reduction to 10 200837916 2: Avoidance, the formed conductive column can have good electrical properties, X: thermal expansion coefficient of two materials, 舆 electroplated via hole wall is completely mismatched, and can also achieve thin circuit process capability </ RTI> </ RTI> </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; Different specific embodiments are implemented or applied to the shore, and 10 15 20 ring A recognizes Dingfei application. The details in this book are also used to steal and apply. In the spirit of the invention, modifications and changes are made. The drawings are simplified in the embodiment of the present invention. However, the drawings show the components related to the present invention, and the components shown therein are not separated from each other, J: paste Ρ疚力士 - For example - selectivity: ":, and: Λ = er, shape, etc. The 70 layout pattern of the embodiment may be more complicated. Please refer to phase 2, which is a cross-sectional view of the structure of the conductor substrate of the present invention. The basin includes a core board 21, at least one first conductive post 241, at least one second lead = 2, and at least one first, circuit layer 244. The first conductive 241 is in the plate 21, and the first conductive pillar 241 extends at least one layer 243 on both sides of the core and the plate 21. In addition, the second conductive (four) $ is formed in the core board 21, and the second circuit layer 244 is formed on the branching board to:: here, the first conductive pillar 241 and the first road layer 243 extending therefrom: - conductive The material used for the pillars 242 and the second wiring layer 244 is phase 11 200837916, and copper is used in this embodiment. In this embodiment, the copper substrate (9) is punched and removed, such as: the substrate is a core plate having a thin metal layer 21a, that is, a copper foil, and the thickness can be about 2~ 12^ melon. In addition, in this embodiment, a first conductive layer 23 may be formed on the bottom of the first circuit layer 243 and the periphery of the first conductive pillar 241 and the core plate 21. Similarly, the first conductive layer 23 is formed simultaneously with the second conductive pillar 242 and the core plate formed at the bottom of the second wiring layer 244. This first conductive layer 23 is mainly used for the current conduction path required for the electroplating process. Therefore, the material that can be used for the first conductive layer 23 is a conductive material such as 10 copper or a germanium-containing molecule. In the present embodiment, the first conductive layer 23 is made of copper. Example 2 The materials used in the present examples were the same as those of the examples. This embodiment can fabricate a semiconductor substrate structure as shown in Fig. 2. Please refer to FIG. 3A to FIG. 3E as cross-sectional views showing the manufacturing process of the semiconductor substrate structure. As shown in Fig. 3A, a core board 21 is provided having a thin metal layer 21a, such as a copper foil, and having a thickness of about 3,000. Next, as shown in FIG. 3B, the core plate (four) is formed into a plurality of through holes 22 by mechanical drilling or laser, but when using the technique of laser drilling, the de-smear is required. The job is to remove the slag remaining in the through hole 22 due to the drilling. 2〇 Then, as shown in FIG. 3C, a first conductive layer 23 is formed on the surface of the core plate 21 and the inner wall of the through hole 22 by electroless plating, and the first conductive layer is mainly required for performing a subsequent plating process. Used for current conduction paths. + Subsequently, a first metal layer 24 is formed on the surface of the core plate 21 and the first conductive layer 23 in the via hole 22 by electroplating, and the germanium is formed into a structure as shown in Fig. 3] 3 200837916. In the middle, the material used for the first metal layer 24 is steel. Finally, as shown in FIG. 3E, a patterning process is performed, and the first metal layer 24 is patterned by a thirst etching or a dry pattern to remove a portion of the first metal layer 24 while The first conductive layer 23 and the thin metal layer 覆盖 under the first metal layer 24 to be removed are also removed, and the core plate 2 is exposed so that the first metal layer 24 is added to the via hole. Forming at least a first conductive pillar 241 and at least a second conductive pillar 242, and a surface of the core plate 21 is formed with a first wiring layer 243 and a second wiring layer 244, wherein the first wiring layer 243 is formed on the first conductive pillar. The two sides of I. Thus, the semiconductor substrate structure of the present embodiment is obtained. Embodiment 3 The material used in this embodiment can be the same as that of the embodiment 。. Please refer to FIG. 4, which is the semiconductor substrate structure of the present embodiment. The cross-section is as shown in FIG. *, which includes - a core plate 2, at least a second conductive post, and a third 15 f-way layer 33. The second conductive post 242 is formed in the core plate 21, and The third circuit layer 33 is formed on a portion of the surface of the second conductive pillar 242 and the core The surface of the second circuit layer 33 is also copper. In addition, in the present embodiment, a portion can be formed in the periphery formed between the second conductive pillar 242 and the core plate 2 a conductive layer 23. A second conductive (four) is formed on the bottom of the third line 20 layer 33. The material 2 of the first conductive layer 23 is the same as in the first embodiment, and the second conductive layer 31 can be made of copper or The T-electropolymer 'in this embodiment is copper. In this structure, the half-body substrate structure can be made into a finer line to meet the requirements of various products. Embodiment 4 13 200837916 This embodiment uses The material can be the same as the material of the embodiment 3. In addition, in the embodiment, the front-end process of the manufacturing process can be carried out as in the steps of FIGS. 3A to 3D of the embodiment 2, and in the subsequent process and the embodiment 2 Differently, please fix the A to the first metal layer on the surface of the core board 21 by wet etching or dry J after the structure of the semiconductor substrate structure of the present invention is obtained. μ and cover under it = the first: the conductive layer 23 is completely removed and the same The thin metal layer 2U on the surface of the core plate 21 is removed. At this time, the first metal layer 24 in the via hole 22 is still left to form a second conductive pillar 242, and a structure as shown in FIG. The surface of the plate 21 is not completely smooth after being inscribed, but has a thick edge (Fig.:). However, this roughness can be utilized to increase the line bonding ability in subsequent processes. 15 20 The picker is as shown in Fig. 5B. It is shown that the surface of the core board 21 is electrically wrought-free: a second conductive layer 31 is formed, and the second conductive layer 31 is made of a material conductive polymer as a '/;' required for subsequent electric ore processing. In the second embodiment, the second conductive layer 31 is formed by using a copper on the second conductive layer 31 to be printed on the second conductive layer 31. The layer 32, and the resist layer 32 forms a plurality of resistive opening openings in a manner of development and development, and the light used when performing the exposure may be irradiated with the material light, and the developing layer may be generally used for the semiconductor process. Developer, and form the local resistance 32a' to obtain - patterned resist layer%Layer Opening 14 200837916 Finally, as shown in FIG. 5D, a second metal layer 34 is formed by electroplating in the resist opening 32& in FIG. 5C, wherein the second metal layer 34 is made of copper. The resist layer 32 is then removed and the second conductive layer 31 underlying the resist layer 32 is etched. Therefore, the second metal layer on the surface of the core board 21 and the second conductive layer 31 underneath can be used as a third wiring layer 33, and the semiconductor substrate structure of the present invention can be obtained. Example 5
10 本實施例可依據實施例1的結構繼續製作另一形式之 半導體基板結構。料考圖6M6F ’係為製作本實施例半 導體基板結構流程圖。 15 首先，如圖6 A所示，提供一如圖2所 構，將此半導體基板結構作為一核心基板2如， 示之半導體基板結 於此核心基 板20a表面兩側壓合一介電層41。此介電層4ι的材料例如可 為 ABF(Ajin〇m〇t〇 Build，Film )、苯阱環丁烯（Benz〇cycl〇_ buthene ; BCB)、液晶高分子聚合物（Liquid Crystal10 This embodiment can continue to fabricate another form of semiconductor substrate structure in accordance with the structure of Embodiment 1. Fig. 6M6F' is a flow chart for fabricating the semiconductor substrate of this embodiment. First, as shown in FIG. 6A, a semiconductor substrate structure is provided as a core substrate 2. For example, the semiconductor substrate is bonded to a dielectric layer 41 on both sides of the surface of the core substrate 20a. . The material of the dielectric layer 4ι can be, for example, ABF (Ajin〇m〇t〇 Build, Film), Benzene cyclobutene (BCB), Liquid Crystal Polymer (Liquid Crystal).
Polymer ; LCP)、聚乙醯胺（Polyimide ; PI)、聚乙烯醚Polymer ; LCP), Polyimide (PI), Polyvinyl ether
20 (Poly(phenylene ether) ; PPE)、聚四氟乙烯^以乂⑽忭心 fluoroethylene) ; PTFE)、FR4、FR5、雙順丁 醯二酸醯亞胺 /三氮胖（Bismaleimide Triazine; BT)、芳香尼龍（Aramide) 等感光或非感光有機樹脂，或亦可混合環氧樹脂與玻璃纖 維等材質所組成之群組。在本實施例係使用ABF作為介電 層41。 接著，如圖6B所示，於介電層41内以雷射鑽孔的方式 形成一盲孔41a，並以機械鑽孔或雷射鑽孔方式形成一貫穿 15 200837916 核心基板20a及其表面兩側之介電層41的通孔41b。 然後，如圖6C所示，於介電層41表面、盲孔41a及通孔 41b内壁以無電電鍍的方式形成一第三導電層42。此第三導 電層42使用的材料係可為銅金屬。此第三導電層42的功能 5 係主要在於進行後續電鍍製程時所需的電流傳導路徑之 用。 再如圖6D所示，於第三導電層42表面以印刷的方式形 成一阻層43，其材料可為乾膜。此阻層43係可利用曝光及 顯影之方式形成複數個阻層開口 43a，並顯露出盲孔41a及 10 通孔41b。 最後，如圖6E所示，於圖6D中之阻層開口 43a、盲孔41 a 及通孔4 lb内以電鍍的方式，形成一電鍍金屬層44。此電鍍 金屬層44使用的材料為銅金屬。之後，移除阻層43及其所 覆蓋之第三導電層42。因此，所形成的電鍍金屬層44係用 15 以作為增層線路層441、導電盲孔442及第三導電柱443。其 中，導電盲孔442及增層線路層441係作為線路增層結構45 的一部份。此導電盲孔442係用以電性導通核心基板20a的 第一線路層243與第二線路層244以及線路增層結構45中的 增層線路層441。而第三導電柱443更可直接電性導通至核 20 心基板20a另一侧表面的增層線路層441及部分的第二線路 層 244 〇 此外，在完成前述的線路增層結構45之後，可如圖6F 所示，再於此線路增層結構45的表面形成一防焊層46，以 保護此線路增層結構45，而此防焊層46的材料係為感光性 16 200837916 樹脂。此防焊層46係利用曝光以及顯影之方式形成複數個 開口 461，此等開口 461係顯露出增層線路層441，以作為電 性連接墊444，而可與外部電子元件電性連接。 、因此，在本實施例中係以實施例1的半導體基板結構作 5為一核心基板2〇a，此核心基板2〇a表面係可形成一線路增 層結構45，以作為不同形式之半導體基板結構。 曰 實施例6 • 本實施例係與實施例5相同，但不同的是’請參考圖7， 本實施例使用的核心基板20b係為實施例3中之半導體基板 1〇結構，其餘步驟皆與實施例5相同。在此，導電盲孔44土2係 電性導通核心基板鳥的第三線路層33以及線 籌 45中的增層線路層441。而第二導 、'，σ構 乐一 V包柱443可直接電性導通 15 至核心基板20b另-侧表面的增層線路層441及部分的第三 線路^3。進而完成本實施例的半導體基板結構。 20 带综上所述，相較於習知的電料通孔結構中所包括的導 =、，銅層以及絕緣樹脂，在填充絕緣_的製Μ 三土塞孔材料熱膨脹係數與電鑛導通孔孔壁金屬不匹配 七可靠度問題。本發明利用導電柱取代電鑛導通孔，其僅 :括：：層以及金屬銅。在此結構中’可以具有良好的電 入屬=性、避免塞孔材料熱膨脹係數與電料通孔孔壁 設計。 更了以做到細線路的製程能力與佈線 A板姓i依據本^明實施例3及實施例4中所形成的半導體 構所形成的線路，因為金屬薄層完全去除，其所得 17 200837916 到的線路（即第三線路層 之可靠度品質。 )可得到最佳的延展性，提升細線路 上述實施例僅係為了方便說明而舉例而已，本發 主張之權利範圍自應以巾請專利_所述為準，而非 於上述實施例。 ^20 (Poly (phenylene ether); PPE), polytetrafluoroethylene ^ 乂 (10) fluoro fluoroethylene); PTFE), FR4, FR5, bis-succinimide bismuth imide / bis(Bismaleimide Triazine; BT) A photosensitive or non-photosensitive organic resin such as Aramide or a combination of epoxy resin and glass fiber. In the present embodiment, ABF is used as the dielectric layer 41. Next, as shown in FIG. 6B, a blind hole 41a is formed in the dielectric layer 41 by laser drilling, and a through hole 15 200837916 core substrate 20a and its surface are formed by mechanical drilling or laser drilling. The through hole 41b of the dielectric layer 41 on the side. Then, as shown in FIG. 6C, a third conductive layer 42 is formed on the surface of the dielectric layer 41, the blind via 41a, and the inner wall of the via 41b by electroless plating. The material used for the third conductive layer 42 may be copper metal. The function of the third conductive layer 42 is mainly for the current conduction path required for the subsequent plating process. Further, as shown in Fig. 6D, a resist layer 43 is formed on the surface of the third conductive layer 42 in a printed manner, and the material thereof may be a dry film. The resist layer 43 is formed by forming a plurality of barrier openings 43a by exposure and development, and reveals the blind vias 41a and 10 through holes 41b. Finally, as shown in FIG. 6E, a plating metal layer 44 is formed by electroplating in the resist opening 43a, the blind via 41a and the via 4lb in FIG. 6D. The material used for the plated metal layer 44 is copper metal. Thereafter, the resist layer 43 and the third conductive layer 42 covered thereon are removed. Therefore, the formed electroplated metal layer 44 is used as the build-up wiring layer 441, the conductive blind vias 442, and the third conductive pillars 443. The conductive blind vias 442 and the build-up wiring layer 441 are part of the line build-up structure 45. The conductive via hole 442 is for electrically conducting the first circuit layer 243 and the second circuit layer 244 of the core substrate 20a and the build-up wiring layer 441 of the line build-up structure 45. The third conductive pillar 443 is directly electrically conductively connected to the build-up wiring layer 441 and the partial second wiring layer 244 on the other side surface of the core 20 core substrate 20a. Further, after the aforementioned line build-up structure 45 is completed, As shown in FIG. 6F, a solder resist layer 46 is formed on the surface of the line build-up structure 45 to protect the line build-up structure 45. The material of the solder resist layer 46 is photosensitive 16 200837916 resin. The solder resist layer 46 is formed by a plurality of openings 461 by exposure and development. The openings 461 expose the build-up wiring layer 441 as an electrical connection pad 444 and can be electrically connected to external electronic components. Therefore, in the present embodiment, the semiconductor substrate structure of Embodiment 1 is used as a core substrate 2A, and the surface of the core substrate 2A can form a line build-up structure 45 to serve as a semiconductor of different forms. Substrate structure.曰Embodiment 6 • This embodiment is the same as Embodiment 5, but the difference is 'Please refer to FIG. 7. The core substrate 20b used in this embodiment is the semiconductor substrate 1〇 structure in Embodiment 3, and the remaining steps are the same. Example 5 is the same. Here, the conductive blind hole 44 is electrically connected to the third wiring layer 33 of the core substrate bird and the build-up wiring layer 441 of the line 45. The second conductive, ', σ music-V-pack 443 can directly electrically conduct 15 to the additional wiring layer 441 of the other-side surface of the core substrate 20b and a portion of the third wiring ^3. Further, the structure of the semiconductor substrate of this embodiment is completed. 20 In the above, compared with the conventional conductive material through-hole structure, the conductive layer, the copper layer and the insulating resin, the thermal expansion coefficient of the three-earth plug material and the electrical conductivity conduction in the filling insulation_ The hole wall metal does not match the seven reliability issues. The invention replaces the electric ore vias with conductive pillars, which only include: layers and metallic copper. In this structure, 'there can be good electrical conductivity=, avoiding the thermal expansion coefficient of the plug material and the design of the through-hole wall of the electric material. Moreover, in order to achieve the fine circuit process capability and the wiring A board name i according to the semiconductor structure formed in Embodiment 3 and Embodiment 4, since the thin metal layer is completely removed, the resulting 17 200837916 The line (that is, the reliability quality of the third circuit layer) can obtain the best ductility, and the fine line is improved. The above embodiments are only examples for convenience of explanation, and the scope of the claims of the present invention is to be patented. The above is true, not the above embodiment. ^
10 【圖式簡單說明】 圖1A及1B係習知之且右雷雜道、s , “μη孔之轉體基板結 圖2係本發明—較佳實施例之半導體基板結構剖視圖。 圖3A至3E係本發明_較佳實施例之半導體基板 作流程剖視圖。 再表 圖 圖4係本發明另—較佳實施例之半導體基板結構剖視 1510A and 1B are conventional and right-handed tracks, s, "transfer substrate of μη hole, FIG. 2 is a cross-sectional view of the structure of the semiconductor substrate of the preferred embodiment of the present invention. Figs. 3A to 3E A cross-sectional view of a semiconductor substrate according to a preferred embodiment of the present invention. FIG. 4 is a cross-sectional view showing a structure of a semiconductor substrate according to another preferred embodiment of the present invention.
構製發明另―㈣實㈣之半導體基板結 製本發明再—較佳實施例之半㈣基板結構 20 圖 。圖7係本發明又-較佳實施例之半導體基板結構剖視 12 12a 線路層 内層線路層 【主要元件符號說明】 UMlbJi核心板 13 電鍍導通孔 18 200837916STRUCTURE OF THE INVENTION - (4) Semiconductor substrate fabrication of the fourth embodiment of the present invention - a half (four) substrate structure of the preferred embodiment. 7 is a cross-sectional view showing the structure of a semiconductor substrate according to still another preferred embodiment of the present invention. 12 12a circuit layer inner layer circuit layer [Description of main components] UMlbJi core board 13 electroplated via hole 18 200837916
12b 外層線路層 13b 第二電鍍導通孔 15 導電孔 21 核心板 22 通孔 24 第一金屬層 242 第二導電柱 244 第二線路層 32 阻層 33 第三線路層 41a 盲孔 42 第三導電層 43a 阻層開口 441 增層線路層 443 第二導電柱 46 防焊層 34 第二金屬層 13a 第一電鍍導通孔 14 絕緣樹脂 20a520b 核心基板 21a 金屬薄層 23 第一導電層 241 第一導電柱 243 第一線路層 31 第二導電層 32a 阻層開口 41 介電層 41b 通孔 43 阻層 44 電鍍金屬層 442 導電盲孔 45 線路增層結構 444 電性連接墊 1912b outer wiring layer 13b second plating via 15 conductive hole 21 core plate 22 via 24 first metal layer 242 second conductive pillar 244 second wiring layer 32 resist layer 33 third wiring layer 41a blind via 42 third conductive layer 43a resistive opening 441 buildup wiring layer 443 second conductive pillar 46 solder resist layer 34 second metal layer 13a first plating via 14 insulating resin 20a520b core substrate 21a metal thin layer 23 first conductive layer 241 first conductive pillar 243 First circuit layer 31 second conductive layer 32a resist opening 41 dielectric layer 41b via 43 resist layer 44 plated metal layer 442 conductive blind hole 45 line build-up structure 444 electrical connection pad 19