CN100584155C - Manufacture process for substrate of internally embedded element - Google Patents
Manufacture process for substrate of internally embedded element Download PDFInfo
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- CN100584155C CN100584155C CN200710100549A CN200710100549A CN100584155C CN 100584155 C CN100584155 C CN 100584155C CN 200710100549 A CN200710100549 A CN 200710100549A CN 200710100549 A CN200710100549 A CN 200710100549A CN 100584155 C CN100584155 C CN 100584155C
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Abstract
The invention discloses a base plate processing of an embedded element, which comprises the steps: firstly, a core layer which comprises a first dielectric layer, a patterning line layer and a second patterning line layer is provided, wherein, the first patterning line layer and the second patterning line layer are respectively positioned on the upper surface and the lower surface of the first dielectric layer; secondly, a through hole is formed in the core layer; thirdly, the core layer is configured on a support plate and the embedded element is arranged in the through hole, wherein, the embedded element is provided with at least one electrode; and then glue pouring process is carried out to cause the embedded element to be fixed in the through hole; and then the support plate is removed; finally, the electrode of the embedded element is electrically connected with the second patterning line layer.
Description
Technical field
The invention relates to a kind of basal plate making process, and particularly relevant for a kind of basal plate making process of embedded element.
Background technology
Generally speaking, circuit base plate mainly be by multi-layered patterned line layer (patterned circuitlayer) and dielectric layer (dielectric layer) be superimposed constitute.Wherein, patterned line layer is to be formed through little shadow and etch process definition by copper foil layer (copper foil), and dielectric layer is disposed between the patterned line layer, in order to isolate two adjacent patterned line layer.In addition, between the adjacent patterned line layer be see through the conductive through hole run through dielectric layer (plating through hole, PTH) or conduction duct (conductive via) and being electrically connected to each other.At last, at the various electronic components of the surface configuration of circuit base plate (for example active member or passive device), and reach the purpose of electronic signal transmission (electrical signal propagation) by the circuit design of internal wiring.
Yet, along with market should have demand compact and easy to carry for electronic product, therefore in present electronic product, the electronic component that originally was welded in the circuit base plate surface is designed to be embedded in an embedded element of the inside of circuit base plate, can increase the wiring area on circuit base plate surface like this, to reach the electronic product purpose of thinness.
Figure 1A to Fig. 1 E is the making flow process generalized section of the basal plate making process of existing a kind of embedded element.At first, please refer to Figure 1A, a core layer 110 is provided, core layer 110 has one first dielectric layer 112, one first patterned line layer 114, and one second patterned line layer 116.First patterned line layer 114 and second patterned line layer 116 lay respectively at a upper surface 112a and a lower surface 112b of first dielectric layer 112.
Then, please refer to Figure 1B, form a perforation (through hole) H1 and an embedded element E is positioned among the perforation H1 in core layer 110, wherein embedded element E has two electrode E1.Then, please refer to Fig. 1 C, one first overlapping layers 120 and one second overlapping layers 130 are disposed at respectively on first patterned line layer 114 and second patterned line layer 116, wherein, first overlapping layers 120 comprises a first metal layer 122 and one second dielectric layer 124, second overlapping layers 130 comprises one second metal level 132 and one the 3rd dielectric layer 134, and second dielectric layer 124 and the 3rd dielectric layer 134 are respectively towards first patterned line layer 114 and second patterned line layer 116.
Moreover, please refer to Fig. 1 D, pressing first overlapping layers 120, core layer 110 and second overlapping layers 130, and form at least one conductive through hole H2 and a plurality of conductions duct V.Wherein, conductive through hole H2 runs through first overlapping layers 120, core layer 110 and second overlapping layers 130, makes the first metal layer 122 and second metal level 132 can see through conductive through hole H2 and is electrically connected to each other.In addition, the two electrode E1 of embedded element E can electrically connect with the first metal layer 122 and second metal level 132 respectively through these conductions duct V.
At last, please refer to Fig. 1 D and Fig. 1 E, the patterning the first metal layer 122 and second metal level 132, to form one first top layer circuit 122 ' and one second top layer circuit 132 ' respectively, and by conductive through hole H2 the electrically conduct first top layer circuit 122 ' and the second top layer circuit 132 ', and make the two electrode E1 of embedded element E electrically connect with the first top layer circuit 122 ' and the second top layer circuit 132 ' respectively by these conductions duct V.Finish the making flow process of the basal plate making process of embedded element in this way.
Yet, embedded element E in the basal plate making process of existing embedded element must conduct electricity duct V and be electrically connected to the first top layer circuit 122 ' and the second top layer circuit 132 ' via these, can reduce the wiring area of first patterned line layer 114 and second patterned line layer 116 like this, and then reduce the wiring density of first patterned line layer 114 and second patterned line layer 116.In addition, embedded element E need see through the conduction duct V and the first top layer circuit 122 ' and the second top layer circuit 132 ' and electrically connect, yet this mode will increase the thickness of whole circuit base plate, and can't meet compact product design requirement.Therefore the basal plate making process of existing embedded element has improved necessity in fact.
Summary of the invention
Main purpose of the present invention is to provide a kind of basal plate making process of embedded element, promoting the wiring density of first patterned line layer, second patterned line layer, the first top layer circuit and the second top layer circuit, and can reduce the thickness of whole base plate effectively.
For reaching above-mentioned purpose or other purpose, the present invention adopts following technical scheme: a kind of basal plate making process of embedded element, it comprises the following steps: that step (a) provides a core layer, described core layer has one first dielectric layer, one first patterned line layer and one second patterned line layer, and described first patterned line layer and described second patterned line layer lay respectively at a upper surface and a lower surface of described first dielectric layer; Step (b) is to form a perforation in described core layer; It is characterized in that: described basal plate making process also includes the following step: step (c) is that described core layer is configured on the supporting bracket, and an embedded element is seated in the described perforation, and wherein said embedded element has at least one electrode; Step (d) is to carry out an encapsulating processing procedure, and described embedded element is fixed in the described perforation; Step (e) is to remove described supporting bracket; And step (f) is described electrode and described second patterned line layer that electrically connects described embedded element.
In one embodiment of this invention, the above-mentioned step (a) of core layer that provides comprises: utilize little shadow and etch process respectively patterning be positioned at the upper surface of first dielectric layer and a first metal layer and one second metal level of lower surface, on the upper surface of first dielectric layer and lower surface, to form first patterned line layer and second patterned line layer.
In one embodiment of this invention, the above-mentioned step (a) of core layer that provides comprises: utilize little shadow and etch process respectively patterning be positioned at the upper surface of first dielectric layer and a first metal layer and one second metal level of lower surface, on the upper surface of first dielectric layer and lower surface, to form first patterned line layer and second patterned line layer.In addition, the material of the first metal layer and second metal level comprises copper.
In one embodiment of this invention, the mode of above-mentioned formation perforation comprises machine drilling or laser pore-forming.
In one embodiment of this invention, above-mentioned supporting bracket can be a glass plate or a poly-terephthalic acids vinyl acetate film (PET film).
In one embodiment of this invention, above-mentioned embedded element comprises active member and passive device.
In one embodiment of this invention, above-mentioned encapsulating processing procedure for example is that an adhesive agent is filled in the gap between embedded element and the perforation.
In one embodiment of this invention, the step of the electrode of above-mentioned electric connection embedded element and second patterned line layer (f) includes following steps: at first, configuration one shielding on second patterned line layer, shielding exposes electrode and part second patterned line layer; Then, form a metal level at the lower surface of first dielectric layer, wherein the part metals layer is to electrically connect the electrode and second patterned line layer; Follow again, remove shielding.
In one embodiment of this invention, the step of the electrode of above-mentioned electric connection embedded element and second patterned line layer (f) includes following steps: at first, configuration one shielding on second patterned line layer, shielding exposes electrode and part second patterned line layer; Then, form a metal level at the lower surface of first dielectric layer, wherein the part metals layer is to electrically connect the electrode and second patterned line layer; Follow again, remove shielding.In addition, the method for formation metal level comprises plating, electroless plating, physical vaporous deposition or chemical vapour deposition technique.
In one embodiment of this invention, the step of the electrode of above-mentioned electric connection embedded element and second patterned line layer (f) may further comprise the steps: at first, configuration one shielding on second patterned line layer, shielding exposes electrode and part second patterned line layer.Then, form a metal level at the lower surface of first dielectric layer, wherein the part metals layer is to electrically connect the electrode and second patterned line layer.Moreover, remove shielding.In addition, the method for formation metal level can be the lower surface coating one deck conducting resinl at first dielectric layer.
In one embodiment of this invention, when the electrode of above-mentioned electric connection embedded element and second patterned line layer, can electrically connect the electrode and first patterned line layer of embedded element simultaneously.
In one embodiment of this invention, after the electrode and second patterned line layer of above-mentioned electric connection embedded element, more may further comprise the steps: at first, one first overlapping layers and one second overlapping layers are disposed at respectively on first patterned line layer and second patterned line layer, wherein first overlapping layers comprises one the 3rd metal level and one second dielectric layer, second overlapping layers comprises one the 4th metal level and one the 3rd dielectric layer, and second dielectric layer and the 3rd dielectric layer are respectively towards first patterned line layer and second patterned line layer; Then, pressing first overlapping layers, core layer and second overlapping layers; Follow again, between first overlapping layers, core layer and second overlapping layers, form at least one conductive through hole; Follow again, patterning the 3rd metal level and the 4th metal level, forming one first top layer circuit and one second top layer circuit respectively, and by the conductive through hole conducting first top layer circuit and the second top layer circuit.
In one embodiment of this invention, after the electrode and second patterned line layer of above-mentioned electric connection embedded element, more may further comprise the steps: at first, one first overlapping layers and one second overlapping layers are disposed at respectively on first patterned line layer and second patterned line layer, wherein first overlapping layers comprises one the 3rd metal level and one second dielectric layer, second overlapping layers comprises one the 4th metal level and one the 3rd dielectric layer, and second dielectric layer and the 3rd dielectric layer are respectively towards first patterned line layer and second patterned line layer; Then, pressing first overlapping layers, core layer and second overlapping layers; Follow again, between first overlapping layers, core layer and second overlapping layers, form at least one conductive through hole.Follow again, patterning the 3rd metal level and the 4th metal level, forming one first top layer circuit and one second top layer circuit respectively, and by the conductive through hole conducting first top layer circuit and the second top layer circuit.In addition, form after the first top layer circuit and the second top layer circuit, more may further comprise the steps: at first, on second dielectric layer and the 3rd dielectric layer, form one first welding cover layer and one second welding cover layer respectively, wherein first welding cover layer exposes to the small part first top layer circuit, and second welding cover layer exposes to the small part second top layer circuit; Then, to the small part first top layer circuit, formed one first anti oxidation layer, and to the small part second top layer circuit, formed one second anti oxidation layer what second welding cover layer exposed what first welding cover layer exposed.
In one embodiment of this invention, after the electrode and second patterned line layer of above-mentioned electric connection embedded element, more may further comprise the steps: at first, one first overlapping layers and one second overlapping layers are configured in respectively on first patterned line layer and second patterned line layer, wherein first overlapping layers comprises one the 3rd metal level and one second dielectric layer, second overlapping layers comprises one the 4th metal level and one the 3rd dielectric layer, and second dielectric layer and the 3rd dielectric layer are respectively towards first patterned line layer and second patterned line layer; Then, pressing first overlapping layers, core layer and second overlapping layers; Follow again, between first overlapping layers, core layer and second overlapping layers, form at least one conductive through hole; Follow again, patterning the 3rd metal level and the 4th metal level, forming one first top layer circuit and one second top layer circuit respectively, and by the conductive through hole conducting first top layer circuit and the second top layer circuit.In addition, form after the first top layer circuit and the second top layer circuit, more may further comprise the steps: at first, on second dielectric layer and the 3rd dielectric layer, form one first welding cover layer and one second welding cover layer respectively, wherein first welding cover layer exposes to the small part first top layer circuit, and second welding cover layer exposes to the small part second top layer circuit; Then, to the small part first top layer circuit, formed one first anti oxidation layer, and to the small part second top layer circuit, formed one second anti oxidation layer what second welding cover layer exposed what first welding cover layer exposed.In addition, the method that forms first anti oxidation layer and second anti oxidation layer comprises respectively and is electroplated nickel or gold layer what first welding cover layer exposed to the small part second top layer circuit to the small part first top layer circuit and what second welding cover layer was exposed.
In one embodiment of this invention, after the above-mentioned formation first top layer circuit and the second top layer circuit, more may further comprise the steps: at first, on the first top layer circuit and the second top layer circuit, form one first anti oxidation layer of patterning and one second anti oxidation layer of patterning respectively; Then, form one first welding cover layer and one second welding cover layer on second dielectric layer and the 3rd dielectric layer respectively, wherein first welding cover layer covers the first top layer circuit, and exposes first anti oxidation layer, and second welding cover layer covers the second top layer circuit, and exposes second anti oxidation layer.
Compared to prior art, in the basal plate making process of embedded element of the present invention, the electrode of embedded element directly is electrically connected to first patterned line layer or second patterned line layer of internal layer, therefore, the wiring density of first patterned line layer, second patterned line layer, the first top layer circuit and the second top layer circuit can be promoted, and the reliability of the electric connection of embedded element and first patterned line layer or second patterned line layer can be improved.In addition, the patterned line layer of direct and internal layer electrically connects because embedded element need not see through existing conductive through hole, therefore, can effectively reduce the thickness of whole base plate, make the electronic product of using this substrate can meet compact product design requirement.
Description of drawings
Figure 1A to Fig. 1 E is the making flow process generalized section of the basal plate making process of existing a kind of embedded element.
Fig. 2 A to Fig. 2 J is the making flow process generalized section of basal plate making process of a kind of embedded element of one embodiment of the invention.
Fig. 3 A to Fig. 3 C is the electrode of electric connection embedded element and the making flow process generalized section of second patterned line layer.
Fig. 4 is the making flow process generalized section of the formation welding cover layer and the anti oxidation layer of another embodiment of the present invention.
Embodiment
In order to make above-mentioned purpose of the present invention and other purpose, feature and advantage become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Fig. 2 A to Fig. 2 J is the making flow process generalized section of basal plate making process of a kind of embedded element of one embodiment of the invention.At first, please refer to Fig. 2 A, a core layer 210 is provided, core layer 210 has one first dielectric layer 212, one first patterned line layer 214 and one second patterned line layer 216.First patterned line layer 214 and second patterned line layer 216 lay respectively at a upper surface 212a and a lower surface 212b of first dielectric layer 212.In the present embodiment, provide the step of core layer 210 to comprise to utilize little shadow and etch process respectively patterning to be positioned at the first metal layer of the upper surface 212a of first dielectric layer 212 and lower surface 212b (not shown, its material can be copper) (not shown with one second metal level, its material can be copper), on the upper surface 212a of first dielectric layer 212 and lower surface 212b, to form first patterned line layer 214 and second patterned line layer 216 respectively.
Then, please refer to Fig. 2 B, in core layer 210, form a perforation H3, and perforation H3 can utilize machine drilling, laser pore-forming or alternate manner to form.Then, please refer to Fig. 2 C, core layer 210 is disposed on the supporting bracket S, and an embedded element E ' is placed among the perforation H3, wherein embedded element E ' has at least one electrode E1 ' (being provided with two electrode E1 ' in Fig. 2 C).In the present embodiment, supporting bracket S can be the plate that a glass plate, poly-terephthalic acids vinyl acetate film or other material are constituted; In addition, embedded element E ' comprises active member (for example being thin-film transistor) and passive device (for example being resistance, electric capacity or inductance).It should be noted that because embedded element E ' is supported by supporting bracket S with second patterned line layer 216, so embedded element E ' approximately is positioned on the same plane of supporting bracket S with second patterned conductive layer 216.
Come again, please refer to Fig. 2 D, carry out an encapsulating processing procedure, embedded element E ' is fixed among the perforation H3.In the present embodiment, this encapsulating processing procedure is that an adhesive agent A is filled in the gap between embedded element E ' and the perforation H3, and with its curing, embedded element E ' is fixed among the perforation H3 of core layer 210.In addition, adhesive agent A can be thermosetting resin (thermal setting resin) or ultraviolet curing type resin, with respectively by heating or in the mode of ultraviolet irradiation with its curing (curing).Afterwards, please refer to Fig. 2 E, remove supporting bracket S.
Next, please continue 2E, electrically connect the electrode E1 ' and second patterned line layer 216 of embedded element E ' with reference to figure.Finish the basal plate making process of basic embedded element in this way.
Below collocation is illustrated the electrode E1 ' of wherein a kind of electric connection embedded element E ' and the manufacture method of second patterned line layer 216, yet, the user also can make the electrode E1 ' of embedded element E ' constitute with second patterned line layer 216 by alternate manner and electrically connect, and the present invention does not impose any restrictions this.Fig. 3 A to Fig. 3 C is the electrode of electric connection embedded element and the making flow process generalized section of second patterned line layer.Particularly, at first, please refer to Fig. 3 A, configuration one shielding M on second patterned line layer 216, shielding M exposes electrode E1 ' and part second patterned line layer 216.Then, please refer to Fig. 3 B, form a metal level L at the lower surface 212b of first dielectric layer 212, wherein part metals layer L electrically connects the electrode E1 ' and second patterned line layer 216.The method that forms metal level L comprises plating, electroless plating, physical vaporous deposition, chemical vapour deposition technique, or also can at the lower surface 212b of first dielectric layer 212 coating one deck conducting resinl.Moreover, please refer to Fig. 3 B and Fig. 3 C, remove shielding M, in this way, the electrode E1 ' of embedded element E ' can see through metal level L and second patterned line layer 216 constitutes electric connection.In this mandatory declaration is, can electrically connect the electrode E1 ' and first patterned line layer 214 of embedded element E ' simultaneously, but not illustrate with drawing at this during with second patterned line layer 216 at the electrode E1 ' of above-mentioned electric connection embedded element E '.
And after the step of the electrode E1 ' that finishes the electric connection embedded element E ' that Fig. 2 E illustrated and second patterned line layer 216, more can utilize following dual mode to form top layer circuit, welding cover layer and anti oxidation layer, so that substrate becomes the substrate with double-deck line layer on the surface of substrate both sides.
Fig. 2 F to 2J is for to retain plating line in advance, to form the making flow process profile of top layer circuit, welding cover layer and anti oxidation layer in regular turn on the surface of substrate on substrate.At first, please refer to Fig. 2 F, one first overlapping layers 220 and one second overlapping layers 230 are disposed at respectively on first patterned line layer 214 and second patterned line layer 216.Wherein first overlapping layers 220 comprises one the 3rd metal level 222 and one second dielectric layer 224, second overlapping layers 230 comprises one the 4th metal level 232 and one the 3rd dielectric layer 234, and second dielectric layer 224 and the 3rd dielectric layer 234 are respectively towards first patterned line layer 214 and second patterned line layer 216, in other words, second dielectric layer 224 is between the 3rd metal level 222 and first patterned line layer 214, and the 3rd dielectric layer 234 is between the 4th metal level 232 and second patterned line layer 216.
Then, please refer to Fig. 2 G, pressing first overlapping layers 220, core layer 210 and second overlapping layers 230, so that first patterned line layer 214 and second patterned line layer 216 embed second dielectric layer 224 and the 3rd dielectric layer 234 respectively, and the 3rd metal level 222 and the 4th metal level 232 are disposed on second dielectric layer 224 and the 3rd dielectric layer 234 respectively.
Come, please refer to Fig. 2 H, form at least one conductive through hole H4 between first overlapping layers 220, core layer 210 and second overlapping layers 230, in other words, conductive through hole H4 runs through first overlapping layers 220, core layer 210 and second overlapping layers 230.The generation type of conductive through hole H4 be for example earlier with machine drilling or laser pore-forming mode form a through hole, again around this through hole sidewall or inner plated with copper metal to form conductive through hole H4.
Moreover, please refer to Fig. 2 H and Fig. 2 I, come patterning the 3rd metal level 222 and the 4th metal level 232 by for example little shadow and etch process, forming one first top layer circuit 222 ' and one second top layer circuit 232 ' respectively, and the first top layer circuit 222 ' and the second top layer circuit 232 ' are to electrically conduct by conductive through hole H4.
Afterwards, please refer to Fig. 2 J, on second dielectric layer 224 and the 3rd dielectric layer 234, form one first welding cover layer 240 and one second welding cover layer 250 respectively, wherein first welding cover layer 240 exposes to the small part first top layer circuit 222 ', and second welding cover layer 250 exposes to the small part second top layer circuit 232 '.In this mandatory declaration be; first welding cover layer 240 and second welding cover layer 250 are respectively in order to protect the first top layer circuit 222 ' and the second top layer circuit 232 '; and the part second top layer circuit 232 ' that the part first top layer circuit 222 ' that first welding cover layer 240 is exposed and second welding cover layer 250 are exposed for example can be used as electrical connection pad (electrical pad), and it is in order to the contact as electric connection external electronic or element.
Then, form one first anti oxidation layer 260, and form one second anti oxidation layer 270 going up of being exposed of second welding cover layer 250 to the small part second top layer circuit 232 ' going up of being exposed of first welding cover layer 240 to the small part first top layer circuit 222 '.The material of first anti oxidation layer 260 and second anti oxidation layer 270 can be the electric conducting material that is difficult for oxidation, for example be nickel or gold, it can adopt the mode of plating to form, and the part first top layer circuit 222 ' that is exposed to avoid and the second top layer circuit 232 ' are because of ingress of air and aqueous vapor oxidation.
In another embodiment of the present invention, the step of above-mentioned formation welding cover layer that is illustrated with Fig. 2 J and anti oxidation layer can be done the change of sequence of steps.Please refer to Fig. 2 I and Fig. 4, wherein Fig. 4 is the making flow process generalized section of the formation welding cover layer and the anti oxidation layer of another embodiment of the present invention.Forming the first top layer circuit 222 ' shown in Fig. 2 I and the second top layer circuit 232 ' afterwards, can may further comprise the steps.At first, for example on the first top layer circuit 222 ' and the second top layer circuit 232 ', form one first anti oxidation layer 260 ' of patterning and one second anti oxidation layer 270 ' of patterning respectively with little shadow and etched processing procedure.
Then, on second dielectric layer 224 and the 3rd dielectric layer 234, form one first welding cover layer 240 ' and one second welding cover layer 250 ' respectively, wherein first welding cover layer 240 ' covers the first top layer circuit 222 ', and expose first anti oxidation layer 260 ', and second welding cover layer 250 ' covers the second top layer circuit 232 ', and exposes second anti oxidation layer 270 '.In the present embodiment, the function of first welding cover layer 240 ' and second welding cover layer 250 ' is as above-mentioned first welding cover layer 240 and second welding cover layer 250 (please refer to Fig. 2 J), the material of first anti oxidation layer 260 ' and second anti oxidation layer 270 ', generation type and function are then as above-mentioned first anti oxidation layer 260 and second anti oxidation layer 270 (please refer to Fig. 2 J), so just no longer be described in detail at this.
In sum, the basal plate making process of embedded element of the present invention has following advantages at least:
(1) because in the basal plate making process of embedded element of the present invention, the electrode of embedded element electrically connects Be connected to first patterned line layer or second patterned line layer of internal layer, therefore can promote first pattern Change the wiring density of line layer, second patterned line layer, the first top layer circuit and the second top layer circuit, And improve embedded element and first patterned line layer or second patterned line layer electric connection can By degree;
(2) because embedded element need not see through existing conductive through hole and first pattern of direct and internal layer Change line layer or second patterned line layer and be electrically connected, therefore can effectively reduce the thickness of whole substrate, Can meet compact product design requirement so that use the electronic product of this substrate;
(3) because in the basal plate making process of embedded element of the present invention, the electrode of embedded element electrically connects Be connected to first patterned line layer or second patterned line layer of internal layer, therefore can reduce embedded element Electrode and first patterned line layer or second patterned line layer between the cross-talk effect of transmission electrical signals Answer (cross-talk effect), and then promote its electrical performance (electrical performance);
(4) because in the basal plate making process of embedded element of the present invention, the electrode of embedded element is not with shape Become the mode in conduction duct and be electrically connected to first patterned line layer or second patterned circuit of internal layer Layer, therefore the manufacturing cost of the basal plate making process of embedded element of the present invention is lower.
Claims (11)
1. the basal plate making process of an embedded element, comprise the following steps: that step (a) provides a core layer, described core layer has one first dielectric layer, one first patterned line layer and one second patterned line layer, and described first patterned line layer and described second patterned line layer lay respectively at a upper surface and a lower surface of described first dielectric layer; Step (b) is to form a perforation in described core layer; It is characterized in that: described basal plate making process also includes the following step (c) to (f), and wherein step (c) is that described core layer is configured on the supporting bracket, and an embedded element is seated in the described perforation, and wherein said embedded element has at least one electrode; Step (d) is to carry out an encapsulating processing procedure, and described embedded element is fixed in the described perforation; Step (e) is to remove described supporting bracket; And step (f) is described electrode and described second patterned line layer that electrically connects described embedded element.
2. the basal plate making process of embedded element as claimed in claim 1, it is characterized in that: provide the described step (a) of described core layer to comprise: utilize little shadow and etch process respectively patterning be positioned at the described upper surface of described first dielectric layer and a first metal layer and one second metal level of described lower surface, on the described upper surface of described first dielectric layer and described lower surface, to form described first patterned line layer and described second patterned line layer.
3. the basal plate making process of embedded element as claimed in claim 1 is characterized in that: described encapsulating processing procedure is that an adhesive agent is filled in the gap between described embedded element and the described perforation.
4. the basal plate making process of embedded element as claimed in claim 1 is characterized in that: include following steps in the described step (f) of described electrode that electrically connects described embedded element and described second patterned line layer:
Configuration one shielding on described second patterned line layer, described shielding is to expose described electrode and part second patterned line layer;
Described lower surface at described first dielectric layer forms a metal level, and wherein the part metals layer is to electrically connect described electrode and described second patterned line layer; And
Remove described shielding.
5. the basal plate making process of embedded element as claimed in claim 4, it is characterized in that: the method that forms described metal level comprises plating, electroless plating, physical vaporous deposition or chemical vapour deposition technique.
6. the basal plate making process of embedded element as claimed in claim 4 is characterized in that: the method that forms described metal level is the described lower surface coating one deck conducting resinl at described first dielectric layer.
7. the basal plate making process of embedded element as claimed in claim 1, it is characterized in that: when described electrode that electrically connects described embedded element and described second patterned line layer, electrically connect the described electrode and described first patterned line layer of described embedded element simultaneously.
8. the basal plate making process of embedded element as claimed in claim 1 is characterized in that: in the described step (f) of described electrode that electrically connects described embedded element and described second patterned line layer afterwards, more include following steps:
One first overlapping layers and one second overlapping layers are configured in respectively on described first patterned line layer and described second patterned line layer, wherein, described first overlapping layers comprises one the 3rd metal level and one second dielectric layer, described second overlapping layers comprises one the 4th metal level and one the 3rd dielectric layer, and described second dielectric layer and described the 3rd dielectric layer are respectively towards described first patterned line layer and described second patterned line layer;
Described first overlapping layers of pressing, described core layer and described second overlapping layers;
Between described first overlapping layers, described core layer and described second overlapping layers, form at least one conductive through hole; And
Described the 3rd metal level of patterning and described the 4th metal level, forming one first top layer circuit and one second top layer circuit respectively, and by described first top layer circuit of described conductive through hole conducting and the described second top layer circuit.
9. the basal plate making process of embedded element as claimed in claim 8 is characterized in that: after forming described first top layer circuit and the described second top layer circuit, more include following steps:
Form one first welding cover layer and one second welding cover layer on described second dielectric layer and described the 3rd dielectric layer respectively, wherein said first welding cover layer exposes to the small part first top layer circuit, and described second welding cover layer exposes to the small part second top layer circuit; And
To the small part first top layer circuit, formed one first anti oxidation layer what described first welding cover layer exposed, and to the small part second top layer circuit, formed one second anti oxidation layer what described second welding cover layer exposed.
10. the basal plate making process of embedded element as claimed in claim 9 is characterized in that: the method that forms described first anti oxidation layer and described second anti oxidation layer comprise respectively described first welding cover layer exposed to the small part first top layer circuit and described second welding cover layer exposed to the small part second top layer circuit, electroplate nickel or gold layer.
11. the basal plate making process of embedded element as claimed in claim 8 is characterized in that: after forming described first top layer circuit and the described second top layer circuit, more include following steps:
On described first top layer circuit and the described second top layer circuit, form one first anti oxidation layer of patterning and one second anti oxidation layer of patterning respectively; And
On described second dielectric layer and described the 3rd dielectric layer, form one first welding cover layer and one second welding cover layer respectively, wherein said first welding cover layer covers the described first top layer circuit, and expose described first anti oxidation layer, and described second welding cover layer covers the described second top layer circuit, and exposes described second anti oxidation layer.
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| CN200710100549A CN100584155C (en) | 2007-04-10 | 2007-04-10 | Manufacture process for substrate of internally embedded element |
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| CN106376170A (en) * | 2015-07-24 | 2017-02-01 | 宏启胜精密电子(秦皇岛)有限公司 | Flexible circuit board, manufacturing method thereof, and electronic device |
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