CN103632985A - 制造裸片的金属垫片结构的方法、裸片配置和芯片配置 - Google Patents

制造裸片的金属垫片结构的方法、裸片配置和芯片配置 Download PDF

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CN103632985A
CN103632985A CN201310368205.0A CN201310368205A CN103632985A CN 103632985 A CN103632985 A CN 103632985A CN 201310368205 A CN201310368205 A CN 201310368205A CN 103632985 A CN103632985 A CN 103632985A
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encapsulating material
gap
electrically conducting
conducting contact
metallic gasket
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CN103632985B (zh
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约翰·加特鲍尔
约尔格·布施
伯恩哈德·韦德甘斯
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

本发明提供了制造裸片的金属垫片结构的方法、裸片配置和芯片配置。一种用来制造裸片的金属垫片结构的方法，所述方法包括：在裸片的封装材料之间形成金属垫片，其中，所述金属垫片和所述封装材料被间隙彼此分隔开；以及在间隙中形成额外的材料以使间隙的至少一部分变窄。

Description

制造裸片的金属垫片结构的方法、裸片配置和芯片配置
技术领域
各种实施方式通常涉及用于制造裸片（die）的金属垫片结构的方法、用于制造芯片焊垫的方法以及裸片配置和芯片配置。
背景技术
传统地，将铝（Al）上焊接金（Au）垫片已经被用作互连。铝垫片金属化具有良好的自钝化性质。然而，关于高温需求（例如，温度大于150℃），例如，就可靠性而言，由于诸如金属相形成和Kirkendall空隙而导致对金的界面受到限制。半导体工业主要通过采用两个途径来克服这些可靠性限制并避免因选择实施Au垫片金属化的昂贵花费。
第一，可将铜（Cu）线应用在Al垫上从而如果可控制配线焊接工艺的机械冲击，可显著增加使用期限。
第二，例如，可通过例如镍-磷（NiP）或者钯（Pd）或者金（Au）的无电电镀沉积执行垫片增强片上金属化（pad enforcement over padmetallization，OPM）。如图1所示，例如钯OPM的OPM102可以例如涂覆在例如Al垫片的金属垫片104上。OPM102可为Au配线形成可靠的界面但也可用于铝或铜互连。用作垫片抛光的可选的Au焊瘤（Au-flash）可提高垫片的抗氧化能力。用于OPM的无电电镀的好处是可以仅在垫片金属化层104（例如，再分布层（redistribution layer，EDL））上进行金属的生长。因为不存在与诸如聚酰亚胺或者钝化层的绝缘材料106的反应，因此，不存在OPM对侧壁108的粘附。在电镀后（例如：无电电镀）沿侧壁处会有无穷小的间隙112，所述无穷小间隙112是可以接受的。然而，例如，在数据保持烘烤过程中，当施加热处理时，无定形沉积NiP层可在大约350℃下结晶并可引起NiP层（即，OPM层）的收缩和/或酰亚胺形状的改变，这将扩大侧壁处的间隙。扩大的更宽的间隙112为后续工艺步骤打开通路，诸如，可能接触金属垫片（例如Al垫片和NiP层）的界面的Au焊瘤。随后的这些接触面可被作为OPM和酰亚胺/钝化层之间的间隙而被攻击。因此，对于打开的腔封装，例如，用于绝缘芯片的封装工艺，芯片可被诸如封装材料的凝胶覆盖，并且间隙会导致在危险环境下的侵蚀。如图2和图3示出了可选的OPM装置。
发明内容
各种实施方式提供了用于制造裸片的金属垫片结构的方法，所述方法包括：在裸片的封装材料之间形成金属垫片，其中，所述金属垫片和封装材料被间隙彼此分开；以及在所述间隙中形成额外的材料于以使所述间隙的至少一部分变窄。
附图说明
在附图中，不同示图中的相似参考符号一般表示相同部分。附图没必要按比例绘制，而是将重点放在阐明本发明的原理上。在以下描述中，参考以下附图描述本发明各种实施方式，在附图中：
图1示出了使用比例酰亚胺工艺制造的裸片的金属垫片；
图2示出了使用非比例酰亚胺工艺制造的裸片的金属垫片；
图3示出了使用预涂层（ProCoat）工艺制造的裸片的金属垫片；
图4示出了根据实施方式的用于制造裸片的金属垫片结构的方法；
图5A至图5F示出了根据实施方式的用于制造裸片的金属垫片结构的方法；
图6示出了根据实施方式的用于制造芯片的焊垫的方法。
图7示出了根据实施方式的裸片配置。
具体实施方式
以下具体描述参考以示例的方式示出特定细节的附图和其中可以实践本发明的实施方式。
此处使用的词“示例性”意指“用作实例、例证或者示例”。此处描述的任何实施方式或者设计作为“示例性的”，没必要解释成比其他的实施方式或设计更优选或有优势的。
关于在侧面或表面“上”形成沉积材料的词语“上”，此处可用作表示沉积材料可“直接”形成于所述侧面或表面“上”，例如，与所指的侧面或表面直接接触。关于在侧面或表面“上”形成沉积材料的词语“上”，此处可用作表示沉积材料可“间接”形成于所指侧面或表面“上”，一层或多层附加层设置在所指侧面或表面与沉积材料之间。
各种实施方式提供一种用于封闭间隙，例如，形成在金属垫片结构和隔离体之间的间隙的方法。根据各种实施方式的方法可避免额外的光刻层和/或步骤。
图4示出了用于制造裸片的金属垫片结构的方法。方法400可包括：
在裸片的封装材料之间形成金属垫片，其中，金属垫片和封装材料被间隙彼此分开（410中）；以及
在间隙中形成额外的材料使间隙（420中）的至少一部分变窄。
图5示出了用于制造裸片的金属垫片结构的方法500。
在方法500的工艺510中，钝化材料514可沉积在包含导电接触部504的裸片516上。裸片516可包含半导体芯片，例如，包含集成电路的半导体芯片，例如，包含一个或多个传感器，例如，一个或多个控制器，例如，一个或多个晶体管。裸片516可包含半导体芯片，所述半导体芯片可包含形成在晶片基板的至少一部分上和/或内的电子部件。晶片基板可包含各种材料，例如，半导体材料。晶片基板可包含来自以下材料组中的至少一种材料，所述材料组由以下材料组成：硅、诸、III至V族材料、聚合体、掺杂或不掺杂硅、绝缘体上硅（SOI）晶片、半导体化合物材料，例如，砷化镓（GaAs），例如，磷化铟（InP），四元半导体化合物材料，例如，砷化铟镓（InGaAs）。
导电接触部504可称为导电接触垫片，并且可形成于例如裸片516的正面524或者背面（未示出）上。正面524可理解为指裸片的通常可以承载一个或多个接触垫片、或电接触部（其中，可以附接垫片或电连接）的一侧；或者其中，其为芯片的例如相对于逻辑装置大部分由金属化层覆盖的一侧。导电接触部504可电连接至形成在裸片516内的一个或多个电路和/或组件，并可用于提供外接垫片（例如，在裸片正面或者后侧），用来提供电力以电激活电路。例如，导电接触部504可通过有线连接（例如，电连接和/或粘接至导电接触部504的焊接配线）电连接至另一个裸片和/或电路板。导电接触部504可包含至少一种来自以下材料组的材料、元件或者合金，所述组由以下材料组成：铜、铝、银、锡、金、钯、锌、镍、铁。导电接触部504可包括裸片的导电性再分布层（conductive redistributionlayer）的至少一部分。导电接触部504可包含裸片的导电性再分布层。
钝化材料514可包含来自以下材料组中的至少一种材料，所述组由以下材料组成：氧化硅（SiO）、二氧化硅（SiO2）、氮化硅（Si3N4）、碳化硅（SiC）。可通过来自以下沉积方法组中至少一种方法沉积钝化材料514，所述方法组由以下方法组成：气相沉积、蒸发、溅射、化学气相沉积。钝化材料514可具有从大约40nm至大约1000nm范围，例如，从大约50nm至大约800nm范围，例如，从大约100nm至大约500nm范围的厚度。钝化材料514可形成在导电接触部504的顶面以及导电接触部的一个或多个侧壁上。换言之，钝化材料514可基本上覆盖导电接触部。
在方法500的工艺520中，封装材料506可沉积在钝化材料514上。封装材料506可包括来自以下材料组的至少一种材料，所述材料组由以下材料组成：聚酰亚胺、环氧树脂、聚合体、二氧化硅、氮化硅。可选择封装材料506（例如，原聚酰亚胺）从而其可以提供合适的芯片表面和/或合适的芯片封装表面以满足封装相关要求，例如，对复合模的良好的粘结性。封装材料506可以具有从大约5μm至大约15μm的范围内的厚度。
在方法500的工艺530中，可选择性地去除钝化材料514和封装材料506的部分518，从而使得导电接触部504的部分522上可没有钝化材料514和封装材料506。换言之，可在封装材料506和钝化材料514中形成暴露导电接触部504的至少一部分的开口。
在钝化材料514未沉积在裸片516上的情况下，封装材料506例如可直接沉积在裸片516的导电接触部504上，且导电接触部504的至少一部分通过在封装材料506中形成的开口被暴露和/或没有封装材料506。换言之，封装材料506可沉积在裸片516的导电部上，例如，导电性再分布层上；以及导电接触部504的至少一部分522通过在封装材料506中形成开口可以被暴露和/或没有封装材料506。导电接触部504的部分522上可没有封装材料506和/或钝化材料514，而导电接触部504的其他部分523可被封装材料506和/或钝化材料514覆盖。导电接触部504的部分522可具有大约2μm至大约1000μm的范围内的长度。
封装材料506可分别通过光刻和显影工艺去除。
在单独工艺中使用化学蚀刻和/或等离子体蚀刻或通过单独的光刻或者通过使用封装材料506的结构可选择地蚀刻钝化材料514。根据其他实施方式，可利用诸如氟或者氯的化学反应去除钝化材料506。
在方法500的工艺540中，金属垫片502可形成在导电接触部504的部分522（导电部）上，所述部分522上可没有钝化材料514和封装材料506。换言之，金属垫片502可形成在由于钝化材料514和封装材料506的选择性去除而被暴露的部分522上。可通过在钝化材料514和封装材料506内和/或通过钝化材料514和封装材料506形成开口进行钝化材料514和封装材料506的选择性的去除。金属垫片502可具有大约200nm至大约20μm，例如，从大约500nm至大约10μm，例如，从大约1μm至大约5μm的范围内的厚度。金属垫片502可包含在垫片上金属化金属（overpad metallization，OPM）层。
金属垫片502可形成于封装材料506之间的导电接触部504的部分522上。金属垫片502可形成在裸片516的封装材料506之间，其中，金属垫片502和封装材料506可被间隙512彼此分隔开。间隙512可包含一个或多个间隙512，它们为金属垫片502和封装材料506之间的间隔。在裸片516的封装材料506之间形成金属垫片502包括通过以下沉积方法组中至少一种沉积方法在裸片516的封装材料506之间沉积金属垫片502，所述组由以下方法组成：无电电镀、电镀、电沉积、溅射、蒸发。例如，封装材料506可用作金属垫片502（OPM）的掩模，例如，用于OPM502的电镀掩模。换言之，金属垫片502可根据封装材料的侧壁508的轮廓线形成。然而，金属垫片502可以不电镀在侧壁508上。
金属垫片502和封装材料506可被间隙512彼此分隔开，例如，从大约在10nm至500nm，例如，大约15nm至大约400nm，例如，大约20nm至大约300nm的范围内的间隔。
方法500因此可包括：在包括导电接触部504的裸片516上沉积封装材料506；选择性地去除封装材料506的一部分以暴露导电接触部504的部分522；以及在导电接触部504的部分522上形成金属垫片502。
在方法500的工艺550中，在间隙512中可形成额外的材料526以使间隙512的至少一部分变窄。在间隙512中形成额外的材料526以使间隙512的至少一部分变窄可包括在间隙512中形成导电材料。额外的材料526可包含来自导电材料组中的至少一种导电材料，所述导电材料组由钯、银、铂、金构成。额外的材料526可包含贵金属。根据其他实施方式，在间隙512中形成额外的材料526以使分间隙512的至少一部变窄可包括在间隙中形成电绝缘材料。额外的材料526可包含来自电绝缘材料组中的至少一种电绝缘材料，电绝缘材料组由环氧树脂、有机聚合物、无机聚合物、聚酰亚胺以及碳基材料构成。可考虑到相对于封装材料506和金属垫片502的热膨胀系数（CTE）来选择额外的材料526。额外的材料526可包含薄绝缘层，例如，电隔离和/或热传导层，可粘附至封装材料506（例如，聚酰亚胺（酰亚胺））和金属垫片502。因此，间隙512可变窄或闭合。换言之，额外的材料526可在间隙512内形成插塞或者阻塞部，从而使得导电接触部504可以免于外部的侵袭，例如，化学腐蚀。
在间隙512中形成额外的材料526可包括通过来自以下沉积方法组中的至少一种沉积方法在间隙512中形成额外的材料526，所述组包括：喷射、气相沉积、旋涂、浸涂、化学气相沉积、等离子体增强化学气相沉积、原子层沉积、无电电镀以及电镀。额外的材料526可包含液体或蒸气。由于将额外的材料526吸引至间隙512的毛细管效应，额外的材料526可形成于间隙512中。在间隙512中形成额外的材料526以使间隙512的至少一部分变窄可包括用额外的材料526至少部分地填充间隙。在间隙512中形成额外的材料526以使间隙512的至少部分变窄可包括将额外的材料526粘附至封装材料506的一个或多个侧壁508上和/或金属垫片502的一个或多个侧壁507上。在间隙512中形成额外的材料526以使间隙512的至少一部分变窄可包括将额外的材料526粘附至封装材料506的部分侧壁508上和/或金属垫片502的部分侧壁507上。此外，在间隙512中形成额外的材料526以使间隙512的至少一部分变窄可包含在导电接触部504的至少一部分部分522上形成额外的材料526。此外，额外的材料526可形成在金属垫片502上，例如，在金属垫片502的表面528上和/或在封装材料侧上，例如，封装材料顶侧532和在金属垫片502上。额外的材料526可经受定型化工艺，例如，加热和/或烘焙和/或退火，所述定型化工艺可选择地凝固额外的材料526和/或在间隙512中粘附额外的材料526。
在方法500的工艺560中，可去除额外材料526的一个或多个部分。例如，可去除形成于金属垫片502的表面528上的额外材料526的部分。例如，可以去除形成在封装材料侧（例如封装材料顶面532）上的额外材料526部分。换言之，只有形成在间隙512中的额外的材料526可以保留。例如，在封装材料506的侧壁508上和/或侧壁508和金属垫片502之间和/或金属垫片502的侧壁507上和/导电接触部504上的额外材料526可以保留。例如通过刻蚀工艺可去除额外材料526的一个或多个部分。此外，可执行随后的蚀刻工艺以清洗垫片，例如，金属垫片502的顶面528以确保良好的粘结性，例如，对金属垫片502的良好的配线焊接。
根据各种其他实施方式，金属垫片502可包含芯片的焊垫。各种实施方式提供了用于制造芯片516的焊垫502的方法600。结合图5A至图5F，方法600可包括：在包含导电接触部504的裸片516上形成封装材料506（在610中）；选择性地去除部分封装材料506以至少暴露导电接触部504的部分522（在620中）；在通过选择性地去除部分封装材料506而暴露的导电接触部504的部分522上形成焊垫502，其中，焊垫502和封装材料506可通过间隙512彼此分隔开（在630中）；以及在间隙512中形成额外的材料526以使间隙512的至少一部分变窄（在640中）。
可以理解的是，各种实施方式可以提供裸片配置，例如，如图5E（570）、图5F（580）以及图7（710）中所示。诸如710、570以及580的裸片配置可包含：诸如半导体芯片的裸片516，包含形成在裸片516的封装材料506之间的金属垫片502，其中，金属垫片502和封装材料506可被间隙512彼此分隔开；以及额外的材料526，形成在间隙512中以使间隙512的至少一部分变窄。
可以理解的是，各种实施方式可以提供芯片配置，例如，如图5E（570）和图5F（580）中所示。诸如570、580的芯片配置可包含导电接触部504；形成在芯片506上的封装材料506；形成在封装材料506中的暴露导电接触部504的至少一部分的开口；形成在导电接触部504的暴露部分522上的焊垫502，其中，焊垫502和封装材料506可被间隙512彼此分隔开；以及间隙512中额外的材料526以使间隙512的至少一部分变窄。
各种实施方式提供一种方法，所述方法可包括组合用于使间隙512闭合的非比例和比例酰亚胺工艺的无间隙原理。此外，可不必需要额外的光刻层，并因此可保持适度的成本。
各种实施方式提供用于填充间隙512的方法，其中，绝缘和粘合保护层（adhesive cap layer），例如，额外的材料526可以被构造而无需另外的光刻层来填充间隙512。此外，用于焊接和成型的众所周知的封装材料和/或界面可保持相对不变。假定额外的材料526的良好的加工性能（所述额外的材料526可以包括粘合层，即，其可以具有用于填充间隙512的粘合特性）可以使用已知的材料，例如，半导体制造兼容材料，例如，聚酰亚胺，例如，碳基材料，例如，有机溶液。
各种实施方式提供了用于保护芯片组件不受侵袭和/或腐蚀的方法。再分布层（例如：镍基再分布层）和/或导电接触部504会极其容易受到腐蚀。
可理解的是，方法400、500和600也可适用于焊接应用中，例如，倒装焊（flip chip bonding）、嵌入式晶片级封装（embedded wafer levelpackage），例如，eWLB，其中，金属垫片502可包括，例如焊料凸起和/或焊料合金和/或焊料球。方法400和方法500也可应用于细间距焊接工艺，其中，窄的间隙可以被填充。
各种实施方式提供了用于制造裸片的金属垫片结构的方法，所述方法包含：在裸片的封装材料之间形成金属垫片，其中，金属垫片和封装材料被间隙彼此分隔开；并在间隙中形成额外的材料以使间隙的至少一部分变窄。
根据实施方式，所述方法进一步包括在裸片的导电部上沉积封装材料；在封装材料中形成暴露导电部的至少一部分的开口；并在导电部的通过封装材料中的开口而暴露的部分上形成金属垫片。
根据实施方式，在所述封装材料中形成暴露导电部的至少一部分的开口包括从导电部分的一部分选择性地去除封装材料，从而使得所述导电部的所述部分上没有封装材料。
根据实施方式，在所述封装材料中形成暴露导电部的至少一部分的开口包括通过从导电部的所述部分去除所述封装材料而暴露所述导电部的所述部分。
根据实施方式，所述方法进一步包括在裸片的导电接触部上沉积封装材料；在封装材料中形成暴露导电接触部的至少一部分的开口；并在导电接触部的通过封装材料中的开口而暴露的部分上形成金属垫片。
根据实施方式，在裸片的导电接触部上沉积封装材料包括在裸片的导电性再分布层上沉积封装材料。
根据实施方式，在所述封装材料中形成暴露导电部的至少一部分的开口包括从导电接触部的所述部分选择性地去除封装材料，从而使得导电接触部的所述部分上没有封装材料。
根据实施方式，在所述封装材料中形成暴露导电部的至少一部分的开口包括通过从导电接触部的所述部分去除封装材料而暴露导电接触部的所述部分。
根据实施方式，所述方法进一步包括在包含导电接触部的裸片上沉积封装材料；选择性地去除封装材料的一部分从而使得暴露导电接触部的一部分；以及在导电接触部的通过选择性地去除封装材料的所述部分而暴露的部分上形成金属垫片。
根据实施方式，所述方法进一步包括在包含导电接触部的裸片上沉积钝化材料；在钝化材料上沉积封装材料；选择性地去除钝化材料和封装材料的一部分从而使得暴露导电接触部的一部分；以及在导电接触部的通过选择性地去除钝化材料和封装材料而暴露的部分上形成金属垫片。
根据实施方式，在所述裸片的封装材料之间形成金属垫片包含通过来自以下沉积方法组中至少一种沉积方法在裸片的封装材料之间沉积金属垫片，所述组包括：无电电镀、电镀、电沉积、溅射、蒸发。
根据实施方式，金属垫片和封装材料被在大约10nm至大约500nm的范围内的间隙彼此分隔开。
根据实施方式，在间隙中形成额外的材料以使间隙的至少一部分变窄包括在间隙中形成导电材料。
根据实施方式，额外的材料包含来自导电材料组的至少一种导电材料，所述导电材料组包含：钯、银、铂、金。
根据实施方式，在间隙中形成额外的材料以使间隙的至少一部分变窄包括在间隙中形成电绝缘材料。
根据实施方式，额外的材料包含来自电绝缘材料组的至少一种电绝缘材料，所述电绝缘材料组包括：环氧树脂、有机聚合物、无机聚合物、聚酰亚胺和碳基材料。
根据实施方式，在间隙中形成额外的材料包括通过以下沉积方法组中至少一种方法在间隙中形成额外的材料，所述沉积方法组包括：喷射、气相沉积、旋涂、浸涂、化学气相沉积法、等离子体增强化学气相沉积、原子层沉积、无电电镀、电镀。
根据实施方式，在间隙中形成额外的材料以使间隙的至少一部分变窄包括用额外的材料至少部分地填充所述间隙。
根据实施方式，在间隙中形成额外的材料以使间隙的至少一部分变窄包含将额外的材料粘附至封装材料的一个或多个侧壁上。
根据实施方式，所述金属垫片包含大约200nm至大约20μm的范围内的厚度
根据实施方式，所述金属垫片包含在垫片上金属化层。
各种实施方式提供了用于制造芯片的焊垫的方法，所述方法包含：在包含导电接触部的裸片上形成封装材料；选择性地去除封装材料的一部分以暴露导电接触部的至少一部分；在导电接触部的通过选择性地去除所述封装材料的所述部分为暴露的部分上形成焊垫，其中，焊垫和封装材料通过间隙彼此分隔开；以及在间隙内形成额外的材料以使间隙的至少一部分变窄。
各种实施方式提供裸片配置，所述配置包括：裸片，包括形成在裸片的封装材料之间的金属垫片，其中，金属垫片和封装材料被间隙彼此分隔开；以及额外的材料，形成在间隙中以使间隙的至少一部分变窄。
各种实施方式提供一种芯片配置包括：芯片，包括导电接触部；封装材料，形成在芯片；开口，形成在封装材料中，所述开口暴露导电接触部的至少一部分；以及焊垫，形成在导电接触部的暴露的部分上，其中，焊垫和封装材料通过间隙彼此分隔开；以及额外的材料，间隙中以使得间隙的至少一部分变窄。
虽然已参考具体实施方式特别地示出和描述了本发明，本领域技术人员应理解的是，在这里可以进行各种形式上和细节上的改变而不脱离由所附权利要求限定的本发明的精神和范围。因此本发明的范围由所附权利要求指示，并且意在包含在权利要求的等同替换的含义和范围内的所有改变。

Claims (24)

1.一种用于制造裸片的金属垫片结构的方法，所述方法包括：
在所述裸片的封装材料之间形成金属垫片，其中，所述金属垫片和所述封装材料被间隙彼此分开；以及
在所述间隙中形成额外的材料以使所述间隙的至少一部分变窄。
2.根据权利要求1所述的方法，进一步包括：
在所述裸片的导电部上沉积所述封装材料；
在所述封装材料中形成暴露所述导电部的至少一部分的开口；以及
在所述导电部的由所述封装材料中的所述开口暴露的所述部分上形成所述金属垫片。
3.根据权利要求1所述的方法，进一步包括：
在所述裸片的导电接触部上沉积所述封装材料；
在所述封装材料中形成暴露所述导电接触部的至少一部分的开口；以及
在所述导电接触部的由所述封装材料中的所述开口暴露的所述部分上形成所述金属垫片。
4.根据权利要求3所述的方法，其中，
在所述裸片的导电接触部上沉积所述封装材料包括在所述裸片的导电性再分布层上沉积封装材料。
5.根据权利要求1所述的方法，进一步包括：
在包含导电接触部的裸片上沉积所述封装材料；
选择性地去除所述封装材料的一部分以暴露所述导电接触部的至少一部分；以及
在所述导电接触部的通过选择性地去除所述封装材料的所述部分而暴露的所述部分上形成所述金属垫片。
6.根据权利要求1所述的方法，进一步包括：
在包含导电接触部的裸片上沉积钝化材料；
在所述钝化材料上沉积所述封装材料；
选择性地去除所述钝化材料的一部分和所述封装材料的一部分以暴露所述导电接触部的至少一部分；以及
在所述导电接触部的通过选择性地去除所述钝化材料和所述封装材料而暴露的所述部分上形成所述金属垫片。
7.根据权利要求1所述的方法，其中
在所述裸片的封装材料之间形成金属垫片包括通过来自以下沉积方法组中的至少一种沉积方法在所述裸片的封装材料之间沉积金属垫片，所述组由无电电镀、电镀、电沉积、溅射、蒸镀构成。
8.根据权利要求1所述的方法，
其中，所述金属垫片和所述封装材料被大约10nm至大约500nm范围内的间隙彼此分开。
9.根据权利要求1所述的方法，
其中，在所述间隙中形成额外的材料以使所述间隙的至少一部分变窄包括在所述间隙中形成导电材料。
10.根据权利要求1所述的方法，
其中，所述额外的材料包括来自导电材料组中的至少一种导电材料，所述导电材料组由钯、银、铂、金构成。
11.根据权利要求1所述的方法，
其中，在所述间隙中形成额外的材料以使所述间隙的至少一部分变窄包括在所述间隙中形成电绝缘材料。
12.根据权利要求1所述的方法，
其中，所述额外的材料包括来自电绝缘材料组中的至少一种电绝缘材料，所述电绝缘材料组由环氧树脂、有机聚合物、无机聚合物、聚酰亚胺和碳基材料构成。
13.根据权利要求1所述的方法，
其中，在所述间隙中形成额外的材料包括通过来自以下沉积方法组中的至少一种沉积方法在所述间隙中形成额外的材料，所述组由喷射、气相沉积、旋涂、浸涂、化学气相沉积、等离子体增强化学气相沉积、原子层沉积、无电电镀、电镀构成。
14.根据权利要求1所述的方法，
其中，在所述间隙中形成额外的材料以使所述间隙的至少一部分变窄包括用所述额外的材料至少部分地填充所述间隙。
15.根据权利要求1所述的方法，
其中，在所述间隙中形成额外的材料以使所述间隙的至少一部分变窄包括将所述额外的材料粘附至所述封装材料的一个或多个侧壁上。
16.根据权利要求1所述的方法，
其中，所述金属垫片包括大约200nm至大约20μm的范围内的厚度。
17.根据权利要求1所述的方法，
其中，所述金属垫片包括垫片上金属化层。
18.根据权利要求2所述的方法，其中
在所述封装材料中形成暴露所述导电部的至少一部分的开口包括从所述导电部的一部分选择性地去除所述封装材料，从而使得所述导电部的一部分上没有所述封装材料。
19.根据权利要求2所述的方法，其中
在所述封装材料中形成暴露所述导电部的至少一部分的开口包括通过从所述导电部的一部分去除所述封装材料来暴露所述导电部的所述部分。
20.根据权利要求3所述的方法，其中
在所述封装材料中形成暴露所述导电接触部的至少一部分的开口包括从所述导电接触部的一部分选择性地去除所述封装材料，从而使得所述导电接触部的一部分上没有所述封装材料。
21.根据权利要求3所述的方法，其中
在所述封装材料中形成暴露所述导电接触部的至少一部分的开口包括通过从所述导电接触部的一部分去除所述封装材料来暴露所述导电接触部的所述部分。
22.一种用于制造芯片的焊垫的方法，所述方法包括：
在包括导电接触部的芯片上形成封装材料；
选择性地去除所述封装材料的一部分以暴露所述导电接触部的至少一部分；
在通过选择性地去除所述封装材料的所述部分而暴露的所述导电接触部的所述部分上形成焊垫，其中，所述焊垫和所述封装材料被间隙彼此分开；以及
在所述间隙中形成额外的材料以使所述间隙的至少一部分变窄。
23.一种裸片配置件，包括：
裸片，包括形成在所述裸片的封装材料之间的金属垫片，其中，所述金属垫片和所述封装材料被间隙彼此分开；以及
额外的材料，形成在所述间隙中以使所述间隙的至少一部分变窄。
24.一种芯片配置件，包括：
芯片，包括导电接触部；
封装材料，形成在所述芯片上；
开口，形成在所述封装材料中，所述开口暴露所述导电接触部的至少一部分；
焊垫，形成在所述导电接触部的所暴露的部分上，其中，所述焊垫和所述封装材料被间隙彼此分开；以及
所述间隙中的额外的材料，使所述间隙的至少一部分变窄。
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