CN107369668B - 用于制造半导体封装元件的半导体结构 - Google Patents

用于制造半导体封装元件的半导体结构 Download PDF

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CN107369668B
CN107369668B CN201710475466.0A CN201710475466A CN107369668B CN 107369668 B CN107369668 B CN 107369668B CN 201710475466 A CN201710475466 A CN 201710475466A CN 107369668 B CN107369668 B CN 107369668B
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carrier
semiconductor structure
outer coating
semiconductor
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CN107369668A (zh
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周辉星
林建福
欧菲索
林少雄
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Advanpack Solutions Pte Ltd
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Abstract

本发明公开一种用于制造半导体封装元件的半导体结构。半导体结构包括载板以及绝缘层。载板具有相对的第一表面与第二表面，载板包括内层(inner layer)及外披覆层(exterior clad layer)，外披覆层包覆内层。绝缘层形成于载板的第一表面上，其中载板支撑绝缘层。

Description

用于制造半导体封装元件的半导体结构
本申请是2012年7月23日提交的、申请号为201210256856.6、发明名称为“用于制造半导体封装元件的半导体结构及其制造方法”的发明专利申请的分案申请。
技术领域
本发明涉及一种半导体结构及其制造方法，且特别是涉及一种用于制造半导体封装元件的半导体结构及其制造方法。
背景技术
传统的半导体封装元件例如包括基板、导线、环氧树脂封装层及芯片。基板的材质例如是铜，用以承载芯片，芯片与导线电连接，环氧树脂封装层包覆导线与芯片。
然而，基板整体材质都以铜来制作时，其成本较高，且容易发生翘曲。并且，环氧树脂封装层与导线之间的密封性不佳，常产生后续蚀刻制作工艺中的蚀刻液露出而破坏导线的问题。因此，为了因应上述问题而提出解决方法实为必要的。
发明内容
本发明的目的在于提供一种半导体结构及其制造方法。半导体结构中，载板的外披覆层包覆内层，可于后续蚀刻步骤中提供较佳的蚀刻阻隔，并且，导线层埋设于绝缘层中，可以防止导线层在后续的蚀刻制作工艺中受到蚀刻液的破坏。
为达上述目的，根据本发明的一方面，提出一种用于制造半导体封装元件的半导体结构。半导体结构包括载板以及绝缘层。载板具有相对的一第一表面与一第二表面，载板包括内层及外披覆层，外披覆层包覆内层。绝缘层形成于该载板的该第一表面上，其中该载板支撑该绝缘层。
根据本发明的另一方面，提出一种半导体封装元件的制造方法。半导体封装元件的制造方法包括：提供一载板，载板具有相对的一第一表面与一第二表面，载板包括一内层及一外披覆层，外披覆层包覆内层；形成一导线层于载板的第一表面上；以及形成一绝缘层于载板上且暴露出导线层。
为让本发明的上述内容能更明显易懂，下文特举较佳实施例，并配合所附附图，作详细说明如下：
附图说明
图1A为本发明一实施例的半导体结构的剖视图；
图1B为本发明另一实施例的半导体结构的剖视图；
图1C为本发明再一实施例的半导体结构的剖视图；
图2A为本发明一实施例的半导体封装元件的剖视图；
图2B为本发明另一实施例的半导体封装元件的剖视图；
图2C为本发明再一实施例的半导体封装元件的剖视图；
图3A至图3G为本发明一实施例的半导体封装元件的制造方法的流程图；
图4A至图4C为本发明另一实施例的半导体封装元件的制造方法的流程图；
图5A至图5D为本发明一实施例的移除载板的制作工艺步骤的流程图；
图6为本发明另一实施例的移除载板的制作工艺步骤的流程图；
图7为本发明更一实施例的移除载板的制作工艺步骤的流程图。
主要元件符号说明
10A、10B、10C：半导体结构
110：载板
110a、130a：第一表面
110b、130b：第二表面
111：内层
113：外披覆层
120：导线层
121：导电层
123：阻障层
125：保护层
130：绝缘层
130’：绝缘材料层
140：半导体芯片
150：连接元件
160：封装层
170：粘着层
20A、20B、20C、20D：半导体封装元件
T1、T2、T3：厚度
具体实施方式
请参照图1A。图1A绘示依照本发明一实施例的半导体结构的剖视图。半导体结构10A包括载板110以及导线层120。载板110具有相对的第一表面110a与第二表面110b，载板110包括内层111(inner layer)及外披覆层113(exterior clad layer)，外披覆层113包覆内层111。
实施例中，内层111的厚度例如是大约200微米，外披覆层113的厚度例如是5～20微米。实施例中，内层111的厚度相对于外披覆层113的厚度的一比例例如是大于10。
实施例中，内层111包括一第一金属，第一金属的材质例如是钢，或是包括铁、碳、镁、磷、硫、铬及镍其中两种以上的合金，或是不锈钢合金。一实施例中，内层111的材质例如是具有以下组成的合金：97％以上的铁、小于或等于0.12％的碳、小于或等于0.5％的镁、小于或等于0.05％的磷、小于或等于0.05％的硫、小于或等于0.2％的铬及小于或等于0.2％的镍，其中碳和镍的百分比最低可以为0％。另一实施例中，内层111的材质例如包括导电金属材料。
实施例中，外披覆层113包括一第二金属，第二金属的材质例如是铜，其材质与第一金属的材质为不相同。在后续的半导体制作工艺中，可于移除载板110的蚀刻步骤中，利用外披覆层113的材质与内层111的材质不相同，从而提供较佳的蚀刻阻隔。并且，外披覆层113的材质例如是铜时，使得载板110可以被视作一个完整的铜层来操作应用，并且能够降低整体制作成本。另一实施例中，外披覆层113的材质例如包括导电金属材料。
载板110的热膨胀系数(CTE)和模数(modulus)取决于内层111的热膨胀系数(CTE)和模数(modulus)。实施例中，内层111的第一金属的热膨胀系数(CTE)介于约10至15ppm/℃，此热膨胀系数接近用以包覆半导体芯片的封装材料的热膨胀系数，可以使得应用载板110而制成的半导体封装元件的翘曲量减少，可容许载板110的面积增大，在此情况下，可在载板110上形成更多数量的半导体封装元件。实施例中，内层111的第一金属的模数(modulus)介于约150至250GPa，载板110坚固的特性有利于后续的制作工艺操作。
如图1A所示，半导体结构10A可包括绝缘层130，绝缘层130形成于载板110上。实施例中，绝缘层130形成于载板110的第一表面110a上。实施例中，绝缘层130例如是树脂(resin)材料，树脂材料的热膨胀系数介于约10至15ppm/℃，其与载板110的热膨胀系数的差值小于3ppm/℃。一实施例中，绝缘层130的材质例如是有机树脂材料。另一实施例中，绝缘层130的材质例如包括环氧树脂及氧化硅填料(silica fillers)。
如图1A所示，导线层120埋设于绝缘层130中。导线层120埋设于绝缘层130中可以防止导线层120在后续的蚀刻制作工艺中受到蚀刻液的破坏。
实施例中，绝缘层130具有一第一表面邻接于载板110以及一第二表面相对于第一表面，导线层120埋设于绝缘层130的第一表面和第二表面之间，导线层120连接绝缘层130的第一表面和第二表面。
实施例中，部分导线层120暴露于绝缘层130之外。实施例中，外披覆层113的材质例如是铜，导线层120的材质例如是和外披覆层113的材质为相同。
请参照图1B。图1B绘示依照本发明另一实施例的半导体结构的剖视图。本实施例与图1A的实施例的差别在于，半导体结构10B中，导线层120包括一导电层121和一阻障层123，导电层121形成于110载板上，阻障层123形成载板110与导电层121之间。
实施例中，导电层121的材质例如是铜，阻障层123的材质例如包括镍、金或锡。实施例中，导电层121的厚度例如是大约15微米，阻障层123的厚度例如是大约5微米。
请参照图1C。图1C绘示依照本发明再一实施例的半导体结构的剖视图。本实施例与图1B的实施例的差别在于，半导体结构10C中，导线层120还包括一保护层125，保护层125形成于载板110上且位于载板110与阻障层123之间。
实施例中，保护层125的材质例如是铜，保护层125的材质与外披覆层113的材质例如相同。实施例中，保护层125的厚度例如是大约5微米。
请参照图2A。图2A绘示依照本发明一实施例的半导体封装元件的剖视图。半导体封装元件20A包括导线层120、绝缘层130以及半导体芯片140。导线层120埋设于绝缘层130中，半导体芯片140设置于绝缘层130上。实施例中，半导体芯片140电连接导线层120。
实施例中，导线层120埋设于绝缘层130中，可以防止导线层120在后续的蚀刻制作工艺中受到蚀刻液的破坏。
如图2A所示，半导体封装元件20A可包括连接元件150，连接元件150电连接半导体芯片140与导线层120。
请参照图2B。图2B绘示依照本发明另一实施例的半导体封装元件的剖视图。本实施例与图2A的实施例的差别在于，半导体封装元件20B中还可包括封装层160，封装层160包覆半导体芯片140。
请参照图2C。图2C绘示依照本发明再一实施例的半导体封装元件的剖视图。本实施例与图2A的实施例的差别在于，半导体封装元件20C中，导线层120包括一导电层121和一阻障层123。导电层121和阻障层123的材质、厚度及配置关系如前述实施例所述，在此不再赘述。部分阻障层123暴露于绝缘层130之外，以利于将半导体封装元件20C焊接到其他外部元件，例如基板。
请参照图3A至图3G。图3A至图3G绘示依照本发明一实施例的半导体封装元件的制造方法的流程图。
请参照图3A，提供载板110。载板110具有相对的第一表面110a与第二表面110b，载板110包括内层111及外披覆层113，外披覆层113包覆内层111。外披覆层113和内层111的材质如前述实施例所述，在此不再赘述。
实施例中，载板110的制造方式例如包括以下步骤：提供内层111；清洁(degreasing)内层111的表面；抛光(buffing)内层111的表面；以及形成外披覆层113。
实施例中，清洁内层111的表面例如是移除表面残留或不必要的化学物质(chemical)以及微粒，将内层111的表面清洁干净，用以提升内层111与外披覆层113的粘着性。实施例中，抛光内层111的表面例如是移除表面的缺陷，例如是刮痕(scratches)或凹陷(pits)，以形成均匀的表面。接着，例如是以电解电镀(electrolytic plating)或无电解电镀(electroless plating)形成外披覆层113。实施例中，形成外披覆层113之前，可先形成一晶种电镀层(seed plating layer)，有助于外披覆层113的电镀成长。
请参照图3B，形成导线层120于载板110的第一表面110a上。
一实施例中，形成导线层120的步骤例如包括：形成一阻障层123于载板110上，以及形成一导电层121于阻障层123上(请参照图1B)。另一实施例中，形成导线层120的步骤例如包括：形成一保护层125于载板110上、形成一阻障层123于保护层125上以及形成一导电层121于阻障层123上(请参照图1C)。
实施例中，例如是以图案化电解电镀(patterned electrolytic plating)方式形成导线层120于载板110上。实施例中，例如是以全加成法(full additive processing)、半加成法(semi-additive processing)或全减成法(full subtractive processing)方式形成导线层120于载板110上，并且上述形成步骤可以重复进行，以形成多层导线层120或具有多层结构的导线层120。
请参照图3C，形成绝缘材料层130’于载板110上且包覆导线层120。实施例中，绝缘材料层130’形成于载板110的第一表面110a上，并且完全包覆导线层120。一实施例中，例如是以一热压膜制(molding)方式形成绝缘材料层130’于载板110上。在高温高压下进行热压膜制，使得绝缘层130与导线之间的密封性好，在后续蚀刻制作工艺中导线不会被破坏。另一实施例中，例如是以贴合(lamination)或旋转涂布(spin-coating)树脂材料的方式形成绝缘材料层130’于载板110上。
请参照图3D，薄化绝缘材料层130’以形成绝缘层130并暴露出导线层120。绝缘层130具有相对的第一表面130a与第二表面130b，绝缘层130的第一表面130a邻接载板110的第一表面110a。实施例中，例如是自载板110的第一表面110a侧研磨绝缘材料层130’以形成绝缘层130，使导线层120的一部分自绝缘层130的第二表面130b暴露出来。
请参照图3E，移除载板110。实施例中，例如是蚀刻方式移除载板110。此时，导线层120的另一部分自绝缘层130的第一表面130a暴露出来。由此形成的半导体结构，导线层120完全埋设于绝缘层130中。
请参照图3F，设置半导体芯片140于绝缘层130上。实施例中，设置半导体芯片140于绝缘层130的第一表面130a上。如图3F所示，可形成连接元件150及粘着层170，连接元件150电连接半导体芯片140与导线层120，半导体芯片140经由粘着层170设置于绝缘层130上。
请参照图3G，形成封装层160。封装层160包覆半导体芯片140。如图3G所示，封装层160包覆导线层120、半导体芯片140、连接元件150、粘着层170及部分绝缘层130的第一表面130a。至此，形成如图3G所示的半导体封装元件20D。
请同时参照图3A至图3D及图4A至图4C。图4A至图4C绘示依照本发明另一实施例的半导体封装元件的制造方法的流程图。本实施例中与前述实施例相同的元件沿用同样的元件标号，且相同元件的相关说明请参考前述，在此不再赘述。
首先，如图3A至图3D所示，提供载板110、形成导线层120于载板110的第一表面110a上、形成绝缘材料层130’于载板110上且包覆导线层120、以及薄化绝缘材料层130’以形成绝缘层130并暴露出导线层120。
请参照图4A，设置半导体芯片140于绝缘层130上。实施例中，设置半导体芯片140于绝缘层130的第二表面130b上。如图4A所示，可形成连接元件150及粘着层170，连接元件150电连接半导体芯片140与导线层120，半导体芯片140经由粘着层170设置于绝缘层130上。
请参照图4B，形成封装层160。封装层160包覆半导体芯片140。如图4B所示，封装层160包覆导线层120、半导体芯片140、连接元件150、粘着层170及部分绝缘层130的第二表面130b。
请参照图4C，移除载板110。实施例中，例如是蚀刻方式移除载板110。此时，导线层120的一部分自绝缘层130的第一表面130a暴露出来。至此，形成如图4C(图2B)所示的半导体封装元件20B。
请参照图5A至图5D。图5A至图5D绘示依照本发明一实施例的移除载板的制作工艺步骤的流程图。本实施例中与前述实施例相同的元件沿用同样的元件标号，且相同元件的相关说明请参考前述，在此不再赘述。
请参照图5A，导线层120及绝缘层130设置于载板110的第一表面110a上。导线层120埋设于该绝缘层130中。请参照图5B，以第一蚀刻液蚀刻载板110，以移除位于载板110的第二表面110b的部分外披覆层113及部分内层111。
实施例中，第一蚀刻液例如包括氯化铁或氯化氢。
实施例中，第一蚀刻液对内层111的蚀刻速率大约大于20微米/分钟(μm/min)，蚀刻之后残留的部分内层111具有的厚度T1大约是20微米。
请参照图5C，以第二蚀刻液蚀刻载板110，以移除载板110的残留的内层111，并曝露位于载板110的第一表面110a的部分外披覆层113。
实施例中，第二蚀刻液对内层111及外披覆层113的蚀刻速率比大约大于5。实施例中，第二蚀刻液例如包括硫酸或过氧化氢。
实施例中，第二蚀刻液对外披覆层113的蚀刻速率约小于1微米/分钟，第二蚀刻液对内层111的蚀刻速率约大于5微米/分钟，蚀刻之后残留的部分外披覆层113具有的厚度T2大约是3微米。如此一来，内层111实质上被蚀刻而完全移除，以第二蚀刻液对内层111及外披覆层113的蚀刻速率差距来降低第二蚀刻液对于外披覆层113蚀刻的程度，残留的部分外披覆层113可具有相对平整的表面，并且防止过度蚀刻对导线层带来的损害。
请参照图5D，利用在第二蚀刻步骤中所达到的外披覆层113的平整的表面，以第三蚀刻液蚀刻载板110，移除位于载板110的第一表面110a的残留的部分外披覆层113并曝露导线层120。
实施例中，第三蚀刻液例如包括氯化铵或氨。实施例中，第三蚀刻液对外披覆层113的蚀刻速率约小于5微米/分钟(μm/min)。蚀刻后暴露出的导线层120具有相对平整的表面。
另一实施例中，以第三蚀刻液蚀刻载板110同时也蚀刻大约3至5微米导线层120，使得导线层120的表面低于绝缘层130的第一表面130a。
如前所述，以包括内层111及外披覆层113的载板110结构结合三个蚀刻液分别进行三次蚀刻步骤以移除载板110，如此一来，可以针对不同膜层的特性分别调整各个蚀刻液的组成及蚀刻速率，可以提高对于整个蚀刻制作工艺的控制作工艺度，并且使得蚀刻后暴露出的导线层120的表面更加平整。
请同时参照图5A至图5C及图6。图6绘示依照本发明另一实施例的移除载板的制作工艺步骤的流程图。本实施例中与前述实施例相同的元件沿用同样的元件标号，且相同元件的相关说明请参考前述，在此不再赘述。
首先，如图5A至图5C所示，以第一蚀刻液蚀刻载板110以移除位于载板110的第二表面110b的部分外披覆层113及部分内层111，以及以第二蚀刻液蚀刻载板110，以移除载板110的内层111并曝露位于载板110的第一表面110a的部分外披覆层113。
接着，请参照图6，以第三蚀刻液蚀刻载板110，以移除位于载板110的第一表面110a的部分外披覆层113并曝露导线层120。实施例中，导线层120包括一导电层121及阻障层123，阻障层123位于载板110与导电层121之间，蚀刻后曝露出阻障层123。
实施例中，第二蚀刻液对外披覆层113的蚀刻速率约为5微米/分钟，第二蚀刻液对内层111的蚀刻速率约大于20微米/分钟，蚀刻之后残留的部分外披覆层113具有的厚度大约是3微米。如此一来，内层111实质上被蚀刻而完全移除，残留的部分外披覆层113可具有相对平整的表面。实施例中，第三蚀刻液对阻障层123的蚀刻速率约小于1微米/分钟，第三蚀刻液对外披覆层113的蚀刻速率约小于5微米/分钟，蚀刻之后的阻障层123具有的厚度大约是3微米。如此一来，利用第三蚀刻液对阻障层123和外披覆层113的蚀刻速率差距，可以阻挡第二蚀刻液对于导电层121可能造成破坏。
请同时参照图5A至图5C及图7。图7绘示依照本发明更一实施例的移除载板的制作工艺步骤的流程图。本实施例中与前述实施例相同的元件沿用同样的元件标号，且相同元件的相关说明请参考前述，在此不再赘述。
首先，如图5A至图5C所示，以第一蚀刻液蚀刻载板110以移除位于载板110的第二表面110b的部分外披覆层113及部分内层111，以及以第二蚀刻液蚀刻载板110，以移除载板110的内层111并曝露位于载板110的第一表面110a的部分外披覆层113。
接着，请参照图7，以第三蚀刻液蚀刻载板110，以移除位于载板110的第一表面110a的部分外披覆层113并曝露导线层120。实施例中，导线层120包括一导电层121、一阻障层123及一保护层125，阻障层123位于载板110与导电层121之间，保护层125位于载板110与阻障层123之间。如图7所示，保护层125的材质与外披覆层113的材质例如是相同，以第三蚀刻液蚀刻载板110时也蚀刻保护层125，蚀刻后暴露出阻障层123。
实施例中，第三蚀刻液对外披覆层113的蚀刻速率约小于5微米/分钟，第三蚀刻液对阻障层123的蚀刻速率约小于1微米/分钟，蚀刻之后的阻障层123具有的厚度T3大约是3微米。
实施例中，蚀刻后保护层125实质上被蚀刻而完全移除，暴露出的阻障层123可具有相对平整的表面，使得导线层120的表面低于绝缘层130的第一表面130a。
综上所述，虽然结合以上实施例揭露了本发明，然而其并非用以限定本发明。本发明所属技术领域中熟悉此技术者，在不脱离本发明的精神和范围内，可作各种的更动与润饰。因此，本发明的保护范围应以附上的权利要求所界定的为准。

Claims (10)

1.一种用于防止半导体封装元件在制造时受到蚀刻工艺破坏的半导体结构，包括：
载板，用于在制造该半导体封装元件时提供支撑，该载板包括内层及外披覆层，该外披覆层形成该载板的第一载板表面及相对的第二载板表面并包覆该内层，该外披覆层的材质不相同于该内层的材质；
其中，该半导体封装元件包括绝缘层以及导线层，该绝缘层具有第一绝缘层表面邻接于该第一载板表面及相对的第二绝缘层表面，该导线层埋设于该第一绝缘层表面和该第二绝缘层表面之间并电性连接该第一绝缘层表面和该第二绝缘层表面；
其中，该外披覆层的蚀刻速率小于该内层的蚀刻速率。
2.如权利要求1所述的半导体结构，其中该内层包括第一金属，该外披覆层包括第二金属。
3.如权利要求2所述的半导体结构，其中该第一金属包括铁，该第二金属包括铜。
4.如权利要求3所述的半导体结构，其中该第一金属为一合金，该第一金属还包括碳、镁、磷、硫、铬或镍。
5.如权利要求4所述的半导体结构，其中该第一金属为一不锈钢合金。
6.如权利要求1所述的半导体结构，其中该内层相对于该第一载板表面的该外披覆层的厚度比例大于10。
7.如权利要求1所述的半导体结构，其中该绝缘层的材质包括树脂材料及氧化硅填料。
8.如权利要求1所述的半导体结构，其中该导线层包括导电层，该导电层埋设于该绝缘层中并邻接于该第一载板表面的该外披覆层。
9.如权利要求8所述的半导体结构，其中该导线层还包括阻障层，设于该第一载板表面与该导电层之间并邻接于该第一载板表面的该外披覆层，该阻障层的蚀刻速率小于该外披覆层的蚀刻速率。
10.如权利要求9所述的半导体结构，其中该导线层还包括保护层，设于该第一载板表面与该阻障层之间并邻接于该第一载板表面的该外披覆层，该保护层的材质与该外披覆层的材质相同。
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