WO2011027186A1 - 封装结构 - Google Patents

封装结构 Download PDF

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Publication number
WO2011027186A1
WO2011027186A1 PCT/IB2009/006710 IB2009006710W WO2011027186A1 WO 2011027186 A1 WO2011027186 A1 WO 2011027186A1 IB 2009006710 W IB2009006710 W IB 2009006710W WO 2011027186 A1 WO2011027186 A1 WO 2011027186A1
Authority
WO
WIPO (PCT)
Prior art keywords
conductive
signal
semiconductor
package structure
conductive bumps
Prior art date
Application number
PCT/IB2009/006710
Other languages
English (en)
French (fr)
Inventor
周辉星
王志坚
Original Assignee
先进封装技术私人有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 先进封装技术私人有限公司 filed Critical 先进封装技术私人有限公司
Priority to US13/393,746 priority Critical patent/US8796844B2/en
Priority to PCT/IB2009/006710 priority patent/WO2011027186A1/zh
Publication of WO2011027186A1 publication Critical patent/WO2011027186A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/0243—Printed circuits associated with mounted high frequency components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10378—Interposers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10507—Involving several components
    • H05K2201/10522—Adjacent components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip

Definitions

  • the present invention relates to a package structure, and more particularly to a package structure including a semiconductor connection element (Interposer). Background technique
  • the semiconductor components are electrically connected and disposed on a substrate, and then a package structure is completed by covering the sealant.
  • the external signal can be transmitted to the inside of the semiconductor element through the substrate.
  • each semiconductor component has several electrical contacts. If the electrical contacts of two or more semiconductor components are connected to the substrate, the design of the wires will be a rather difficult task.
  • the present invention relates to a package structure that utilizes the design of the wires of a semiconductor connection element such that the substrate of the package structure can simultaneously form a signal communication path with the first semiconductor component and the second semiconductor component.
  • a package structure includes at least one first semiconductor component, at least one second semiconductor component, a semiconductor connection component, and a substrate.
  • the first semiconductor component includes a plurality of first conductive bumps.
  • the second semiconductor component includes a plurality of second conductive bumps.
  • the semiconductor connecting component includes a connecting main board, at least one signal wire and at least one signal conducting post. The signal wires are placed on the connection board. Both ends of the signal wire are electrically connected to the first guide One of the electrical bumps and one of the second conductive bumps.
  • the signal conductive column is electrically connected to the signal wire.
  • the substrate is electrically connected to the signal conductive column.
  • the first semiconductor element and the second semiconductor element are both memory chips, and the first semiconductor element and the second semiconductor element have the same line structure.
  • a package structure includes a semiconductor component, a semiconductor connection component, and a substrate.
  • the semiconductor component includes at least two signal conductive bumps.
  • the semiconductor connecting component comprises a connecting main board, at least two signal conducting columns and at least two signal wires.
  • the signal conductive column runs through the connection motherboard.
  • the signal wires are placed on the connection board.
  • the two ends of each signal wire are electrically connected to one of the signal conductive bumps and one of the signal conductive columns. Wherein the lengths of the individual signal conductors are substantially equal.
  • the substrate is electrically connected to the signal conductive column.
  • FIG. 1 is a schematic view of a package structure in accordance with a first embodiment of the present invention
  • FIG. 2 is a top plan view of the package structure of FIG. 1;
  • 3A is a cross-sectional view of the package structure of FIG. 2 taken along a section line ⁇ - ⁇ ';
  • 3A is a cross-sectional view of the package structure of FIG. 2 along a section line ⁇ - ⁇ ;
  • 3C is a cross-sectional view of the package structure of FIG. 2 taken along section line C-C';
  • FIG. 4 is a schematic diagram of the first conductive bump, the signal conductor, the signal conductive pillar, and the second conductive bump of FIG. 2;
  • FIG. 5 is a top plan view of a package structure in accordance with a second embodiment of the present invention.
  • FIG. 6 is a top plan view of a package structure in accordance with a third embodiment of the present invention.
  • FIG. 7 is a top plan view of a package structure in accordance with a fourth embodiment of the present invention.
  • 8 to 13 are schematic views showing a method of manufacturing a semiconductor connecting element. detailed description
  • FIG. 1 is a schematic diagram of a package structure 1000 in accordance with a first embodiment of the present invention.
  • the package structure 1000 of the present embodiment includes a first semiconductor component 100, a second semiconductor component 200, and a semiconductor connection component 300 (Interposer) (the material of which includes a thermoplastic resin (thermo) Plastic ) or epoxy ( epoxy ) and a substrate 400 .
  • the first semiconductor element 100 and the second semiconductor element 200 are, for example, a memory chip, a processing chip, a photosensitive chip, or the like.
  • the first semiconductor element 100 and the second semiconductor element 200 are both memory chips, and the circuit structures of the first semiconductor element 100 and the second semiconductor element 200 are the same.
  • the material of the substrate 400 is an insulating material such as glass fiber (FR4) or ceramic material.
  • the semiconductor connection element 300 is disposed between the first semiconductor 100 and the substrate 400 and is disposed between the second semiconductor 200 and the substrate 400.
  • the semiconductor connection component 300 is used to electrically connect the substrate 400 to the first semiconductor component 100 and the second semiconductor component 200 at the same time.
  • FIG. 2 is a plan view of the package structure 1000 of FIG. 1
  • FIG. 3A is a cross-sectional view of the package structure 1000 of FIG. 2 along the line AA
  • FIG. 3C is a cross-sectional view of the package structure 1000 of FIG. 2 taken along section line CC.
  • the first semiconductor device 100 includes a plurality of first conductive bumps 110, a plurality of third conductive bumps 130, and a plurality of power conductive bumps 150.
  • the second semiconductor device 200 includes a plurality of second conductive bumps.
  • Figure 2 presents the internal components in a perspective manner.
  • the first conductive bumps 110 are arranged along a first extension line L1.
  • the second conductive bumps 220 are arranged along a second extension line L2.
  • the third conductive bumps 130 are arranged along a third extension line L3.
  • the four conductive bumps 240 are arranged along a fourth extension line L4.
  • the first extension line L1, the second extension line L2, the third extension line L3, and the fourth extension line L4 are substantially parallel to each other.
  • the pitch of the first extension line L1 and the third extension line L3 is substantially 350 ⁇ m (um).
  • the pitch of each of the first conductive bumps 110 is 150 micrometers on the solid shield, and the pitch of each of the third conductive bumps 130 is substantially 150 micrometers.
  • the first conductive bumps 110 and the third conductive bumps 130 are arranged correspondingly. That is, the line L13 of the first conductive bump 110 and the corresponding third conductive bump 130 is substantially perpendicular to the first extension line L1 and the third extension line 13.
  • the second conductive bumps 220 and the fourth conductive bumps 240 are correspondingly arranged. That is, the connection line L24 of the second conductive bump 220 and the corresponding fourth conductive bump 240 is perpendicular to the second extension line L1 and the fourth extension line.
  • FIG. 3A as an example, along the AA of FIG. 2, the first conductive bump 110 and the third conductive bump 130 can be viewed simultaneously.
  • the first semiconductor device 100 and the second semiconductor device 200 of the present embodiment have a similar structure, so that the arrangement of the first conductive bumps 110 and the third conductive bumps 130 and the second conductive bumps 220 and fourth The conductive bumps 240 are arranged in a similar manner.
  • the pitch of the second extension line L2 and the fourth extension line L4 is also substantially 350 micrometers.
  • the pitch of each of the second conductive bumps 220 is also substantially 150 micrometers, and the pitch of each of the four conductive bumps 240 is substantially 150 square meters.
  • the semiconductor connection component 300 of the present embodiment includes a connection main board 310, a plurality of signal wires 320, a plurality of power supply wires 340, a plurality of signal conductive columns 330, and a plurality of power sources.
  • the signal wire 320 is disposed on the connection main board 310.
  • the two ends of the signal conductors 320 are electrically connected to one of the first conductive bumps 110 and one of the second conductive bumps 220, respectively.
  • the two ends of the signal conductors 320 are electrically connected to one of the third conductive bumps 130 and one of the fourth conductive bumps 240, respectively.
  • FIG. 4 is a schematic diagram of the first conductive bump 110, the signal conductor 320, the signal conductive pillar 330 and the second conductive bump 220 of FIG.
  • the signal conductive post 330 is connected to the main board 310.
  • the substrate 400 is electrically connected to the signal conductors 320 through the signal conductive posts 330.
  • the first conductive bumps 110, the signal wires 320, and the signal conductive pillars 330 form a signal transmission path.
  • the second conductive bump 220, the signal conductor 320, and the signal conductive pillar 330 may also form another signal transmission path. That is, the signals of the first conductive bumps 110 and the second conductive bumps 220 may be transmitted together to the substrate 400 (or the substrate 400 may transmit signals to the first conductive bumps 110 and the second conductive via the same signal conductive pillars 330). Bump 220).
  • the signal conductive post 330 is electrically connected to a midpoint M of a line segment of the signal conductor 320.
  • the lengths D1 and D2 of the line segment midpoint M to the signal conductors 320 are substantially equal. Since the lengths D1 and D2 of the two ends of the line segment M to the signal wire 320 are substantially equal, the lengths of the two signal transmission paths are also equal, so that the difference between the two signal transmissions causes any difference in transmission time (Differential in Arrival time ).
  • the first semiconductor device 100 there are a plurality of third conductive bumps 130 on the left side of the first conductive bump 110, and no other conductive bumps on the right side; and in the second semiconductor device 200,
  • the second conductive bump 220 has a thousand fourth conductive bumps 140 on the left side, and the right side has no He has conductive bumps.
  • the first conductive bumps 110 and the second conductive bumps 220 are staggered.
  • the signal wire 320 extending from the first conductive bump 110 extends first to the right, then extends downward, and then extends to the left to the second conductive bump 220 to form a U-shaped opening to the left. Transition structure.
  • the signal conductor 320 extending from the fourth conductive bump 240 extends first to the left, then extends upward, and then extends to the right to form a U-turn structure having an opening to the right.
  • the U-shaped transition structure extends the distance between the midpoint M and the two end points of the line segment of the signal conductor 320, and a portion of the signal conductive pillars 330 are arranged along a fifth extension line L5, and a portion of the signal conductive pillars 330 follow a sixth extension line L6.
  • the pitch of the fifth extension line L5 and the sixth extension line L6 is greater than the pitch of the first extension line L1 and the third extension line L3, and is greater than the pitch of the second extension line L2 and the fourth extension line L4.
  • the signal conductor 320 of the present embodiment includes a first sub-signal conductor 321, a second sub-signal conductor 322, and a third sub-signal conductor 323.
  • One end of the first sub-signal wire 321 is connected to one of the first conductive bumps 110.
  • One end of the second sub-signal conductor 322 is connected to one of the second conductive bumps 220 and is parallel to the first sub-signal conductor 321 .
  • the two ends of the third sub-signal conductor 323 are connected to the other end of the first sub-signal conductor 321 and the other end of the second sub-signal conductor 322, respectively.
  • the third sub-signal conductor 323 is substantially perpendicular to the first sub-signal conductor 321 and the second sub-signal conductor 322. That is, the signal wire 320 of the present embodiment has a U-turn structure with a double right angle. Similarly, the signal wires 320 connecting the third conductive bumps 130 and the fourth conductive bumps 240 have the same structure and will not be repeated here.
  • the semiconductor connection element 300 of the present embodiment can form a signal transmission path for the first semiconductor element 100 and the second semiconductor element 200 and the substrate 400 in a single-layer circuit structure without requiring a complicated multilayer circuit structure. This significantly reduces manufacturing and material costs.
  • the power lead 340 is connected in series with the power conductive bumps 150 of the first semiconductor component 100 and disposed adjacent to the power conductive bumps 150. in this way First, as shown in FIG. 3B, the power supply conductive bumps 150, the power supply wires 340, and the power supply conductive posts 350 form a power transmission path. Similarly, as shown in FIG. 3C, the power conductive bump 250, the power lead 340, and the power conductive post 350 also form another power transfer path.
  • the current of the power signal is large, and the lower the impedance of the wire, the better, to avoid overheating the wire.
  • the power conductive bumps 150 since the power supply conductive bumps 150 are connected in series by a power supply line 340, the number of power supply wires 340 can be reduced. And the power supply wires 340 are disposed adjacent to the power supply conductive bumps 150, and the length of the power supply wires 340 can also be shortened. As a result, the impedance of the power supply lead 340 can be minimized and the transmission efficiency of the power supply signal can be improved.
  • the package structure 1000 of the embodiment further includes a first sealant 500 and a second sealant 600.
  • the first adhesive 500 is disposed between the first semiconductor component 100 and the semiconductor connection component 300, and between the second semiconductor component 200 and the semiconductor connection component 300.
  • the second sealant 600 is disposed between the semiconductor connecting member 300 and the substrate 400.
  • the first conductive bumps 110, the second conductive bumps 220, the third conductive bumps 130 (not shown in FIG. 1), the fourth conductive bumps 240 (not shown in FIG. 1), the signal wires 320, and the power wires The 340 is covered in the first sealant 500, and the signal conductive post 330 and the power conductive post 350 are wrapped in the second sealant 600. Therefore, the package structure 1000 can be completely protected.
  • FIG. 5 a top view of a package structure 2000 in accordance with a second embodiment of the present invention is shown.
  • the package structure 2000 of the present embodiment is different from the package structure 1000 of the first embodiment in the arrangement of the power supply wires 340a, and the rest of the same points are not repeated.
  • the semiconductor connecting component 300a of the present embodiment includes a plurality of power supply wires 340a, one end of each power supply wire 340a is connected to a power conductive bump 150 or a power conductive bump 250, and adjacent to the power conductive bump 150 or this power supply conductive bump 250 is provided.
  • the other end of each power supply line 340a is connected to each of the respective power supply conductive posts 350.
  • FIG. 6 a top view of a package structure 3000 in accordance with a third embodiment of the present invention is shown.
  • the package structure 3000 of the present embodiment is different from the package structure 2000 of the second embodiment in the number of the first semiconductor elements 100 and the number of the second semiconductor elements 200, and the rest are not the same. Repeat again.
  • the package structure 3000 includes a plurality of first semiconductor elements 100 and a plurality of second semiconductor elements 200.
  • the number of these first semiconductor elements 100 and these second semiconductor elements 200 is the same. And these first semiconductor elements 100 and these second semiconductor elements 200 correspond.
  • the semiconductor connecting element 300b can replicate the pattern of the plurality of sets of signal wires 320 and power wires 340a by repeated exposure of a photomask, which is quite convenient.
  • FIG. 7 a top view of a package structure 4000 in accordance with a fourth embodiment of the present invention is shown.
  • the package structure 4000 of the present embodiment differs from the package structure 1000 of the first embodiment in the number of the semiconductor elements 700 and the arrangement of the signal wires 820 and the power wires 840, and the rest are not repeated.
  • the package structure 4000 of the present embodiment includes a semiconductor element 700, a semiconductor connection element 800, and a substrate 900.
  • package structure 4000 includes only one semiconductor component 700.
  • the semiconductor component 700 includes at least two signal conductive bumps 710 and a power conductive bump 750.
  • the semiconductor connection component 800 includes a connection main board 810, at least two signal conductive pillars 830, at least two signal conductors 820, at least one power supply conductor 840, and at least one power supply conductive pillar 850.
  • the signal conductive post 830 is connected to the main board 810.
  • the signal wires 820 are disposed on the connection main board 810. The two ends of the signal wires 820 are electrically connected to one of the signal conductive bumps 710 and one of the signal conductive columns 830.
  • the substrate 900 is electrically connected to the signal conductive pillar 830.
  • the lengths of the individual signal conductors 820 are substantially equal.
  • each of the signal conductive bumps 710 reduces any time differences when transmitting signals.
  • one end of the power lead 840 is connected to the power conductive bump 750 and disposed adjacent to the power conductive bump 750.
  • the impedance of the power supply lead 840 can be reduced to a minimum and the transmission efficiency of the power supply signal can be improved.
  • the semiconductor connecting component used in the above embodiments of the present invention may also be a paper lead frame.
  • a carrier 19 is provided, which in this embodiment is a copper piece.
  • a patterned first conductive layer 20 is formed on the carrier 19.
  • a photoresist layer 25 is formed, and the photoresist layer 25 is patterned to leave a hole 27'.
  • a second conductive layer 27 is formed in the hole 27, a second conductive layer 27 is formed.
  • it is formed by electroplating, which is substantially flat and does not protrude from the surface of the photoresist layer 25.
  • the photoresist layer 25 is removed to obtain a patterned first conductive layer 20 and a second conductive layer 27.
  • a first insulating layer 28 is formed by filling a mold with a molding material to embed the patterned first conductive layer 20 and the second conductive layer 27 in the first insulating layer 28.
  • the molding material used for this first insulating layer 28, which in this embodiment is an epoxy resin, has a characteristic of an elastic modulus of more than 1.0 GPa and a CTE value of less than 10 ppm.
  • the carrier 19 is removed by etching to obtain a semiconductor connecting component before packaging.
  • the package structure disclosed in the above embodiments of the present invention has a plurality of advantages through the design of the semiconductor connection element, and only some of the advantages described below are as follows:
  • the first conductive bump, the signal conductor, the signal conductive pillar and the conductive solder ball form a signal transmission path
  • the second conductive bump, the signal conductor, the signal conductive pillar and the conductive solder ball also form another signal transmission path. Therefore, the substrate can simultaneously form a signal communication path with the first semiconductor element and the second semiconductor element.
  • the third U-turn structure extends the distance between the midpoint M and the two end points of the line segment of the signal conductor, so that part of the signal conductive pillars are arranged along a fifth extension line, and part of the signal conductive pillars are arranged along a sixth extension line,
  • the spacing between the five extension lines and the sixth extension line is greater than the spacing between the first extension line and the third extension line, and is greater than the spacing between the second extension line and the fourth extension line.
  • the semiconductor connection component can be formed in a single layer circuit structure to enable the first semiconductor component and The signal transmission path of the second semiconductor element and the substrate does not require a complicated multilayer circuit structure. This significantly reduces manufacturing and material costs.
  • the number of power supply wires can be reduced, and the length of the power supply wires can be shortened.
  • the impedance of the power supply conductor can be reduced to a minimum and the transmission of the power signal can be improved.
  • the sixth, first and second seals can also completely protect the package structure.
  • each power supply wire if one end of each power supply wire is connected to a power supply conductive bump and disposed adjacent to the power supply conductive bump, the length of each power supply wire can be minimized, so that the impedance of the power supply wire can be minimized.
  • the semiconductor connecting component is not only suitable for electrical connection of two semiconductor components, but is more suitable for electrical connection of multiple sets of semiconductor components.
  • the semiconductor connecting element can reproduce the patterns of the plurality of sets of signal wires and power wires by repeated exposure of a photomask, which is quite convenient.
  • the semiconductor connection elements may also electrically connect the plurality of semiconductor elements into one group, depending on the needs of the designer.
  • the signal transmission through the semiconductor connecting element reduces the minimum pitch of the conductive bumps of the semiconductor element.
  • the minimum spacing between the first conductive bump and the third conductive bump may be less than 100 micrometers (Microns), and the minimum spacing of the second conductive bump and the fourth conductive bump may be less than 100 micrometers.

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Abstract

本发明公开了一种封装结构，封装结构包括至少一第一半导体元件、至少一第二半导体元件、一半导体连接元件及一基板，第一半导体元件包括数个第一导电凸块。第二半导体元件包括数个第二导电凸块。半导体连接元件包括一连接主板、至少一信号导线及至少一信号导电柱。信号导线设置于连接主板上。信号导线的两端分别电性连接于第一导电凸块的其中之一及第二导电凸块的其中之一。信号导电柱电性连接于信号导线。基板电性连接于信号导电柱。其中，第一半导体元件及第二半导体元件皆为存储器芯片，且第一半导体元件及第二半导体元件的线路结构相同。根据本发明，封装结构的基板可以同时与第一半导体元件及第二半导体元件形成信号沟通路径。

Description

封装结构 技术领域
本发明涉及一种封装结构， 且特别涉及一种包含具有半导体连接元件 ( Interposer ) 的封装结构。 背景技术
半导体元件的问世， 是科技发展的重要里程碑。 其中封装工艺在半导 体技术中， 扮演者举足轻重的角色。 随着半导体元件的不断进步， 元件越 来越多元化， 封装工艺亦趋复杂。
一般而言， 半导体元件电性连接并设置于一基板上， 再通过封胶的覆 盖而完成一封装结构。 外界的信号即可通过基板传递至半导体元件的内部。
在追求 "轻、 薄、 短、 小，， 的设计下， 设计者必须将二个以上半导体 元件设置于同一基板上， 并共用同一基板。 然后再将其封装成一封装结构， 以减少产品体积。
然而， 每一半导体元件皆具有数个电性接点， 若将二个以上半导体元 件的电性接点连接于基板上时， 导线的设计将是一项相当困难的工作。
并且， 在半导体元件的电性接点的设计越来越复杂的情况下， 如何让 一个半导体元件或二个以上半导体元件的几个特定电性接点減少产生信号 传递时间上的差异， 以及如何提高电源信号的传递效率实为目前研发的一 重要方向。 发明内容
本发明涉及一种封装结构， 其利用一半导体连接元件的导线的设计， 使得封装结构的基板可以同时与第一半导体元件及第二半导体元件形成信 号沟通路径。
才艮据本发明的一方面， 提出一种封装结构。 封装结构包括至少一第一 半导体元件、 至少一第二半导体元件、 一半导体连接元件及一基板。 第一 半导体元件包括数个笫一导电凸块。 笫二半导体元件包括数个第二导电凸 块。 半导体连接元件包括一连接主板、 至少一信号导线及至少一信号导电 柱。 信号导线设置于连接主板上。 信号导线的两端分别电性连接于第一导 电凸块的其中之一及第二导电凸块的其中之一。 信号导电柱电性连接于该 信号导线。 基板电性连接于信号导电柱。 其中， 第一半导体元件及第二半 导体元件皆为存储器芯片， 且第一半导体元件及第二半导体元件的线路结 构相同。
根据本发明的另一方面， 提出一种封装结构。 封装结构包括一半导体 元件、 一半导体连接元件及一基板。 半导体元件包括至少二信号导电凸块。 半导体连接元件包括一连接主板、 至少二信号导电柱及至少二信号导线。 信号导电柱贯穿连接主板。 信号导线设置于连接主板上。 各个信号导线的 两端分别电性连接于信号导电凸块的其中之一及信号导电柱的其中之一。 其中各个信号导线的长度实质上相等。 基板电性连接于信号导电柱。
为了让本发明的上述内容能更明显易懂， 下文特举优选实施例， 并配 合所附图示， 作详细说明如下。 附图说明
图 1绘示依照本发明第一实施例的封装结构的示意图；
图 2绘示图 1的封装结构的俯视图；
图 3A绘示图 2的封装结构沿截面线 Α-Α'的剖面图；
图 3Β绘示图 2的封装结构沿截面线 Β-Β，的剖面图；
图 3C绘示图 2的封装结构沿截面线 C-C'的剖面图；
图 4绘示图 2的第一导电凸块、 信号导线、 信号导电柱及第二导电凸 块的示意图；
图 5绘示依照本发明第二实施例封装结构的俯视图；
图 6绘示依照本发明笫三实施例的封装结构的俯视图；
图 7绘示依照本发明第四实施例封装结构的俯视图； 以及
图 8 ~ 13绘示一种半导体连接元件的制造方法的示意图。 具体实施方式
第一实施例
请参照图 1 ,其绘示依照本发明第一实施例的封装结构 1000的示意图。 本实施例的封装结构 1000包括一第一半导体元件 100、 一第二半导体元件 200、 一半导体连接元件 300 ( Interposer ) (其材料包含热塑性树脂（thermo plastic )或环氧树脂 （epoxy ) )及一基板 400。 第一半导体元件 100及第二 半导体元件 200例如是存储器芯片、 处理芯片或感光芯片等。 在本实施例 中， 第一半导体元件 100及第二半导体元件 200皆为存储器芯片， 且第一 半导体元件 100及第二半导体元件 200的线路结构相同。 基板 400的材料 为一绝缘材料， 例如是玻璃纤维（FR4 )或陶瓷材料。 半导体连接元件 300 设置于第一半导体 100及基板 400之间， 且设置于第二半导体 200以及基 板 400之间。 半导体连接元件 300用以使基板 400同时电性连接至第一半 导体元件 100及第二半导体元件 200。 为了清楚说明本实施例的封装结构 1000 的细部元件， 以下以俯视图及数张沿不同截面线的剖面图详细说明如 下。 ，
请参照图 2及图 3A ~ 3C, 图 2绘示图 1的封装结构 1000的俯视图， 图 3A绘示图 2的封装结构 1000沿截面线 A-A，的剖面图， 图 3B绘示图 2 的封装结构 1000沿截面线 B-B，的剖面图， 图 3C绘示图 2的封装结构 1000 沿截面线 C-C，的剖面图。 如图 2所示， 第一半导体元件 100包括数个第一 导电凸块 110、 数个第三导电凸块 130及数个电源导电凸块 150, 第二半导 体元件 200包括数个第二导电凸块 220、数个第四导电凸块 240及数个电源 导电凸块 250。
为了清楚说明封装结构 1000的细部元件， 图 2以透视的方式呈现内部 元件。 这些第一导电凸块 110沿一第一延伸线 L1排列， 这些第二导电凸块 220沿一第二延伸线 L2排列， 这些第三导电凸块 130沿一第三延伸线 L3 排列， 这些第四导电凸块 240沿一第四延伸线 L4排列。 第一延伸线 Ll、 第 二延伸线 L2、 第三延伸线 L3及第四延伸线 L4实质上相互平行。
并且，第一延伸线 L1及第三延伸线 L3的间距实质上为 350微米 ( um )。 各个第一导电凸块 110的间距实盾上为 150微米,且各个笫三导电凸块 130 的间距实质上为 150微米。
其中， 这些第一导电凸块 110及这些第三导电凸块 130对应排列。 也 就是说， 第一导电凸块 110与对应的笫三导电凸块 130的连线 L13实质上 垂直于第一延伸线 L1及第三延伸线 13。 同样地， 这些第二导电凸块 220 及这些第四导电凸块 240对应排列。 也就是说， 笫二导电凸块 220与对应 的第四导电凸块 240的连线 L24实盾上垂直于笫二延伸线 L1及第四延伸线 以图 3A为例， 沿图 2的 A-A，截面线来看， 即可同时观看到第一导电 凸块 110及笫三导电凸块 130。
实质上， 本实施例的第一半导体元件 100及第二半导体元件 200为相 似的结构， 故笫一导电凸块 110及第三导电凸块 130的配置方式与第二导 电凸块 220及第四导电凸块 240的配置方式相似。
也就是说， 第二延伸线 L2及第四延伸线 L4的间距实质上亦为 350微 米。 各个第二导电凸块 220的间距实质上亦为 150微米， 各个笫四导电凸 块 240的间距实质上亦为 150 啟米。
如图 2所示， 就半导体连接元件 300而言， 本实施例的半导体连接元 件 300包括一连接主板 310、 数个信号导线 320、 数个电源导线 340、 数个 信号导电柱 330及数个电源导电柱 350。 信号导线 320设置于连接主板 310 上。 部分信号导线 320的两端分别电性连接于第一导电凸块 110的其中之 一及第二导电凸块 220的其中之一。 另一部分信号导线 320的两端分别电 性连接于第三导电凸块 130的其中之一及第四导电凸块 240的其中之一。
请同时参照图 2、 图 3A及图 4, 图 4绘示图 2的第一导电凸块 110、 信号导线 320、 信号导电柱 330及第二导电凸块 220的示意图。 如图 3A所 示， 信号导电柱 330贯穿连接主板 310。 基板 400通过这些信号导电柱 330 电性连接至信号导线 320。 并且， 第一导电凸块 110、 信号导线 320及信号 导电柱 330形成一信号传递路径。
同样地， 第二导电凸块 220、信号导线 320及信号导电柱 330亦可形成 另一信号传递路径。 也就是说， 第一导电凸块 110及第二导电凸块 220的 信号可一起传递至基板 400 (或者说基板 400可经由同一信号导电柱 330传 递信号至第一导电凸块 110及第二导电凸块 220 )。
如图 4所示， 信号导电柱 330电性连接于信号导线 320的一线段中点 M。 线段中点 M至信号导线 320的两端的长度 Dl、 D2实质上相等。 而由 于线段中点 M至信号导线 320的两端的长度 Dl、 D2实质上相等， 故两个 信号传递路径的长度亦相等， 使得两个信号传递之间 减少产生任何传递时 间上的差异 ( Difference in arrival time )。
如图 2所示， 在第一半导体元件 100中， 笫一导电凸块 110的左侧有 若干第三导电凸块 130, 而右侧没有其他导电凸块； 并且在第二半导体元件 200中， 第二导电凸块 220的左侧有若千第四导电凸块 140, 而右侧没有其 他导电凸块。 并且为了让第一导电凸块 110能够与第二导电凸块 220顺利 电性连接， 且为了让第三导电凸块 130能够与第四导电凸块 240顺利电性 连接， 这些第一导电凸块 110及这些第二导电凸块 220交错排列。
更详细地说， 由第一导电凸块 110开始延伸的信号导线 320,先向右延 伸， 再向下延伸， 接着再向左延伸至第二导电凸块 220, 而形成开口向左的 U型转折结构。 由第四导电凸块 240开始延伸的信号导线 320先向左延伸， 再向上延伸， 接着再向右延伸， 而形成开口向右的 U型转折结构。
其中， 为了说明方便， 在此以图 2为例作 "上、 下、 左、 右" 的文字 说明。 然而 "上、 下、 左、 右" 的文字说明并非用以局限本发明， 本领域 的技术人员均可了解， 只要将图 2转换角度， 其 "上、 下、 左、 右，， 的文 字说明亦随之改变。
上述 U型转折结构延长了信号导线 320的线段中点 M与二端点的距 离， 并且部分的信号导电柱 330沿一第五延伸线 L5排列， 部分的信号导电 柱 330沿一第六延伸线 L6排列，第五延伸线 L5及第六延伸线 L6的间距大 于第一延伸线 L1及第三延伸线 L3的间距，并大于第二延伸线 L2及第四延 伸线 L4的间距。
更详细地说，请参照图 4,本实施例的信号导线 320包括一第一子信号 导线 321、 一第二子信号导线 322及一第三子信号导线 323。 第一子信号导 线 321 的一端连接于第一导电凸块 110的其中之一。 第二子信号导线 322 的一端连接于第二导电凸块 220的其中之一，并平行于第一子信号导线 321。 笫三子信号导线 323的两端分别连接第一子信号导线 321的另一端及第二 子信号导线 322的另一端。
在本实施例中，第三子信号导线 323实质上垂直于第一子信号导线 321 及第二子信号导线 322。 也就是说， 本实施例的信号导线 320具有双直角的 U型转折结构。 同样地， 连接第三导电凸块 130及第四导电凸块 240的信 号导线 320亦具有相同的结构， 在此不再重述。
如上所述， 本实施例的半导体连接元件 300以单层电路结构即可形成 使第一半导体元件 100及第二半导体元件 200与基板 400的信号传递路径， 而不需要复杂的多层电路结构， 因而大幅降低制造与材料成本。
此外， 就电源传导路径而言， 请参照图 2, 电源导线 340串接第一半导 体元件 100的电源导电凸块 150, 并邻近这些电源导电凸块 150设置。 如此 一来， 如图 3B所示， 电源导电凸块 150、 电源导线 340及电源导电柱 350 形成一电源传递路径。 同样地， 如图 3C所示， 电源导电凸块 250、 电源导 线 340及电源导电柱 350亦形成另一电源传递路 。
一般而言， 电源信号的电流较大， 导线阻抗越低越好， 以避免导线过 热。 以电源导电凸块 150为例， 由于这些电源导电凸块 150以一条电源导 线 340串接， 如此可以减少电源导线 340的数量。 并且电源导线 340邻近 这些电源导电凸块 150设置， 亦可缩短电源导线 340的长度。 如此一来， 电源导线 340的阻抗可降至最低， 并增进电源信号的传输效率。
请再参照图 1 , 本实施例的封装结构 1000还包括一第一封胶 500及一 第二封胶 600。第一封胶 500设置于第一半导体元件 100与半导体连接元件 300之间， 以及第二半导体元件 200与半导体连接元件 300之间。 第二封胶 600设置于半导体连接元件 300及基板 400之间。
第一导电凸块 110、 第二导电凸块 220、 第三导电凸块 130 (未绘示于 图 1 )、 第四导电凸块 240 (未绘示于图 1 )、 信号导线 320及电源导线 340 均包覆于第一封胶 500内， 信号导电柱 330及电源导电柱 350则包覆于第 二封胶 600内。 因此， 封装结构 1000可以受到完整地保护。 第二实施例
请参照图 5 , 其绘示依照本发明第二实施例封装结构 2000的俯视图。 本实施例的封装结构 2000与第一实施例的封装结构 1000不同之处在于电 源导线 340a的配置方式， 其余相同之处不再重述。
如图 5所示，本实施例的半导体连接元件 300a包括数条电源导线 340a， 每一电源导线 340a的一端连接一个电源导电凸块 150或一个电源导电凸块 250, 并邻近此电源导电凸块 150或此电源导电凸块 250设置。 每一电源导 线 340a的另一端则连接于各个自的电源导电柱 350。 如此一来， 每一电源 导线 340a的长度可缩至最短， 使得电源导线 340a的阻抗可降至最低。 第三实施例
请参照图 6，其绘示依照本发明笫三实施例的封装结构 3000的俯视图。 本实施例的封装结构 3000与第二实施例的封装结构 2000不同之处在于第 一半导体元件 100的数量及第二半导体元件 200的数量， 其余相同之处不 再重述。
如图 6所示，封装结构 3000包括数个第一半导体元件 100及数个第二 半导体元件 200。这些第一半导体元件 100及这些第二半导体元件 200的数 量相同。 并且这些第一半导体元件 100及这些第二半导体元件 200——对 应。
当第一半导体元件 100及第二半导体元件 200均类似时， 半导体连接 元件 300b可以通过一个光掩模的重复曝光来复制出多组信号导线 320及电 源导线 340a的图案， 相当地方便。 第四实施例
请参照图 7， 其绘示依照本发明第四实施例封装结构 4000的俯视图。 本实施例的封装结构 4000与第一实施例的封装结构 1000不同之处在于半 导体元件 700的数量与信号导线 820及电源导线 840的配置方式， 其余相 同之处不再重述。
如图 7所示， 本实施例的封装结构 4000包括半导体元件 700、 半导体 连接元件 800及基板 900。 在本实施例中， 封装结构 4000仅包括一个半导 体元件 700。半导体元件 700包括至少二信号导电凸块 710及电源导电凸块 750。 半导体连接元件 800包括一连接主板 810、 至少二信号导电柱 830、 至少二信号导线 820、 至少一电源导线 840及至少一电源导电柱 850。 信号 导电柱 830贯穿连接主板 810。 信号导线 820设置于连接主板 810上， 各个 信号导线 820的两端分别电性连接于信号导电凸块 710的其中之一及信号 导电柱 830的其中之一。 基板 900电性连接于信号导电柱 830。
其中， 各个信号导线 820的长度（例如是图 7的长度 D41、 D42 )实质 上相等。 因此各个信号导电凸块 710在传递信号时， 减少产生任何时间上 的差异。
此外， 电源导线 840的一端连接电源导电凸块 750,并邻近电源导电凸 块 750设置。 如此一来， 电源导线 840的阻抗可降至对最低， 并提高电源 信号的传输效率。
此外， 本发明上述实施例所采用的半导体连接元件亦可以是一种纸引 线框架（ Paper Lead Frame )。为了清楚说明纸 1线框架的结构及其制造方法， 在此以一实施例并搭配图示说明如下。 请参图 8 ~ 13 ,其绘示一种半导体连接元件的制造方法的示意图。 首先 提供一载体 19, 在本实施例中， 为一铜片（Copper)。 并在载体 19上形成图 样化的第一导电层 20，。
请参图 9, 在第一导电层 20，上方， 形成一层光阻层 25, 并且图案化该 光阻层 25， 留出孔 27'。
请参图 10, 在孔 27，中， 形成第二导电层 27, 在本实施例中， 以电镀 的方式成型， 其为实质平坦状， 并未凸出该光阻层 25的表面。
请参照图 11 , 移除光阻层 25 , 得到图样化的第一导电层 20，以及第二 导电层 27。
请参图 12， 以模具填入塑模材料 (molding material)形成第一绝缘层 28， 以将图样化的第一导电层 20，以及第二导电层 27嵌入于第一绝缘层 28之 中。 此第一绝缘层 28 所使用的塑模材料， 在本实施例为环氧树脂 （epoxy resin ), 并且具有弹性模量大于 1.0 GPa的特性， 且其 CTE值小于 10 ppm 的特性。
请参照图 13, 以蚀刻方式， 移除载体 19, 得到封装前的半导体连接元 件。 本发明上述实施例所披露的封装结构， 透过半导体连接元件的设计， 使得封装结构具有多项优点， 以下仅列举部分优点说明如下：
第一、 第一导电凸块、 信号导线、 信号导电柱及导电锡球形成一信号 传递路径， 且第二导电凸块、 信号导线、 信号导电柱及导电锡球亦形成另 一信号传递路径。 因此基板可同时与第一半导体元件及第二半导体元件形 成信号沟通路径。
第二、 由于信号导电柱连接于信号导线的线段中点， 因此两传导路径 的长度实质上相同。 如此一来， 信号传递则减少产生任何传递时间上的差 异。
第三、 U型转折结构延长了信号导线的线段中点 M与二端点的距离， 因此部分的信号导电柱沿一第五延伸线排列， 部分的信号导电柱沿一第六 延伸线排列， 第五延伸线及第六延伸线的间距大于第一延伸线及第三延伸 线的间距， 并大于第二延伸线及第四延伸线的间距。
第四、 半导体连接元件以单层电路结构即可形成使第一半导体元件及 第二半导体元件与基板的信号传递路径， 而不需要复杂的多层电路结构。 因此大幅降低制造与材料成本。
第五、 若这些电源导电凸块以一条电源导线串接， 且电源导线邻近这 些电源导电凸块设置时， 可以减少电源导线的数量， 并可缩短电源导线的 长度。 如此一来， 电源导线的阻抗可降至对最低， 并提高电源信号的传输. 效率。
第六、 第一封胶及第二封胶的设置亦可完整地保护封装结构。
第七、 若每一电源导线的一端均连接一电源导电凸块， 并邻近此电源 导电凸块设置时， 每一电源导线的长度可缩至最短， 使得电源导线的阻抗 可降至最低。
第八、 半导体连接元件不仅适用于两个半导体元件的电性连接， 更适 用于多组半导体元件的电性连接。 此时半导体连接元件可以通过一个光掩 模的重复曝光来复制出多组信号导线及电源导线的图案， 相当地方便。
第九、 上述实施例虽然将两个半导体元件电性连接为一组， 然半导体 连接元件亦可将多个半导体元件电性连皆为一组， 端视设计者的需求而定。
第十、 透过半导体连接元件的信号传递， 使得半导体元件的导电凸块 的最小间距得以缩小。 以第一实施例为例， 第一导电凸块及第三导电凸块 的最小间距可小于 100微米（Microns ), 且第二导电凸块及第四导电凸块的 最小间距亦可小于 100微米。 综上所述， 虽然本发明已以优选实施例披露如上， 然其并非用以限定 本发明。 本发明所属技术领域中普通技术人员， 在不脱离本发明的精神和 范围内， 当可作各种的更动与润饰。 因此， 本发明的保护范围当视所附的 权利要求所界定者为准。

Claims

权利要求
1. 一种封装结构， 包括：
至少一第一半导体元件， 包括：
多个第一导电凸块；
至少一第二半导体元件， 包括：
多个第二导电凸块；
一半导体连接元件， 包括：
一连接主板；
至少一信号导线， 设置于该连接主板上， 该信号导线的两端分别电 性连接于该些第一导电凸块的其中之一及该些第二导电凸块的其中之一； 及
至少一信号导电柱， 电性连接于该信号导线； 以及
一基板， 电性连接于该信号导电柱。
2. 如权利要求 1所述的封装结构， 其中， 该第一半导体元件及该第二 半导体元件皆为存储器芯片。
3. 如权利要求 1所述的封装结构， 其中该第一半导体元件及该第二半 导体元件的线路结构相同。
4. 如权利要求 1所述的封装结构， 其中该半导体连接元件包括： 一由塑模材料构成的第一绝缘层；
在该第一绝缘层中， 设有由第一导电层构成的多个电性绝缘的封装导 线布局单元； 而该封装导线布局单元， 则由多个电性绝缘的封装导线所组 成；
在该第一导电层下方， 设有一第二导电层于该第一绝缘层中； 且该第 一导电层与第二导电层为电性相连。
5. 如权利要求 1所述的封装结构， 其中该信号导电柱贯穿该连接主板 并电性连接至该信号导线的一线段中点， 该线段中点至该信号导线的两端 的长度实质上相等。
6. 如权利要求 1所述的封装结构， 其中该信号导线具有一 U型转折结 构。
7. 如权利要求 3所述的封装结构， 其中该信号导线包括： 一第一子信号导线， 一端连接于该些第一导电凸块的其中之一； 一第二子信号导线， 一端连接于该些第二导电凸块的其中之一， 并平 行于该第一子信号导线； 以及
一笫三子信号导线， 两端分别连接该第一子信号导线的另一端及该第 二子信号导线的另一端。
8. 如权利要求 7所述的封装结构， 其中该第三子信号导线实质上垂直 于该第一子信号导线及该第二子信号导线。
9. 如权利要求 1所述的封装结构， 其中该些第一导电凸块沿一第一延 伸线排列， 该些第二导电凸块沿一第二延伸线排列， 该第一延伸线及该第 二延伸线实质上相互平行， 该些第一导电凸块及该些第二导电凸块交错排 列。
10. 如权利要求 9所述的封装结构，其中该第一半导体元件还包括多个 第三导电凸块， 该第二半导体元件还包括多个第四导电凸块， 该些第三导 电凸块沿一第三延伸线排列， 该些第四导电凸块沿一第四延伸线排列， 该 第一延伸线、 该第二延伸线、 该笫三延伸线及该第四延伸线实质上相互平 行， 该些第一导电凸块及该些第三导电凸块对应排列， 该些第二导电凸块 及该些第四导电凸块对应排列。
11. 如权利要求 10所述的封装结构， 其中该半导体连接元件包括多个 信号导电柱， 部分的该些信号导电柱沿一第五延伸线排列， 部分的该些信 号导电柱沿一第六延伸线排列， 该第五延伸线及该第六延伸线的间距大于 该第一延伸线及该第三延伸线的间距， 并大于该第二延伸线及该第四延伸 线的间距。
12. 如权利要求 10所述的封装结构， 其中该第一延伸线及该笫三延伸 线的间距实质上为 350微米， 且该第二延伸线及该第四延伸线的间距实质 上为 350 4敫米。
13. 如权利要求 10所述的封装结构， 其中各该第一导电凸块的间距实 质上为 150微米， 各该第二导电凸块的间距实质上为 150微米， 各该第三 导电凸块的间距实质上为 150微米，各该第四导电凸块的间距实质上为 150 微米。
14. 权利要求 1所述的封装结构，其中该信号导线及该信号导电柱的材 料为铜。
15. 如权利要求 1所述的封装结构，其中该基板为一陶瓷基板、一玻璃 纤维基板或一印刷电路板。
16. 如权利要求 1所述的封装结构，其中该封装结构包括多个第一半导 体元件及多个第二半导体元件， 该些第一半导体元件及该些第二半导体元 件的数量相同。
17. 如权利要求 1所述的封装结构，其中该第一半导体元件还包括多个 电源导电凸块， 该半导体连接元件还包括一电源导线及一电源导电柱， 该 电源导线串接该些电源导电凸块， 并邻近该些电源导电凸块设置。
18. 如权利要求 1所述的封装结构，其中该第一半导体元件还包括一电 源导电凸块， 该半导体连接元件还包括一电源导线及一电源导电柱， 该电 源导线的一端连接该电源导电凸块， 并邻近该电源导电凸块设置。
19. 如权利要求 1 所述的封装结构， 其中该连接主板的材料为绝缘材 料。
20. 如权利要求 1所述的封装结构，其中该连接主板的材料为热塑性树 脂或环氧树脂。
21. 如权利要求 1所述的封装结构， 还包括：
一第一封胶， 设置于该第一半导体元件与该半导体连接元件之间， 以 及该第二半导体元件与该半导体连接元件之间。
22. 如权利要求 21所述的封装结构， 还包括：
一第二封胶， 设置于该半导体连接元件及该基板之间。
23. 如权利要求 1所述的封装结构，其中该半导体连接元件为单层电路 结构。
24. 一种封装结构， 包括：
一半导体元件， 包括：
至少二信号导电凸块；
一半导体连接元件， 包括：
一连接主板；
至少二信号导电柱， 贯穿该连接主板； 及
至少二信号导线， 设置于该连接主板上， 各该信号导线的两端分别 电性连接于该些信号导电凸块的其中之一及该些信号导电柱的其中之一， 其中各该信号导线的长度实盾上相等； 以及 一基板， 电性连接于该些信号导电柱。
25. 如权利要求 24所述的封装结构， 其中该些信号导电凸块的最小间 距小于 100微米。
26. 权利要求 24所述的封装结构， 其中该些信号导线及该些信号导电 柱的材料为铜。
27. 如权利要求 24所述的封装结构， 其中该基板为一陶瓷基板、 一玻 璃纤维基板或一印刷电路板。
28. 如权利要求 24所述的封装结构， 其中该半导体元件还包括至少一 电源导电凸块， 该半导体连接元件还包括至少一电源导线及至少一电源导 电柱， 该电源导线的一端连接该电源导电凸块， 并邻近该电源导电凸块设 置。
29. 如权利要求 24所述的封装结构， 其中该连接主板的材料为绝缘材 料。
30. 如权利要求 24所述的封装结构， 其中该连接主板的材料为热塑性 树脂或环氧树脂。
31. 如权利要求 24所述的封装结构， 还包括：
一第一封胶， 设置于该半导体元件与该半导体连接元件之间。
32. 如权利要求 31所述的封装结构， 还包括：
一第二封胶， 设置于该半导体连接元件及该基板之间。
33. 如权利要求 24所述的封装结构， 其中该半导体连接元件为单层电 路结构。
34. 如权利要求 24所述的封装结构， 其中该半导体连接元件包括： 一由塑模材料构成的第一绝缘层；
在该第一绝缘层中， 设有由第一导电层构成的多个电性绝缘的封装导 线布局单元； 而该封装导线布局单元， 则由多个电性绝缘的封装导线所组 成；
在该第一导电层下方， 设有一第二导电层于该第一绝缘层中； 且该第 一导电层与第二导电层为电性相连。
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