CN102891131A - 用于制造半导体封装元件的半导体结构及其制造方法 - Google Patents
用于制造半导体封装元件的半导体结构及其制造方法 Download PDFInfo
- Publication number
- CN102891131A CN102891131A CN2012102568566A CN201210256856A CN102891131A CN 102891131 A CN102891131 A CN 102891131A CN 2012102568566 A CN2012102568566 A CN 2012102568566A CN 201210256856 A CN201210256856 A CN 201210256856A CN 102891131 A CN102891131 A CN 102891131A
- Authority
- CN
- China
- Prior art keywords
- layer
- support plate
- semiconductor
- encapsulated element
- manufacture method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/85447—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/20—Parameters
- H01L2924/207—Diameter ranges
Abstract
本发明公开一种用于制造半导体封装元件的半导体结构及其制造方法。半导体结构包括一载板。载板具有相对的一第一表面与一第二表面,载板包括一内层(inner layer)及一外披覆层(exterior clad layer),外披覆层包覆内层。
Description
技术领域
本发明涉及一种半导体结构及其制造方法,且特别是涉及一种用于制造半导体封装元件的半导体结构及其制造方法。
背景技术
传统的半导体封装元件例如包括基板、导线、环氧树脂封装层及芯片。基板的材质例如是铜,用以承载芯片,芯片与导线电连接,环氧树脂封装层包覆导线与芯片。
然而,基板整体材质都以铜来制作时,其成本较高,且容易发生翘曲。并且,环氧树脂封装层与导线之间的密封性不佳,常产生后续蚀刻制作工艺中的蚀刻液露出而破坏导线的问题。因此,为了因应上述问题而提出解决方法实为必要的。
发明内容
本发明的目的在于提供一种半导体结构及其制造方法。半导体结构中,载板的外披覆层包覆内层,可于后续蚀刻步骤中提供较佳的蚀刻阻隔,并且,导线层埋设于绝缘层中,可以防止导线层在后续的蚀刻制作工艺中受到蚀刻液的破坏。
为达上述目的,根据本发明的一方面,提出一种用于制造半导体封装元件的半导体结构。半导体结构包括一载板。载板具有相对的一第一表面与一第二表面,载板包括一内层及一外披覆层,外披覆层包覆内层。
根据本发明的另一方面,提出一种半导体封装元件的制造方法。半导体封装元件的制造方法包括:提供一载板,载板具有相对的一第一表面与一第二表面,载板包括一内层及一外披覆层,外披覆层包覆内层;形成一导线层于载板的第一表面上;以及形成一绝缘层于载板上且暴露出导线层。
为让本发明的上述内容能更明显易懂,下文特举较佳实施例,并配合所 附附图,作详细说明如下:
附图说明
图1A为本发明一实施例的半导体结构的剖视图;
图1B为本发明另一实施例的半导体结构的剖视图;
图1C为本发明再一实施例的半导体结构的剖视图;
图2A为本发明一实施例的半导体封装元件的剖视图;
图2B为本发明另一实施例的半导体封装元件的剖视图;
图2C为本发明再一实施例的半导体封装元件的剖视图;
图3A至图3G为本发明一实施例的半导体封装元件的制造方法的流程图;
图4A至图4C为本发明另一实施例的半导体封装元件的制造方法的流程图;
图5A至图5D为本发明一实施例的移除载板的制作工艺步骤的流程图;
图6为本发明另一实施例的移除载板的制作工艺步骤的流程图;
图7为本发明更一实施例的移除载板的制作工艺步骤的流程图。
主要元件符号说明
10A、10B、10C:半导体结构
110:载板
110a、130a:第一表面
110b、130b:第二表面
111:内层
113:外披覆层
120:导线层
121:导电层
123:阻障层
125:保护层
130:绝缘层
130’:绝缘材料层
140:半导体芯片
150:连接元件
160:封装层
170:粘着层
20A、20B、20C、20D:半导体封装元件
T1、T2、T3:厚度
具体实施方式
请参照图1A。图1A绘示依照本发明一实施例的半导体结构的剖视图。半导体结构10A包括载板110以及导线层120。载板110具有相对的第一表面110a与第二表面110b,载板110包括内层111(inner layer)及外披覆层113(exterior clad layer),外披覆层113包覆内层111。
实施例中,内层111的厚度例如是大约200微米,外披覆层113的厚度例如是5~20微米。实施例中,内层111的厚度相对于外披覆层113的厚度的一比例例如是大于10。
实施例中,内层111包括一第一金属,第一金属的材质例如是钢,或是包括铁、碳、镁、磷、硫、铬及镍其中两种以上的合金,或是不锈钢合金。一实施例中,内层111的材质例如是具有以下组成的合金:97%以上的铁、小于或等于0.12%的碳、小于或等于0.5%的镁、小于或等于0.05%的磷、小于或等于0.05%的硫、小于或等于0.2%的铬及小于或等于0.2%的镍,其中碳和镍的百分比最低可以为0%。另一实施例中,内层111的材质例如包括导电金属材料。
实施例中,外披覆层113包括一第二金属,第二金属的材质例如是铜,其材质与第一金属的材质为不相同。在后续的半导体制作工艺中,可于移除载板110的蚀刻步骤中,利用外披覆层113的材质与内层111的材质不相同,从而提供较佳的蚀刻阻隔。并且,外披覆层113的材质例如是铜时,使得载板110可以被视作一个完整的铜层来操作应用,并且能够降低整体制作成本。另一实施例中,外披覆层113的材质例如包括导电金属材料。
载板110的热膨胀系数(CTE)和模数(modulus)取决于内层111的热膨胀系数(CTE)和模数(modulus)。实施例中,内层111的第一金属的热膨胀系数(CTE)介于约10至15ppm/°C,此热膨胀系数接近用以包覆半导体芯片的封装材料的热膨胀系数,可以使得应用载板110而制成的半导体封装元件的翘 曲量减少,可容许载板110的面积增大,在此情况下,可在载板110上形成更多数量的半导体封装元件。实施例中,内层111的第一金属的模数(modulus)介于约150至250GPa,载板110坚固的特性有利于后续的制作工艺操作。
如图1A所示,半导体结构10A可包括绝缘层130,绝缘层130形成于载板110上。实施例中,绝缘层130形成于载板110的第一表面110a上。实施例中,绝缘层130例如是树脂(resin)材料,树脂材料的热膨胀系数介于约10至15ppm/°C,其与载板110的热膨胀系数的差值小于3ppm/°C。一实施例中,绝缘层130的材质例如是有机树脂材料。另一实施例中,绝缘层130的材质例如包括环氧树脂及氧化硅填料(silica fillers)。
如图1A所示,导线层120埋设于绝缘层130中。导线层120埋设于绝缘层130中可以防止导线层120在后续的蚀刻制作工艺中受到蚀刻液的破坏。
实施例中,绝缘层130具有一第一表面邻接于载板110以及一第二表面相对于第一表面,导线层120埋设于绝缘层130的第一表面和第二表面之间,导线层120连接绝缘层130的第一表面和第二表面。
实施例中,部分导线层120暴露于绝缘层130之外。实施例中,外披覆层113的材质例如是铜,导线层120的材质例如是和外披覆层113的材质为相同。
请参照图1B。图1B绘示依照本发明另一实施例的半导体结构的剖视图。本实施例与图1A的实施例的差别在于,半导体结构10B中,导线层120包括一导电层121和一阻障层123,导电层121形成于110载板上,阻障层123形成载板110与导电层121之间。
实施例中,导电层121的材质例如是铜,阻障层123的材质例如包括镍、金或锡。实施例中,导电层121的厚度例如是大约15微米,阻障层123的厚度例如是大约5微米。
请参照图1C。图1C绘示依照本发明再一实施例的半导体结构的剖视图。本实施例与图1B的实施例的差别在于,半导体结构10C中,导线层120还包括一保护层125,保护层125形成于载板110上且位于载板110与阻障层123之间。
实施例中,保护层125的材质例如是铜,保护层125的材质与外披覆层113的材质例如相同。实施例中,保护层125的厚度例如是大约5微米。
请参照图2A。图2A绘示依照本发明一实施例的半导体封装元件的剖视图。半导体封装元件20A包括导线层120、绝缘层130以及半导体芯片140。导线层120埋设于绝缘层130中,半导体芯片140设置于绝缘层130上。实施例中,半导体芯片140电连接导线层120。
实施例中,导线层120埋设于绝缘层130中,可以防止导线层120在后续的蚀刻制作工艺中受到蚀刻液的破坏。
如图2A所示,半导体封装元件20A可包括连接元件150,连接元件150电连接半导体芯片140与导线层120。
请参照图2B。图2B绘示依照本发明另一实施例的半导体封装元件的剖视图。本实施例与图2A的实施例的差别在于,半导体封装元件20B中还可包括封装层160,封装层160包覆半导体芯片140。
请参照图2C。图2C绘示依照本发明再一实施例的半导体封装元件的剖视图。本实施例与图2A的实施例的差别在于,半导体封装元件20C中,导线层120包括一导电层121和一阻障层123。导电层121和阻障层123的材质、厚度及配置关系如前述实施例所述,在此不再赘述。部分阻障层123暴露于绝缘层130之外,以利于将半导体封装元件20C焊接到其他外部元件,例如基板。
请参照图3A至图3G。图3A至图3G绘示依照本发明一实施例的半导体封装元件的制造方法的流程图。
请参照图3A,提供载板110。载板110具有相对的第一表面110a与第二表面110b,载板110包括内层111及外披覆层113,外披覆层113包覆内层111。外披覆层113和内层111的材质如前述实施例所述,在此不再赘述。
实施例中,载板110的制造方式例如包括以下步骤:提供内层111;清洁(degreasing)内层111的表面;抛光(buffing)内层111的表面;以及形成外披覆层113。
实施例中,清洁内层111的表面例如是移除表面残留或不必要的化学物质(chemical)以及微粒,将内层111的表面清洁干净,用以提升内层111与外披覆层113的粘着性。实施例中,抛光内层111的表面例如是移除表面的缺陷,例如是刮痕(scratches)或凹陷(pits),以形成均匀的表面。接着,例如是以电解电镀(electrolytic plating)或无电解电镀(electroless plating)形成外披覆层113。实施例中,形成外披覆层113之前,可先形成一晶种电镀层(seed plating layer),有助于外披覆层113的电镀成长。
请参照图3B,形成导线层120于载板110的第一表面110a上。
一实施例中,形成导线层120的步骤例如包括:形成一阻障层123于载板110上,以及形成一导电层121于阻障层123上(请参照图1B)。另一实施例中,形成导线层120的步骤例如包括:形成一保护层125于载板110上、形成一阻障层123于保护层125上以及形成一导电层121于阻障层123上(请参照图1C)。
实施例中,例如是以图案化电解电镀(patterned electrolytic plating)方式形成导线层120于载板110上。实施例中,例如是以全加成法(full additive processing)、半加成法(semi-additive processing)或全减成法(full subtractive processing)方式形成导线层120于载板110上,并且上述形成步骤可以重复进行,以形成多层导线层120或具有多层结构的导线层120。
请参照图3C,形成绝缘材料层130’于载板110上且包覆导线层120。实施例中,绝缘材料层130’形成于载板110的第一表面110a上,并且完全包覆导线层120。一实施例中,例如是以一热压膜制(molding)方式形成绝缘材料层130’于载板110上。在高温高压下进行热压膜制,使得绝缘层130与导线之间的密封性好,在后续蚀刻制作工艺中导线不会被破坏。另一实施例中,例如是以贴合(lamination)或旋转涂布(spin-coating)树脂材料的方式形成绝缘材料层130’于载板110上。
请参照图3D,薄化绝缘材料层130’以形成绝缘层130并暴露出导线层120。绝缘层130具有相对的第一表面130a与第二表面130b,绝缘层130的第一表面130a邻接载板110的第一表面110a。实施例中,例如是自载板110的第一表面110a侧研磨绝缘材料层130’以形成绝缘层130,使导线层120的一部分自绝缘层130的第二表面130b暴露出来。
请参照图3E,移除载板110。实施例中,例如是蚀刻方式移除载板110。此时,导线层120的另一部分自绝缘层130的第一表面130a暴露出来。由此形成的半导体结构,导线层120完全埋设于绝缘层130中。
请参照图3F,设置半导体芯片140于绝缘层130上。实施例中,设置半导体芯片140于绝缘层130的第一表面130a上。如图3F所示,可形成连接元件150及粘着层170,连接元件150电连接半导体芯片140与导线层120,半导体芯片140经由粘着层170设置于绝缘层130上。
请参照图3G,形成封装层160。封装层160包覆半导体芯片140。如图3G所示,封装层160包覆导线层120、半导体芯片140、连接元件150、粘着层170及部分绝缘层130的第一表面130a。至此,形成如图3G所示的半导体封装元件20D。
请同时参照图3A至图3D及图4A至图4C。图4A至图4C绘示依照本发明另一实施例的半导体封装元件的制造方法的流程图。本实施例中与前述实施例相同的元件沿用同样的元件标号,且相同元件的相关说明请参考前述,在此不再赘述。
首先,如图3A至图3D所示,提供载板110、形成导线层120于载板110的第一表面110a上、形成绝缘材料层130’于载板110上且包覆导线层120、以及薄化绝缘材料层130’以形成绝缘层130并暴露出导线层120。
请参照图4A,设置半导体芯片140于绝缘层130上。实施例中,设置半导体芯片140于绝缘层130的第二表面130b上。如图4A所示,可形成连接元件150及粘着层170,连接元件150电连接半导体芯片140与导线层120,半导体芯片140经由粘着层170设置于绝缘层130上。
请参照图4B,形成封装层160。封装层160包覆半导体芯片140。如图4B所示,封装层160包覆导线层120、半导体芯片140、连接元件150、粘着层170及部分绝缘层130的第二表面130b。
请参照图4C,移除载板110。实施例中,例如是蚀刻方式移除载板110。此时,导线层120的一部分自绝缘层130的第一表面130a暴露出来。至此,形成如图4C(图2B)所示的半导体封装元件20B。
请参照图5A至图5D。图5A至图5D绘示依照本发明一实施例的移除载板的制作工艺步骤的流程图。本实施例中与前述实施例相同的元件沿用同样的元件标号,且相同元件的相关说明请参考前述,在此不再赘述。
请参照图5A,导线层120及绝缘层130设置于载板110的第一表面110a上。导线层120埋设于该绝缘层130中。请参照图5B,以第一蚀刻液蚀刻载板110,以移除位于载板110的第二表面110b的部分外披覆层113及部分内层111。
实施例中,第一蚀刻液例如包括氯化铁或氯化氢。
实施例中,第一蚀刻液对内层111的蚀刻速率大约大于20微米/分钟(μm/min),蚀刻之后残留的部分内层111具有的厚度T1大约是20微米。
请参照图5C,以第二蚀刻液蚀刻载板110,以移除载板110的残留的内层111,并曝露位于载板110的第一表面110a的部分外披覆层113。
实施例中,第二蚀刻液对内层111及外披覆层113的蚀刻速率比大约大于5。实施例中,第二蚀刻液例如包括硫酸或过氧化氢。
实施例中,第二蚀刻液对外披覆层113的蚀刻速率约小于1微米/分钟,第二蚀刻液对内层111的蚀刻速率约大于5微米/分钟,蚀刻之后残留的部分外披覆层113具有的厚度T2大约是3微米。如此一来,内层111实质上被蚀刻而完全移除,以第二蚀刻液对内层111及外披覆层113的蚀刻速率差距来降低第二蚀刻液对于外披覆层113蚀刻的程度,残留的部分外披覆层113可具有相对平整的表面,并且防止过度蚀刻对导线层带来的损害。
请参照图5D,利用在第二蚀刻步骤中所达到的外披覆层113的平整的表面,以第三蚀刻液蚀刻载板110,移除位于载板110的第一表面110a的残留的部分外披覆层113并曝露导线层120。
实施例中,第三蚀刻液例如包括氯化铵或氨。实施例中,第三蚀刻液对外披覆层113的蚀刻速率约小于5微米/分钟(μm/min)。蚀刻后暴露出的导线层120具有相对平整的表面。
另一实施例中,以第三蚀刻液蚀刻载板110同时也蚀刻大约3至5微米导线层120,使得导线层120的表面低于绝缘层130的第一表面130a。
如前所述,以包括内层111及外披覆层113的载板110结构结合三个蚀刻液分别进行三次蚀刻步骤以移除载板110,如此一来,可以针对不同膜层的特性分别调整各个蚀刻液的组成及蚀刻速率,可以提高对于整个蚀刻制作工艺的控制作工艺度,并且使得蚀刻后暴露出的导线层120的表面更加平整。
请同时参照图5A至图5C及图6。图6绘示依照本发明另一实施例的移除载板的制作工艺步骤的流程图。本实施例中与前述实施例相同的元件沿用同样的元件标号,且相同元件的相关说明请参考前述,在此不再赘述。
首先,如图5A至图5C所示,以第一蚀刻液蚀刻载板110以移除位于载板110的第二表面110b的部分外披覆层113及部分内层111,以及以第二蚀刻液蚀刻载板110,以移除载板110的内层111并曝露位于载板110的第一表面110a的部分外披覆层113。
接着,请参照图6,以第三蚀刻液蚀刻载板110,以移除位于载板110的第一表面110a的部分外披覆层113并曝露导线层120。实施例中,导线层 120包括一导电层121及阻障层123,阻障层123位于载板110与导电层121之间,蚀刻后曝露出阻障层123。
实施例中,第二蚀刻液对外披覆层113的蚀刻速率约为5微米/分钟,第二蚀刻液对内层111的蚀刻速率约大于20微米/分钟,蚀刻之后残留的部分外披覆层113具有的厚度大约是3微米。如此一来,内层111实质上被蚀刻而完全移除,残留的部分外披覆层113可具有相对平整的表面。实施例中,第三蚀刻液对阻障层123的蚀刻速率约小于1微米/分钟,第三蚀刻液对外披覆层113的蚀刻速率约小于5微米/分钟,蚀刻之后的阻障层123具有的厚度大约是3微米。如此一来,利用第三蚀刻液对阻障层123和外披覆层113的蚀刻速率差距,可以阻挡第二蚀刻液对于导电层121可能造成破坏。
请同时参照图5A至图5C及图7。图7绘示依照本发明更一实施例的移除载板的制作工艺步骤的流程图。本实施例中与前述实施例相同的元件沿用同样的元件标号,且相同元件的相关说明请参考前述,在此不再赘述。
首先,如图5A至图5C所示,以第一蚀刻液蚀刻载板110以移除位于载板110的第二表面110b的部分外披覆层113及部分内层111,以及以第二蚀刻液蚀刻载板110,以移除载板110的内层111并曝露位于载板110的第一表面110a的部分外披覆层113。
接着,请参照图7,以第三蚀刻液蚀刻载板110,以移除位于载板110的第一表面110a的部分外披覆层113并曝露导线层120。实施例中,导线层120包括一导电层121、一阻障层123及一保护层125,阻障层123位于载板110与导电层121之间,保护层125位于载板110与阻障层123之间。如图7所示,保护层125的材质与外披覆层113的材质例如是相同,以第三蚀刻液蚀刻载板110时也蚀刻保护层125,蚀刻后暴露出阻障层123。
实施例中,第三蚀刻液对外披覆层113的蚀刻速率约小于5微米/分钟,第三蚀刻液对阻障层123的蚀刻速率约小于1微米/分钟,蚀刻之后的阻障层123具有的厚度T3大约是3微米。
实施例中,蚀刻后保护层125实质上被蚀刻而完全移除,暴露出的阻障层123可具有相对平整的表面,使得导线层120的表面低于绝缘层130的第一表面130a。
综上所述,虽然结合以上实施例揭露了本发明,然而其并非用以限定本发明。本发明所属技术领域中熟悉此技术者,在不脱离本发明的精神和范围 内,可作各种的更动与润饰。因此,本发明的保护范围应以附上的权利要求所界定的为准。
Claims (46)
1.一种用于制造半导体封装元件的半导体结构,包括:
载板,具有相对的第一表面与第二表面,包括内层(inner layer)及外披覆层(exterior clad layer),该外披覆层包覆该内层。
2.如权利要求1所述的用于制造半导体封装元件的半导体结构,其中该内层包括第一金属,该外披覆层包括第二金属。
3.如权利要求2所述的用于制造半导体封装元件的半导体结构,其中该第一金属包括铁,该第二金属包括铜。
4.如权利要求3所述的用于制造半导体封装元件的半导体结构,其中该第一金属为一合金,该第一金属还包括碳、镁、磷、硫、铬或镍。
5.如权利要求4所述的用于制造半导体封装元件的半导体结构,其中该第一金属为一不锈钢合金。
6.如权利要求2所述的用于制造半导体封装元件的半导体结构,其中该第一金属具有一热膨胀系数(CTE)为10至15ppm/°C。
7.如权利要求2所述的用于制造半导体封装元件的半导体结构,其中该第一金属具有一模数(modulus)为150至250GPa。
8.如权利要求1所述的用于制造半导体封装元件的半导体结构,其中该内层的厚度相对于该外披覆层的厚度的一比例为大于10。
9.如权利要求1所述的用于制造半导体封装元件的半导体结构,还包括导线层,形成于该载板的该第一表面上。
10.如权利要求9所述的用于制造半导体封装元件的半导体结构,还包括绝缘层,形成于该载板上。
11.如权利要求10所述的用于制造半导体封装元件的半导体结构,其中该导线层埋设于该绝缘层中。
12.如权利要求11所述的用于制造半导体封装元件的半导体结构,其中该绝缘层为一树脂(resin)材料,该树脂材料具有一热膨胀系数(CTE)为10至15ppm/°C。
13.如权利要求11所述的用于制造半导体封装元件的半导体结构,其中该载板与该绝缘层的热膨胀系数差值为小于3ppm/°C。
14.如权利要求11所述的用于制造半导体封装元件的半导体结构,其中该绝缘层具有第一表面,邻接于该载板;以及第二表面,相对于该第一表面,该导线层埋设于该第一表面和该第二表面之间,该导线层连接该第一表面和该第二表面。
15.如权利要求9所述的半导体结构,其中该导线层包括导电层,形成于该载板上。
16.如权利要求15所述的半导体结构,其中该导线层还包括阻障层,形成该载板与该导电层之间。
17.如权利要求16所述的半导体结构,其中该导线层还包括保护层,形成于该载板上且位于该载板与该阻障层之间。
18.如权利要求17所述的半导体结构,其中该保护层的材质与该外披覆层的材质为相同。
19.一种半导体封装元件的制造方法,包括:
提供一载板,该载板具有相对的第一表面与第二表面,该载板包括内层(inner layer)及外披覆层(exterior clad layer),该外披覆层包覆该内层;
形成一导线层于该载板的该第一表面上;以及
形成一绝缘层于该载板上且暴露出该导线层。
20.如权利要求19所述的半导体封装元件的制造方法,其中该内层包括第一金属,该外披覆层包括第二金属。
21.如权利要求20所述的半导体封装元件的制造方法,其中该第一金属包括铁,该第二金属包括铜。
22.如权利要求21所述的半导体封装元件的制造方法,其中该第一金属为一合金,该第一金属还包括碳、镁、磷、硫、铬或镍。
23.如权利要求22所述的半导体封装元件的制造方法,其中该第一金属为一不锈钢合金。
24.如权利要求20所述的半导体封装元件的制造方法,其中该第一金属具有一热膨胀系数(CTE)为10至15ppm/°C。
25.如权利要求20所述的半导体封装元件的制造方法,其中该第一金属具有一模数(modulus)为150至250GPa。
26.如权利要求19所述的半导体封装元件的制造方法,其中该内层的厚度相对于该外披覆层的厚度的一比例为大于10。
27.如权利要求19所述的半导体封装元件的制造方法,其中该导线层埋设于该绝缘层中。
28.如权利要求19所述的半导体封装元件的制造方法,其中该绝缘层为一树脂(resin)材料,该树脂材料具有一热膨胀系数(CTE)为10至15ppm/°C。
29.如权利要求19所述的半导体封装元件的制造方法,其中该载板与该绝缘层的热膨胀系数差值为小于3ppm/°C。
30.如权利要求19所述的半导体封装元件的制造方法,其中该绝缘层具有第一表面,邻接于该载板;以及第二表面,相对于该第一表面,其中该导线层埋设于该第一表面和该第二表面之间,该导线层连接该第一表面和该第二表面。
31.如权利要求19所述的半导体封装元件的制造方法,其中形成该绝缘层于该载板上且暴露出该导线层的步骤包括:
形成一绝缘材料层于该载板上且包覆该导线层;以及
薄化该绝缘材料层以形成该绝缘层并暴露出该导线层。
32.如权利要求19所述的半导体封装元件的制造方法,还包括移除该载板。
33.如权利要求32所述的半导体封装元件的制造方法,其中移除该载板的步骤包括:
以一第一蚀刻液蚀刻该载板,以移除位于该载板的该第二表面的该外披覆层及部分该内层;
以一第二蚀刻液蚀刻该载板,以移除该载板的残留的该内层并曝露位于该载板的该第一表面的该外披覆层;以及
以一第三蚀刻液蚀刻该载板,以移除位于该载板的该第一表面的残留的该外披覆层并曝露该导线层及该绝缘层的一表面。
34.如权利要求33所述的半导体封装元件的制造方法,其中该第一蚀刻液对该外披覆层及该内层的蚀刻速率比为1。
35.如权利要求33所述的半导体封装元件的制造方法,其中该第一蚀刻液对该内层的蚀刻速率为大于20微米/分钟。
36.如权利要求33所述的半导体封装元件的制造方法,其中该第一蚀刻液包括氯化铁或氯化氢。
37.如权利要求33所述的半导体封装元件的制造方法,其中该第二蚀刻液对该内层及该外披覆层的蚀刻速率比为大于5。
38.如权利要求33所述的半导体封装元件的制造方法,其中该第二蚀刻液包括硫酸或过氧化氢。
39.如权利要求33所述的半导体封装元件的制造方法,其中该第三蚀刻液对该外披覆层的蚀刻速率为小于5微米/分钟。
40.如权利要求33所述的半导体封装元件的制造方法,其中该第三蚀刻液包括氯化铵或氨。
41.如权利要求33所述的半导体封装元件的制造方法,其中形成该导线层于该载板的该第一表面上的步骤包括:
形成一导电层于该载板上;以及
形成一阻障层于该载板与该导电层之间,其中该第二蚀刻液对该内层及该阻障层的蚀刻速率比为大于或等于5。
42.如权利要求33所述的半导体封装元件的制造方法,其中形成该导线层于该载板的该第一表面上的步骤包括:
形成一导电层于该载板上;以及
形成一阻障层于该载板与该导电层之间,其中该第三蚀刻液对该外披覆层及该阻障层的蚀刻速率比为大于或等于5。
43.如权利要求33所述的半导体封装元件的制造方法,其中形成该导线层于该载板的该第一表面上的步骤包括:
形成一保护层于该载板上;
形成一阻障层于该保护层上;以及
形成一导电层于该阻障层上;
其中在移除该载板后,同时移除该保护层,该导线层低于该绝缘层的该表面。
44.如权利要求19所述的半导体封装元件的制造方法,还包括设置一半导体芯片于该绝缘层上。
45.如权利要求44所述的半导体封装元件,还包括形成一连接元件,该连接元件电连接该半导体芯片与该导线层。
46.如权利要求45所述的半导体封装元件的制造方法,还包括形成一封装层,该封装层包覆该半导体芯片。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201710475466.0A CN107369668B (zh) | 2011-07-22 | 2012-07-23 | 用于制造半导体封装元件的半导体结构 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201161510494P | 2011-07-22 | 2011-07-22 | |
US61/510,494 | 2011-07-22 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201710475466.0A Division CN107369668B (zh) | 2011-07-22 | 2012-07-23 | 用于制造半导体封装元件的半导体结构 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN102891131A true CN102891131A (zh) | 2013-01-23 |
CN102891131B CN102891131B (zh) | 2017-07-14 |
Family
ID=47534593
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201710475466.0A Active CN107369668B (zh) | 2011-07-22 | 2012-07-23 | 用于制造半导体封装元件的半导体结构 |
CN201210256856.6A Active CN102891131B (zh) | 2011-07-22 | 2012-07-23 | 用于制造半导体封装元件的半导体结构及其制造方法 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201710475466.0A Active CN107369668B (zh) | 2011-07-22 | 2012-07-23 | 用于制造半导体封装元件的半导体结构 |
Country Status (3)
Country | Link |
---|---|
US (2) | US10109503B2 (zh) |
CN (2) | CN107369668B (zh) |
TW (1) | TWI601250B (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104701185A (zh) * | 2013-12-06 | 2015-06-10 | 富葵精密组件(深圳)有限公司 | 封装基板、封装结构以及封装基板的制作方法 |
CN107112289A (zh) * | 2014-12-25 | 2017-08-29 | 友立材料株式会社 | 半导体装置用基板、半导体装置用布线构件及它们的制造方法、以及利用半导体装置用基板进行的半导体装置的制造方法 |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102007034402B4 (de) * | 2006-12-14 | 2014-06-18 | Advanpack Solutions Pte. Ltd. | Halbleiterpackung und Herstellungsverfahren dafür |
US10109503B2 (en) | 2011-07-22 | 2018-10-23 | Advanpack Solutions Pte Ltd. | Method of manufacturing semiconductor package device |
CN202948918U (zh) | 2011-10-20 | 2013-05-22 | 先进封装技术私人有限公司 | 封装基板及半导体元件的封装结构 |
US9301391B2 (en) * | 2011-11-29 | 2016-03-29 | Advanpack Solutions Pte Ltd. | Substrate structure, semiconductor package device, and manufacturing method of substrate structure |
US9177899B2 (en) | 2012-07-31 | 2015-11-03 | Mediatek Inc. | Semiconductor package and method for fabricating base for semiconductor package |
US10991669B2 (en) | 2012-07-31 | 2021-04-27 | Mediatek Inc. | Semiconductor package using flip-chip technology |
TWI562295B (en) | 2012-07-31 | 2016-12-11 | Mediatek Inc | Semiconductor package and method for fabricating base for semiconductor package |
US9142530B2 (en) | 2013-03-21 | 2015-09-22 | Stats Chippac Ltd. | Coreless integrated circuit packaging system and method of manufacture thereof |
TWI620296B (zh) * | 2015-08-14 | 2018-04-01 | 矽品精密工業股份有限公司 | 電子封裝件及其製法 |
US20170084519A1 (en) * | 2015-09-22 | 2017-03-23 | Freescale Semiconductor, Inc. | Semiconductor package and method of manufacturing same |
MY181637A (en) * | 2016-03-31 | 2020-12-30 | Qdos Flexcircuits Sdn Bhd | Single layer integrated circuit package |
US20210074621A1 (en) * | 2019-09-10 | 2021-03-11 | Amazing Microelectronic Corp. | Semiconductor package |
WO2021100366A1 (ja) * | 2019-11-19 | 2021-05-27 | コニカミノルタ株式会社 | 電子デバイス、硫化防止剤及び封止材 |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020037647A1 (en) * | 1998-01-13 | 2002-03-28 | Hwang Jeng H. | Method of etching an anisotropic profile in platinum |
US20020168542A1 (en) * | 2001-03-16 | 2002-11-14 | Izbicki Anthony John | Composite metals and method of making |
US20030104770A1 (en) * | 2001-04-30 | 2003-06-05 | Arch Specialty Chemicals, Inc. | Chemical mechanical polishing slurry composition for polishing conductive and non-conductive layers on semiconductor wafers |
US20030232205A1 (en) * | 2002-06-14 | 2003-12-18 | Nobuyoshi Tsukaguchi | Metal/ceramic bonding article and method for producing same |
CN1764739A (zh) * | 2003-03-25 | 2006-04-26 | 埃托特克德国有限公司 | 用于蚀刻铜表面的溶液和在铜表面上沉积金属的方法 |
US20060145363A1 (en) * | 2003-02-21 | 2006-07-06 | Dai Nippon Printing Co., Ltd. | Semiconductor device fabricating apparatus and semiconductor device fabricating method |
US20070120229A1 (en) * | 2001-02-16 | 2007-05-31 | Dai Nippon Printing Co., Ltd. | Wet etched insulator and electronic circuit component |
CN101241861A (zh) * | 2006-06-01 | 2008-08-13 | Amitec多层互连技术有限公司 | 新型多层无芯支撑结构及其制作方法 |
US20090209064A1 (en) * | 2006-04-28 | 2009-08-20 | Somchai Nonahasitthichai | Lead frame land grid array |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5780315A (en) * | 1995-09-11 | 1998-07-14 | Taiwan Semiconductor Manufacturing Company, Ltd | Dry etch endpoint method |
US5985765A (en) * | 1998-05-11 | 1999-11-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for reducing bonding pad loss using a capping layer when etching bonding pad passivation openings |
KR100480772B1 (ko) * | 2000-01-05 | 2005-04-06 | 삼성에스디아이 주식회사 | 나노 스케일의 표면 거칠기를 가지는 마이크로 구조물의형성방법 |
JP2001338947A (ja) | 2000-05-26 | 2001-12-07 | Nec Corp | フリップチップ型半導体装置及びその製造方法 |
US6969945B2 (en) * | 2001-02-06 | 2005-11-29 | Matsushita Electric Industrial Co., Ltd. | Surface acoustic wave device, method for manufacturing, and electronic circuit device |
US6946205B2 (en) * | 2002-04-25 | 2005-09-20 | Matsushita Electric Industrial Co., Ltd. | Wiring transfer sheet and method for producing the same, and wiring board and method for producing the same |
US7474538B2 (en) | 2002-05-27 | 2009-01-06 | Nec Corporation | Semiconductor device mounting board, method of manufacturing the same, method of inspecting the same, and semiconductor package |
JP3591524B2 (ja) | 2002-05-27 | 2004-11-24 | 日本電気株式会社 | 半導体装置搭載基板とその製造方法およびその基板検査法、並びに半導体パッケージ |
US7582556B2 (en) | 2005-06-24 | 2009-09-01 | Megica Corporation | Circuitry component and method for forming the same |
JP5326281B2 (ja) | 2006-01-06 | 2013-10-30 | ルネサスエレクトロニクス株式会社 | 半導体搭載用配線基板、その製造方法、及び半導体パッケージ |
DE102007034402B4 (de) | 2006-12-14 | 2014-06-18 | Advanpack Solutions Pte. Ltd. | Halbleiterpackung und Herstellungsverfahren dafür |
TWI414048B (zh) | 2008-11-07 | 2013-11-01 | Advanpack Solutions Pte Ltd | 半導體封裝件與其製造方法 |
US20100270668A1 (en) | 2009-04-28 | 2010-10-28 | Wafer-Level Packaging Portfolio Llc | Dual Interconnection in Stacked Memory and Controller Module |
US8796844B2 (en) | 2009-09-02 | 2014-08-05 | Advanpack Solutions Pte Ltd. | Package structure |
US8866301B2 (en) | 2010-05-18 | 2014-10-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package systems having interposers with interconnection structures |
US8865525B2 (en) | 2010-11-22 | 2014-10-21 | Bridge Semiconductor Corporation | Method of making cavity substrate with built-in stiffener and cavity substrate manufactured thereby |
JP5855905B2 (ja) | 2010-12-16 | 2016-02-09 | 日本特殊陶業株式会社 | 多層配線基板及びその製造方法 |
US10109503B2 (en) | 2011-07-22 | 2018-10-23 | Advanpack Solutions Pte Ltd. | Method of manufacturing semiconductor package device |
CN103165566B (zh) | 2011-12-19 | 2016-02-24 | 先进封装技术私人有限公司 | 基板结构、半导体封装件及半导体封装件的制造方法 |
-
2012
- 2012-07-23 US US13/556,022 patent/US10109503B2/en active Active
- 2012-07-23 TW TW101126484A patent/TWI601250B/zh active
- 2012-07-23 CN CN201710475466.0A patent/CN107369668B/zh active Active
- 2012-07-23 CN CN201210256856.6A patent/CN102891131B/zh active Active
-
2018
- 2018-09-19 US US16/136,042 patent/US10763133B2/en active Active
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020037647A1 (en) * | 1998-01-13 | 2002-03-28 | Hwang Jeng H. | Method of etching an anisotropic profile in platinum |
US20070120229A1 (en) * | 2001-02-16 | 2007-05-31 | Dai Nippon Printing Co., Ltd. | Wet etched insulator and electronic circuit component |
US20020168542A1 (en) * | 2001-03-16 | 2002-11-14 | Izbicki Anthony John | Composite metals and method of making |
US20030104770A1 (en) * | 2001-04-30 | 2003-06-05 | Arch Specialty Chemicals, Inc. | Chemical mechanical polishing slurry composition for polishing conductive and non-conductive layers on semiconductor wafers |
US20030232205A1 (en) * | 2002-06-14 | 2003-12-18 | Nobuyoshi Tsukaguchi | Metal/ceramic bonding article and method for producing same |
US20060145363A1 (en) * | 2003-02-21 | 2006-07-06 | Dai Nippon Printing Co., Ltd. | Semiconductor device fabricating apparatus and semiconductor device fabricating method |
CN1764739A (zh) * | 2003-03-25 | 2006-04-26 | 埃托特克德国有限公司 | 用于蚀刻铜表面的溶液和在铜表面上沉积金属的方法 |
US20090209064A1 (en) * | 2006-04-28 | 2009-08-20 | Somchai Nonahasitthichai | Lead frame land grid array |
CN101241861A (zh) * | 2006-06-01 | 2008-08-13 | Amitec多层互连技术有限公司 | 新型多层无芯支撑结构及其制作方法 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104701185A (zh) * | 2013-12-06 | 2015-06-10 | 富葵精密组件(深圳)有限公司 | 封装基板、封装结构以及封装基板的制作方法 |
CN104701185B (zh) * | 2013-12-06 | 2018-01-02 | 碁鼎科技秦皇岛有限公司 | 封装基板、封装结构以及封装基板的制作方法 |
CN107112289A (zh) * | 2014-12-25 | 2017-08-29 | 友立材料株式会社 | 半导体装置用基板、半导体装置用布线构件及它们的制造方法、以及利用半导体装置用基板进行的半导体装置的制造方法 |
CN107112289B (zh) * | 2014-12-25 | 2020-01-07 | 大口电材株式会社 | 半导体装置用基板、半导体装置用布线构件及它们的制造方法、以及利用半导体装置用基板进行的半导体装置的制造方法 |
Also Published As
Publication number | Publication date |
---|---|
CN107369668A (zh) | 2017-11-21 |
TW201306199A (zh) | 2013-02-01 |
US20130020710A1 (en) | 2013-01-24 |
US20190035643A1 (en) | 2019-01-31 |
CN107369668B (zh) | 2020-08-25 |
US10763133B2 (en) | 2020-09-01 |
CN102891131B (zh) | 2017-07-14 |
TWI601250B (zh) | 2017-10-01 |
US10109503B2 (en) | 2018-10-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN102891131A (zh) | 用于制造半导体封装元件的半导体结构及其制造方法 | |
CN102593046B (zh) | 制造半导体器件封装件的方法 | |
CN100556246C (zh) | 配线基板的制造方法 | |
TWI419397B (zh) | 位於半導體或半導體裝置上的薄膜式電池及其製造方法 | |
TWI796595B (zh) | 封裝基板及其製作方法 | |
KR101089959B1 (ko) | 인쇄회로기판 및 그의 제조 방법 | |
WO2022012422A1 (zh) | 封装基板制作方法 | |
CN103517548A (zh) | 布线基板及其制造方法 | |
JP2003338516A (ja) | 半導体装置およびその製造方法 | |
CN102915995B (zh) | 半导体封装件、基板及其制造方法 | |
JP2006519475A (ja) | ケーシングのないモジュール上に直接に形成された自立コンタクト構造体 | |
KR101043328B1 (ko) | 전자소자 내장형 인쇄회로기판 및 그 제조방법 | |
JP2011014644A (ja) | 配線基板およびその製造方法 | |
TWI621224B (zh) | 封裝結構及其製造方法 | |
WO2015107796A1 (ja) | 半導体素子およびその製造方法、ならびに半導体装置 | |
JP2004363364A (ja) | 金属表面処理方法、多層回路基板の製造方法、半導体チップ搭載基板の製造方法、半導体パッケージの製造方法及び半導体パッケージ | |
JPH0487213A (ja) | 異方性導電膜およびその製造方法 | |
JP2008288607A (ja) | 電子部品実装構造の製造方法 | |
KR20140020767A (ko) | 칩형 전자 부품 및 접속 구조체 | |
US20160240464A1 (en) | Hybrid circuit board and method for making the same, and semiconductor package structure | |
US20140101935A1 (en) | Method for manufacturing printed circuit board | |
KR101568528B1 (ko) | 전자소자 봉지재, 그 제조방법 및 봉지방법 | |
US6960822B2 (en) | Solder mask and structure of a substrate | |
TWI753468B (zh) | 具散熱結構之基板結構及其製造方法 | |
US20110000704A1 (en) | Printed Circuit Board and Method of Manufacturing the Same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |