CN100556246C - 配线基板的制造方法 - Google Patents

配线基板的制造方法 Download PDF

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Publication number
CN100556246C
CN100556246C CNB2006100598519A CN200610059851A CN100556246C CN 100556246 C CN100556246 C CN 100556246C CN B2006100598519 A CNB2006100598519 A CN B2006100598519A CN 200610059851 A CN200610059851 A CN 200610059851A CN 100556246 C CN100556246 C CN 100556246C
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Prior art keywords
wiring substrate
insulating barrier
semiconductor chip
stiffener
substrate according
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Expired - Fee Related
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CNB2006100598519A
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CN1835661A (zh
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山野孝治
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Shinko Electric Industries Co Ltd
Shinko Electric Co Ltd
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Shinko Electric Co Ltd
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Abstract

本发明公开一种制造配线基板的方法，包括：在支撑基板上形成第一绝缘层；在第一绝缘层上安装至少一个加强构件；在第一绝缘层上安装至少一个半导体芯片；在加强构件和半导体芯片上形成第二绝缘层；以及在第二绝缘层上形成配线，该配线与半导体芯片连接。

Description

配线基板的制造方法
技术领域
本发明涉及配线基板的制造方法，更具体地，本发明涉及内置有半导体芯片的配线基板的制造方法。
背景技术
目前，采用半导体器件(诸如半导体芯片等)的电子装置的性能已得到提高。这样便存在如下需求：即，在基板上安装半导体芯片的高密度化，使半导体芯片安装于其上的基板的小型化，以及基板的节省空间化。
因此，已提出了其中嵌入半导体芯片的基板，即内置芯片型配线基板。并且提出了在配线基板中内置半导体芯片的多种结构(例如，参见JP-A-2001-217381)。这种内置芯片型配线基板具有与半导体芯片连接的配线结构。同时，在配线基板上形成端子连接部，以使配线基板可与诸如母板等的其他装置连接。
但是，在实现了内置芯片型配线基板的薄型化(变薄)和高密度化的情况下，可能会出现配线基板翘曲的问题。为解决配线基板翘曲的问题，有必要将具有预定厚度的基板(诸如芯板等)与其中嵌入半导体芯片的层进行层叠，以使配线基板具有抗翘曲的结构。因此，在具有这种层压结构的内置芯片型配线基板中，难于实现配线基板的薄型化和配线基板的高密度化。
这样，在抑制配线基板翘曲的同时，难于实现配线基板的薄型化。
发明内容
本发明的目的是提供一种新型实用的配线基板，以及一种制造该配线基板的方法，以解决上述问题。
在本发明中，可以实现内置有半导体芯片的配线基板的薄型化，并且可以抑制这种配线基板的翘曲。
在一些实施例中，本发明的制造配线基板的方法包括：在支撑基板上形成第一绝缘层；在所述第一绝缘层上安装至少一个加强构件；在所述第一绝缘层上安装至少一个半导体芯片；在所述加强构件和所述半导体芯片上形成第二绝缘层；以及在所述第二绝缘层上形成配线，所述配线与所述半导体芯片连接。
根据本发明的制造配线基板的方法，可以实现内置有半导体芯片的配线基板的薄型化，并且可以抑制这种配线基板的翘曲。
本发明的制造配线基板的方法还包括：从第一绝缘层剥离支撑基板。这样，在制造配线基板的过程中可以抑制配线基板的翘曲。而且，可以实现配线基板的薄型化。因此，本方法是合适的。
本发明的制造配线基板的方法还包括：在支撑基板与第一绝缘层之间形成剥离层，所述剥离层有助于从第一绝缘层剥离支撑基板。这有利于支撑基板的剥离。因此，本实施例是有显著效果的。
本发明的制造配线基板的方法还包括：通过加热使第一绝缘层和第二绝缘层硬化，其中，第一绝缘层和第二绝缘层由热硬化树脂材料制成。这样使得第一绝缘层和第二绝缘层能够一体地热硬化，并且可以简化热硬化的步骤。因此，本实施例是有显著效果的。
在本发明的制造配线基板的方法中，加强构件和半导体芯片安装于基本相同的平面上。这样，通过加强构件可以抑制配线基板的翘曲。同时，可以抑制配线基板变得比由现有技术方法制造的配线基板厚。因此，本实施例是有显著效果的。
在本发明的制造配线基板的方法中，加强构件以包围半导体芯片的方式而形成。这样，可以取得良好的抑制配线基板翘曲的效果。因此，本实施例是有显著效果的。
本发明的制造配线基板的方法还包括：在第二绝缘层上形成导通孔；以及在导通孔中形成导通塞。在本发明的制造配线基板的方法中，在导通孔中形成导通塞与在第二绝缘层上形成配线是在同一步骤中进行的。这样，可以提高配线与半导体芯片之间连接的可靠性。
在本发明的制造配线基板的方法中，导通孔是利用激光束形成的，并且在半导体芯片上形成的凸点用作阻挡激光束的阻挡层。这样，可以准确和容易地形成导通孔。因此，本实施例是有显著效果的。
本发明的制造配线基板的方法还包括：对第二绝缘层进行磨削，以使半导体芯片上形成的凸点露出，其中，在第二绝缘层上形成配线，以便与露出的凸点连接。
在根据本发明的制造配线基板的方法中，可以提高配线与半导体芯片之间连接的可靠性。
根据本发明，可以实现内置有半导体芯片的配线基板的薄型化，并且可以抑制这种配线基板的翘曲。
附图说明
图1为示意性地示出根据本发明第一实施例的配线基板的剖视图。
图2A为示出根据第一实施例的加强构件的设置方法的第一视图。
图2B为示出根据第一实施例的加强构件的设置方法的第二视图。
图2C为示出根据第一实施例的加强构件的设置方法的第三视图。
图3A为示出根据第一实施例的配线基板的制造方法的第一视图。
图3B为示出根据第一实施例的配线基板的制造方法的第二视图。
图3C为示出根据第一实施例的配线基板的制造方法的第三视图。
图3D为示出根据第一实施例的配线基板的制造方法的第四视图。
图3E为示出根据第一实施例的配线基板的制造方法的第五视图。
图3F为示出根据第一实施例的配线基板的制造方法的第六视图。
图3G为示出根据第一实施例的配线基板的制造方法的第七视图。
图3H为示出根据第一实施例的配线基板的制造方法的第八视图。
图3I为示出根据第一实施例的配线基板的制造方法的第九视图。
图3J为示出根据第一实施例的配线基板的制造方法的第十视图。
图3K为示出根据第一实施例的配线基板的制造方法的第十一视图。
图3L为示出根据第一实施例的配线基板的制造方法的第十二视图。
图3M为示出根据第一实施例的配线基板的制造方法的第十三视图。
图3N为示出根据第一实施例的配线基板的制造方法的第十四视图。
图4为示意性地示出根据本发明第二实施例的配线基板的剖视图。
图5A为示出根据第二实施例的配线基板的制造方法的第一视图。
图5B为示出根据第二实施例的配线基板的制造方法的第二视图。
图5C为示出根据第二实施例的配线基板的制造方法的第三视图。
图5D为示出根据第二实施例的配线基板的制造方法的第四视图。
图5E为示出根据第二实施例的配线基板的制造方法的第五视图。
图5F为示出根据第二实施例的配线基板的制造方法的第六视图。
图5G为示出根据第二实施例的配线基板的制造方法的第七视图。
图5H为示出根据第二实施例的配线基板的制造方法的第八视图。
图5I为示出根据第二实施例的配线基板的制造方法的第九视图。
图5J为示出根据第二实施例的配线基板的制造方法的第十视图。
图5K为示出根据第二实施例的配线基板的制造方法的第十一视图。
具体实施方式
以下，参考附图对本发明实施例进行说明。
第一实施例
图1为示意性地示出根据本发明第一实施例的配线基板的剖视图。参见图1，在图中所示的配线基板100具有由例如环氧树脂或聚酰亚胺树脂等制成的绝缘层106。配线基板100具有至少一个半导体芯片105嵌入绝缘层106内的结构。
由例如NiP(镍-磷)材料制成的凸点105A形成于半导体芯片105的电极片(图中未示出)上。由例如铜等材料制成的导通塞(viaplug)109以竖立于凸点105A上的方式形成在凸点105A上。而且，由铜等材料制成的图案配线110形成于绝缘层106上，图案配线110与导通塞109成一体以便与导通塞109连接。
另外，端子连接部112包括例如在图案配线110上形成的镍/金层。在图案配线110与绝缘层106上形成阻焊层113，以包围端子连接部112。
另外，根据需要在端子连接部112上形成焊料凸点114。在该图所示的结构中，可以省去焊料凸点114和阻焊层113。
至此，在使这种内置半导体芯片型的配线基板的薄型化的情况下，往往将配线基板与用于支撑配线基板且抑制配线基板翘曲等的结构体(诸如芯板等)进行层叠。因此，难以同时实现配线基板的薄型化和抑制配线基板的翘曲。
这样，根据本实施例的配线基板100构造成：即，通过在半导体芯片105所嵌入的绝缘层106内嵌入加强构件104，可以加强绝缘层106且防止配线基板的翘曲。这样，配线基板100的翘曲可通过加强构件104加以抑制。在采用前述结构的情况下，可以有效地抑制配线基板100的翘曲，而实际上不增加配线基板100的厚度。
这样，与其中具有绝缘层106和用于支撑该绝缘层106的芯板层叠在一起的结构的配线基板相比，本发明具有可使配线基板薄型化的结构。
另外，在所谓面朝上型配线基板诸如配线基板100中，在半导体嵌入绝缘层之后，形成与半导体芯片连接的导通塞以及图案配线。这样，由于以下原因，有时难以保持配线连接的可靠性。
例如，绝缘层106由热硬化树脂材料制成。当将半导体嵌入绝缘层之后，与半导体芯片连接的导通塞以及图案配线通过热硬化过程形成。在这种情况下，当因绝缘层106的热硬化而导致配线基板发生翘曲时，难以连接导通塞与半导体芯片。因此，往往会降低连接的可靠性。
这样，根据本实施例的配线基板可抑制由于热硬化而导致的翘曲，并且可以获得高可靠性的连接。与面朝下型(倒装芯片型)配线基板相比，在这种面朝上型配线基板中，安装(设置)半导体芯片所要求的精度并不高。这样，根据本发明实施例的配线基板的优势在于：半导体芯片易于安装在配线基板上。
例如，在面朝下型配线基板中，进行所形成的图案配线等与半导体芯片的连接部分之间的对准需要高的对准精度。这样，在面朝下型配线基板中进行半导体芯片的安装往往需要耗费成本与时间。
在根据本实施例的配线基板的情况下，可取的是将半导体芯片安装于绝缘层之上，这如后所述。这样，在安装半导体芯片时易于实现对准。而且，在热硬化过程中的绝缘层的翘曲可以由加强构件104加以抑制。这样，根据本实施例的配线基板的优势在于：在安装半导体芯片之后便于实现导通塞与配线之间的对准。
可采用不同材料制造加强构件104。例如，可以采用硬度比绝缘层106大的树脂材料，这些材料例如是：在芯板等中使用的有机芯材料(有时指预浸材料)、诸如铜、镍、铁等的金属材料或上述金属材料的合金材料、或复合材料等。
优选地，加强构件104与半导体芯片105基本形成于同一表平面上。这样，将加强构件104嵌入绝缘层106时不会增加绝缘层106的厚度。
按照半导体芯片的规格和连接规格，根据本实施例的配线基板100可以形成为多种形状和厚度。以下所述为具有具体厚度的配线基板的实例。
例如，绝缘层106底面(下端面)与加强构件104的下端面之间的距离d1为50微米。加强构件104的厚度d2为100微米。加强构件104的上端面与阻焊层113的下端面之间的距离d3小于或等于20微米。阻焊层113的厚度d4为30微米。
在这种情况下，配线基板(不包括焊料凸点114)的厚度等于或小于200微米。
图2A示意性地示出了图1中所示的配线基板的平面图。顺便提及，在图2A中，略去了除半导体芯片105与加强构件104以外的其它部分。如图2A所示，例如在半导体芯片105的周围形成加强构件104，以使加强构件104包围半导体芯片105。这样，可以取得良好的防止翘曲的效果。顺便提及，在配线基板上可安装单个半导体芯片或多个半导体芯片。在这种情况下，加强构件104可以以包围多个半导体芯片的方式而形成。
另外，加强构件并不限于前述实例。例如，加强构件的形状可以下述不同方式进行改变。
图2B与图2C为图2A所示的加强构件的变形的视图。顺便提及，在图2B与图2C中，用与图2A中使用的参考标号相同的参考标号表示图2A示出的上述部分。因此，此处略去对这些部分的说明。加强构件可以变形为与如图2B所示的加强构件104A一样，该加强构件104A分别置于配线基板的两侧(端部)，并且彼此相对。可选地，加强构件也可变形为如图2C所示加强构件104B一样，该加强构件104B分别置于配线基板的角部位附近，并且彼此相对。如上所述，可以根据半导体的尺寸、配线结构或配线基板的规格对加强构件进行多种变形与改变。
以下参考图3A至图3N，按步骤依次对图1所示的根据本发明实施例的配线基板100的制造方法的实例进行说明。
首先，在图3A所示的步骤中，在由例如厚度为725微米的硅晶片制成的支撑基板101上贴附粘性剥离带。从而形成剥离层102。在这种情况下，支撑基板101可以采用诸如有机芯材料等的有机材料。
接着，在图3B所示步骤中，通过层压或涂敷方法在支撑基板101上形成绝缘层103，该绝缘层103例如由环氧树脂或聚酰亚胺树脂等的热硬化树脂材料制成。在这种情况下，在支撑基板101上可以以与支撑基板101相接触的方式形成绝缘层103。优选地，通过在图3A所示的步骤中形成的剥离层102而在支撑基板101上形成绝缘层103，从而易于对支撑基板101进行剥离。
接下来，在图3C所示步骤中，在绝缘层103上设置(安装)由诸如铜等制成的加强构件104。在这种情况下，可采用引线框作为加强构件104。可选地，加强构件104也可以通过镀铜形成。
接着，在图3D所示步骤中，在绝缘层103上例如由加强构件104所包围的区域中设置(安装)半导体芯片105。在这种情况下，优选地，在各半导体芯片105的电极片(图中未示出)上形成由例如NiP(镍-磷)等材料制成的凸点105A。在绝缘层中形成如下所述的导通孔时，凸点105A可以用作阻挡层。同时，凸点105A可以提高在各导通孔中形成的导通塞与半导体芯片之间电连接的可靠性。另外，也可以安装多个半导体芯片。此外，可以使用例如厚度约为95微米的半导体芯片105，厚度约为5微米的凸点105A。
接着，在图3E所示步骤中，例如通过层压方法形成由热硬化环氧树脂或热硬化聚酰亚胺树脂所制成的绝缘层106，该绝缘层106的厚度约为100微米，以便使绝缘层106覆盖半导体芯片105和加强构件104。这样，半导体芯片105和加强构件104被嵌入绝缘层106中。
接下来，在图3F所示步骤中，对绝缘层103与106进行平坦化处理。然后，进行加热处理(固化处理)，以将绝缘层103与106加热至例如160℃。从而，进行热硬化处理。此时，绝缘层103与106相互完全形成为一体。因此，在本图及以下各图中，将绝缘层103和106结合的结构标记为绝缘层106。
在这种情况下，由于加强构件104被嵌入在绝缘层106中，所以，可以有效地抑制特别是因热硬化处理而引起的绝缘层的翘曲。
另外，由于热硬化过程是在绝缘层103与106上同时进行的，所以，绝缘层103的加热过程与绝缘层106的加热过程紧密相关。这样，可以更大程度的抑制由于加热而引起的各绝缘层的翘曲。
接下来，在图3G所示步骤中，在绝缘层上利用例如激光束等形成通达凸点105A的导通孔BH。在这种情况下，在半导体芯片105的电极片上形成的凸点105A可作为阻挡激光束的阻挡层。这样可防止电极片受到损坏。另外，优选地，在导通孔形成之后，根据需要可以利用化学制品进行去污处理，即进行残余物处理和使绝缘层表面粗糙化的处理。
接着，在图3H所示步骤中，利用无电解镀铜方法在包括导通孔BH的内壁表面的绝缘层106和凸点105A上形成种晶层(seed layer)107。
接下来，在图3I所示步骤中，将例如干膜光阻(DFR)层叠在种晶层107上。然后，通过光刻法在干膜光阻上制作布线图案。这样，形成抗蚀图形108。
接着，在图3J所示步骤中，通过例如电解镀铜方法一体地形成导通塞109和图案配线110，以使导通塞109掩埋各导通孔BH，并且图案配线110掩埋抗蚀图形108的各开口部。在电镀完成后，剥离抗蚀图形108。
接下来，在图3K所示步骤中，将例如干膜光阻层叠在种晶层107和图案配线110上。然后，通过光刻法在干膜光阻上制作布线图案。这样，形成抗蚀图形111。
接着，在图3L所示步骤中，利用电镀法在图案配线110从抗蚀图形111的开口部露出的表面上形成端子连接部112，各端子连接部112例如包括镍/金层。然后，在端子连接部112形成之后，剥离抗蚀图形111。进而通过蚀刻方法去除绝缘层106上的种晶层107的多余部分。
接着，在图3M所示步骤中，在图案配线110和绝缘层106上形成阻焊层113，以使端子连接部112露出。
接着，在图3N所示步骤中，利用诸如烘箱等将整个配线基板加热至180℃。然后，将绝缘层106从剥离层102上剥离，并且从绝缘层106上去除支撑基板101。在这种情况下，优选地，剥离层102的粘结强度可以通过加热而降低。在该步骤之后，根据需要在端子连接部112上形成焊球。从而，可以形成图1所示的配线基板100。
在本实施例中，由于采用具有剥离层102的配线基板100，所以通过加热方法从剥离层102上剥离绝缘层106，以及从绝缘层106上去除支撑基板101。但是，配线基板可以由铜等材料制成，而无需剥离层。在这种情况下，在从绝缘层106上去除支撑基板101的步骤中，可以通过蚀刻方法去除由例如铜等材料制成的支撑基板101。此外，当支撑基板101由导电材料制成时，支撑基板可用作电镀时的电极。
根据本实施例的制造方法，在图3C所示步骤中设置加强构件104。然后，在图3F所示步骤中，对其中嵌入有加强构件104的绝缘层106进行固化处理。
这样，在后续步骤中，可以达到抑制绝缘层106或整个配线基板的翘曲程度的效果。特别是，与现有技术的方法相比，可以更有效地抑制因温度的升高/降低使应力变化而引起的翘曲程度，以及可以更有效地抑制因电镀、去污处理、层压处理等使应力变化而引起的翘曲程度。因此，可以获得平面度高且具有高可靠性的配线基板。
此外，在本实施例中，在预定制造过程中，在例如支撑基板101上形成配线基板100。这样，可以抑制制造过程中的翘曲程度。而且，在预定制造过程完成后，去除支撑基板101。这样，可以实现配线基板的薄型化。
第二实施例
根据本发明的配线基板并不限于第一实施例。例如可以对配线结构或加强构件进行各种变形或改变。
例如，图4为示出根据本发明第二实施例的配线基板200。
参见图4，在图中所示的配线基板200中，绝缘层206、加强构件204、半导体芯片205、图案配线210、端子连接部212、阻焊层213和焊料凸点214分别相当于图1所示的配线基板100的绝缘层106、加强构件104、半导体芯片105、图案配线110、端子连接部112、阻焊层113和焊料凸点114。此外，配线基板200的这些结构与配线基板100相似。
在根据本实施例的配线基板200中，由例如铜等材料制成的凸点205A形成于半导体芯片205的电极片(图中未示出)之上。该凸点相当于配线基板100中的导通塞109和凸点105A。即，在本实施例中，凸点205A形成为这样：即，其厚度(高度)例如为15微米，并且其厚度比凸点105A的厚度更厚(更高)。这样，凸点205A也可用作导通塞，以电连接半导体芯片与图案配线。
这样，如下所述，在制造根据本实施例的配线基板的情况下，形成导通孔的步骤以及伴随的去污处理是不必要的。因此，该实施例的优势在于：不仅简化了制造过程，而且降低了制造成本。
接着，参考图5A至图5K，依步骤次序对根据图4所示的本实施例的制造配线基板200的方法的实例进行以下描述。
在本实施例中，首先进行第一实施例中的图3A至图3D所示步骤，以达到图5A所示的状态。顺便提及，在这种情况下，支撑基板201、剥离层202、绝缘层203、加强构件204和半导体芯片205分别相当于第一实施例中的支撑基板101、剥离层102、绝缘层103、加强构件104和半导体芯片105，并且可以由与第一实施例类似的方法形成。
在第二实施例的情况下，在半导体芯片205上形成的、由例如铜等材料制成的凸点205A形成为这样：即，其厚度大于第一实施例中的凸点105A的厚度(凸点205A的高度大于凸点105A的高度)。在这种情况下，凸点205A的高度可以为例如15微米。
接着，在图5B至5C的步骤中形成绝缘层206。此外，可以与第一实施例中的图3E至3F类似的步骤进行平坦化处理和热处理的步骤。
接着，在图5D所示步骤中，通过例如抛光对热硬化后的绝缘层206进行磨削，以使凸点205A露出。在这种情况下，对绝缘层206进行磨削的方法不限于抛光。例如，也可以通过例如CMP(化学机械抛光)等的其它方法进行。
接下来，在图5E所示步骤中，利用无电解镀铜方法在绝缘层206和露出的凸点205A上形成种晶层207。
接着，在图5F所示步骤中，将例如干膜光阻(DFR)层叠在种晶层207上。然后，通过光刻法在该干膜光阻上制作布线图案。这样，形成抗蚀图形208。
接下来，在图5G所示步骤中，通过例如电解镀铜方法形成图案配线210，以掩埋抗蚀图形208的各开口部。在电镀完成之后，剥离抗蚀图形208。
接着，在图5H所示步骤中，将例如干膜光阻层叠在种晶层207和图案配线210上。然后，通过光刻法在干膜光阻上制作布线图案。这样，形成抗蚀图形211。
接下来，在图5I所示步骤中，利用电镀法在图案配线210从抗蚀图形211的开口部露出的表面上形成端子连接部212，各端子连接部212例如包括镍/金层。然后，在端子连接部212形成之后，剥离抗蚀图形211。进而通过蚀刻方法去除绝缘层206上的种晶层207的多余部分。
接着，在图5J所示步骤中，在图案配线210和绝缘层206上形成阻焊层213，以使端子连接部212露出。
接下来，在图5K所示步骤中，与第一实施例类似，利用例如烘箱等将整个配线基板加热至180℃。然后，将绝缘层206从剥离层202上剥离，接着从绝缘层206上去除支撑基板201。在该步骤之后，根据需要在端子连接部212上形成焊球。从而，可以形成图4所示的配线基板200。
根据第二实施例的制造方法，与现有技术的方法相比，可以更有效地抑制配线基板的翘曲程度。因此，与第一实施例类似，可以获得平面度高且具有高可靠性的配线基板。
另外，本发明不仅限于所述实施例。显然，也可以对配线基板的配线结构和配置进行各种变形和改变。而且，也可以对配线与半导体芯片的连接方法进行各种变形和改变。
虽然参照本发明的特定实施例对本发明进行了描述，但是，只要不脱离所附权利要求中所描述的本发明的精神与范围，本领域的技术人员可以作出各种变形和修改。
根据本发明，可以实现内置有半导体芯片的配线基板的薄型化，并且也可以抑制这种配线基板的翘曲。
本申请基于2005年3月15日提交的日本专利申请No.2005-073945，并要求该申请的外国优先权，其内容在此以引用的方式并入本文。

Claims (12)

1.一种制造配线基板的方法，所述方法包括：
在支撑基板上形成第一绝缘层；
在所述第一绝缘层上安装至少一个加强构件；
在所述第一绝缘层上安装至少一个半导体芯片；
在所述加强构件和所述半导体芯片上形成第二绝缘层；以及
在所述第二绝缘层上形成配线，所述配线与所述半导体芯片连接。
2.根据权利要求1所述的制造配线基板的方法，还包括：
从所述第一绝缘层剥离所述支撑基板。
3.根据权利要求2所述的制造配线基板的方法，还包括：
在所述支撑基板与所述第一绝缘层之间形成剥离层，所述剥离层有助于从所述第一绝缘层剥离所述支撑基板。
4.根据权利要求1所述的制造配线基板的方法，还包括：
通过加热使所述第一绝缘层和所述第二绝缘层硬化，其中，
所述第一绝缘层和所述第二绝缘层由热硬化树脂材料制成。
5.根据权利要求1所述的制造配线基板的方法，其中，
所述加强构件和所述半导体芯片安装于相同的平面上。
6.根据权利要求1所述的制造配线基板的方法，其中，
所述加强构件以包围所述半导体芯片的方式而形成。
7.根据权利要求1所述的制造配线基板的方法，其中，
所述至少一个加强构件包括多个加强构件，并且
所述多个加强构件在所述配线基板的两个端部形成。
8.根据权利要求1所述的制造配线基板的方法，其中，
所述至少一个加强构件包括多个加强构件，并且
所述多个加强构件在所述配线基板的角部附近形成。
9.根据权利要求1所述的制造配线基板的方法，还包括：
在所述第二绝缘层上形成导通孔；以及
在所述导通孔中形成导通塞。
10.根据权利要求9所述的制造配线基板的方法，其中，
在所述导通孔中形成所述导通塞与在所述第二绝缘层上形成配线是在同一步骤中进行的。
11.根据权利要求9所述的制造配线基板的方法，其中，
所述导通孔是利用激光束形成的，并且在所述半导体芯片上形成凸点用作阻挡激光束的阻挡层。
12.根据权利要求1所述的制造配线基板的方法，还包括：
对所述第二绝缘层进行磨削，以使所述半导体芯片上形成的凸点露出，
其中，在所述第二绝缘层上形成配线，以便与露出的凸点连接。
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