CN1882224B - 配线基板及其制造方法 - Google Patents

配线基板及其制造方法 Download PDF

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Publication number
CN1882224B
CN1882224B CN2006100833472A CN200610083347A CN1882224B CN 1882224 B CN1882224 B CN 1882224B CN 2006100833472 A CN2006100833472 A CN 2006100833472A CN 200610083347 A CN200610083347 A CN 200610083347A CN 1882224 B CN1882224 B CN 1882224B
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Prior art keywords
wiring substrate
reinforced layer
insulating barrier
semiconductor chip
layer
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Expired - Fee Related
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CN2006100833472A
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CN1882224A (zh
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山野孝治
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Shinko Electric Co Ltd
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Shinko Electric Co Ltd
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    • H05K3/46—Manufacturing multilayer circuits
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    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
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Abstract

本发明公开一种配线基板，该配线基板包括：半导体芯片；内嵌有该半导体芯片的绝缘层；与半导体芯片连接的配线；以及用于加强该绝缘层的加强层，该加强层分别形成于绝缘层的正面侧和绝缘层的背面侧。

Description

配线基板及其制造方法
技术领域
本发明涉及一种配线基板及该配线基板的制造方法，更具体地，本发明涉及一种置入有半导体芯片的配线基板及该配线基板的制造方法。
背景技术
目前，采用半导体芯片等的半导体器件的电子设备的性能已得到不断提高。这样便存在如下要求：即，将半导体芯片安装于基板上时的高密度化、安装半导体芯片时该基板的小型化及节省空间化。
因此，已提出嵌入半导体芯片的基板，即所谓的内置芯片型的配线基板，以及已提出在配线基板中置入半导体芯片的多种结构。上述内置芯片型的配线基板具有与半导体芯片相连接的配线，并且形成连接部分，以便使配线基板与其它设备或母板等相连接(例如，参见JP-A-2004-327624、JP-A-2001-352007和JP-A-2003-142628)。
然而，当实现了内置芯片型配线基板的薄型化和高密度化时，有时会产生配线基板的翘曲问题。为解决配线基板的翘曲问题，举例来说，需要将具有预定厚度的配线基板如芯板层压在半导体芯片所嵌入的层上，以便于抑制翘曲。然而，在这种层压结构中，会出现难于实现配线基板的薄型化和高密度化的问题。
近年来，由于高速运转的半导体芯片产生大量热量，出现了以下问题，即由于这些热量的产生而导致内置有半导体芯片的配线基板可能发生翘曲。
如上所述，在对配线基板的翘曲进行抑制的同时，难以减小配线基板的厚度。尤其当半导体芯片产生大量热量时，更难以减少配线基板的翘曲。
发明内容
鉴于上述情况，做出本发明，并且本发明提供一种新型实用的配线基板及该配线基板的制造方法。
在本发明的实施例中，可实现内置有半导体芯片的配线基板的薄型化，并可抑制该配线基板的翘曲。
在某些实施例中，本发明的配线基板包括：半导体芯片；
内嵌有该半导体芯片的绝缘层；
与该半导体芯片相连接的配线；以及用于该加强绝缘层的加强层，该加强层分别形成于该绝缘层的正面侧和该绝缘层的背面侧。
根据本发明，可实现内置有半导体芯片的配线基板的薄型化，并可抑制该配线基板的翘曲。
此外，当加强层由预浸渍材料制成时，容易形成加强层，并且加强层优选具有较高刚度。
在本发明的配线基板中，加强层中形成于绝缘层的背面侧的一个加强层具有开口部，
并且在该开口部中形成有与配线相连的电极。
因此，在绝缘层的背面侧容易实现与半导体芯片的电连接。
在本发明的配线基板中，加强层中形成于绝缘层的正面侧的另一个加强层之上形成有与配线相连的电极。
因此，在绝缘层的正面侧容易实现与半导体芯片的电连接。
本发明的配线基板还包括：
用于加强绝缘层的附加加强层，该附加加强层嵌入该绝缘层中。
因此，配线基板的刚度可得到进一步提高。
本发明的配线基板还包括：
用于散发半导体芯片的热量的散热部分。
因此，可实现半导体芯片的散热。
在本发明的配线基板中，散热部分包括在半导体芯片上形成的金属层以及与该金属层相连的散热导通塞。
因此，可以有效散发半导体芯片的热量。
在某些实施例中，本发明的配线基板的制造方法包括：
在支撑基板上形成第一加强层，该第一加强层用于加强绝缘层；
在该第一加强层上形成绝缘层和配线，将半导体芯片嵌入该绝缘层中，并将该配线与半导体芯片相连；
在绝缘层上形成第二加强层，该第二加强层用于加强绝缘层；以及
去除该支撑基板。
根据本发明，可实现内置有所述半导体芯片的配线基板的薄型化，并可抑制配线基板的翘曲。
本发明的配线基板的制造方法还包括：
形成第三加强层，以嵌入绝缘层中，该第三加强层用于加强该绝缘层。
因此，可进一步提高配线基板的刚度。
本发明的配线基板的制造方法还包括：
在半导体芯片上形成散热部分，该散热部分用于散发半导体芯片的热量。
因此，可实现半导体芯片的散热。
在本发明的配线基板的制造方法中，第一加强层形成为厚于第二加强层。
因此，可以有效抑制配线基板的翘曲。
根据本发明，可以实现内置有所述半导体芯片的配线基板的薄型化，并可有效抑制配线基板的翘曲。
附图说明
图1为示出根据第一实施例的配线基板的简图。
图2A为按照工艺规程、示出图1所示的配线基板的制造方法的简图(第1)。
图2B为按照工艺规程、示出图1所示的配线基板的制造方法的简图(第2)。
图2C为按照工艺规程、示出图1所示的配线基板的制造方法的简图(第3)。
图2D为按照工艺规程、示出图1所示的配线基板的制造方法的简图(第4)。
图2E为按照工艺规程、示出图1所示的配线基板的制造方法的简图(第5)。
图2F为按照工艺规程、示出图1所示的配线基板的制造方法的简图(第6)。
图2G为按照工艺规程、示出图1所示的配线基板的制造方法的简图(第7)。
图2H为按照工艺规程、示出图1所示的配线基板的制造方法的简图(第8)。
图2I为按照工艺规程、示出图1所示的配线基板的制造方法的简图(第9)。
图2J为按照工艺规程、示出图1所示的配线基板的制造方法的简图(第10)。
图2K为按照工艺规程、示出图1所示的配线基板的制造方法的简图(第11)。
图2L为按照工艺规程、示出图1所示的配线基板的制造方法的简图(第12)。
图2M为按照工艺规程、示出图1所示的配线基板的制造方法的简图(第13)。
图2N为按照工艺规程、示出图1所示的配线基板的制造方法的简图(第14)。
图2O为按照工艺规程、示出图1所示的配线基板的制造方法的简图(第15)。
图2P为按照工艺规程、示出图1所示的配线基板的制造方法的简图(第16)。
图2Q为按照工艺规程、示出图1所示的配线基板的制造方法的简图(第17)。
图2R为按照工艺规程、示出图1所示的配线基板的制造方法的简图(第18)。
图2S为按照工艺规程、示出图1所示的配线基板的制造方法的简图(第19)。
图2T为按照工艺规程、示出图1所示的配线基板的制造方法的简图(第20)。
图2U为按照工艺规程、示出图1所示的配线基板的制造方法的简图(第21)。
图2V为按照工艺规程、示出图1所示的配线基板的制造方法的简图(第22)。
图3为示出根据第二实施例的配线基板的简图。
图4为示出根据第三实施例的配线基板的简图。
图5A为按照工艺规程、示出图4所示的配线基板的制造方法的简图(第1)。
图5B为按照工艺规程、示出图4所示的配线基板的制造方法的简图(第2)。
图5C为按照工艺规程、示出图4所示的配线基板的制造方法的简图(第3)。
图5D为按照工艺规程、示出图4所示的配线基板的制造方法的简图(第4)。
图5E为按照工艺规程、示出图4所示的配线基板的制造方法的简图(第5)。
图5F为按照工艺规程、示出图4所示的配线基板的制造方法的简图(第6)。
图5G为按照工艺规程、示出图4所示的配线基板的制造方法的简图(第7)。
图5H为按照工艺规程、示出图4所示的配线基板的制造方法的简图(第8)。
图5I为按照工艺规程、示出图4所示的配线基板的制造方法的简图(第9)。
图5J为按照工艺规程、示出图4所示的配线基板的制造方法的简图(第10)。
具体实施方式
根据本发明实施例的配线基板是一种内置有半导体芯片的配线基板。配线基板包括：半导体芯片；内嵌有该半导体芯片的绝缘层；与该半导体芯片相连的配线；以及用于加强该绝缘层的加强层，该加强层分别形成于绝缘层的正面侧和绝缘层的背面侧。
因此，可以构成这样的配线基板，即：其翘曲较小，平面度较高，并能够满足微细化的配线。此外，加强层可通过对普通增层(build-up layer)(绝缘层)的层进行部分替换得以实现，以便使得普通增层法可适用于该加强层。因此，配线基板易于以较高可靠性形成，并可以实现薄型化。
以下，通过参照附图，对本发明的实施例进行说明。
[第一实施例]
图1为示意性示出根据本发明第一实施例的配线基板100的剖视图。参照图1，根据本发明的配线基板具有内嵌有半导体芯片110的绝缘层106，该绝缘层例如由环氧树脂等称为增层树脂的材料制成。分别形成用于加强绝缘层106的加强层103和114，以便与绝缘层106的两个表面接触。
半导体芯片110与配线部分(以下进行描述)连接，并通过该配线部分与在加强层103一侧(附图中的下侧，以下同)形成的电极102或在加强层114一侧(附图中的上侧，以下同)形成的电极118连接。例如，电极102或电极118与母板、其它设备或连接设备连接。
在半导体芯片110的电极片(图中未示出)中，形成由例如金制成的柱形凸点(stud bump)111。柱形凸点111通过例如焊接连接部分109与嵌入绝缘层106中的配线部分108连接。此外，在半导体芯片110的下侧，可以形成底部填充层110A。
在根据本发明的配线基板100中，除了配线部分108以外，以层压的方式用例如铜形成配线部分105、配线部分113和配线部分116。
配线部分105包括导通塞(via plug)105a和图案配线105b。在加强层103中形成的开口部中，形成导通塞105a。在加强层103上，形成与导通塞105a连接的图案配线105b。
在配线部分105上，形成与配线部分105连接的配线部分108，并且配线部分108嵌入绝缘层106中。
所述配线部分108包括在图案配线105b上形成的导通塞108a和与导通塞108a连接的图案配线108b。半导体芯片110通过如上所述的焊接连接部分109和柱形凸点111与图案配线108b连接。
此外，在配线部分108上，与配线部分108连接的配线部分113嵌入并形成于绝缘部分106中。配线部分113包括在图案配线108b上形成的导通塞113a和与导通塞113a连接的图案配线113b。
此外，在配线部分113上，形成与配线部分113连接的配线部分116。配线部分116包括在图案配线113b上形成的导通塞116a，以及与导通塞116a连接的图案配线116b。
在从绝缘层106侧到加强层114的开口部中形成导通塞116a，并且在加强层114上形成图案配线116b。
在加强层103的开口部中，形成与导通塞105a连接的电极102。在图案配线116b上分别形成电极118。这样，待连接的对象可以分别在下侧和上侧与半导体芯片容易地电连接。
此外，分别形成阻焊层119和117，以便于用其覆盖加强层103和加强层114。并在这些阻焊层上形成用于使电极暴露的开口部。
此外，举例来说，可以根据需要在电极102中形成焊球120。也可以在电极118中形成焊球。
在本实施例的配线基板100中，内嵌有半导体芯片或配线部分的绝缘层106以夹在加强层103和加强层114之间的方式形成。因此，可以形成这样的配线基板，即：其中内置有半导体芯片的配线基板的翘曲得到减少、平面度较高，并能够满足微细化的配线。
举例来说，优选采用预浸渍材料形成加强层103和114。预浸渍材料称为有机芯材料，或有时简称为芯材料，当形成多层配线基板(增层基板)时，预浸渍材料可以用作芯板材料。
举例来说，预浸渍材料具有这样的结构，即用玻璃纤维浸透环氧型树脂材料并进行固化，并且该预浸渍材料表现出这样的特性，即其刚度高于普通增层树脂(build-up resin)材料的刚度。举例来说，增层树脂的弹性模量(杨氏模量)大约为5Gpa至8Gpa。与之相比，预浸渍材料的弹性模量为20Gpa甚至更高，从而预浸渍材料具有较高的刚度。从而，可以减少配线基板的翘曲。
用以形成加强层103和114的材料并不局限于预浸渍材料，例如，也可以采用具有较高刚度的成型树脂。此外，也可以使用例如金属这样的材料作为形成加强层103和114的材料。当使用例如金属这样的导电材料时，优选增加用于使配线部分与加强层绝缘的结构。
此外，可以按照普通增层法形成根据本实施例的配线基板，并且可以减小该配线基板的厚度。
现在，通过使用图2A至2V，按照工艺规程，对配线基板的制造方法进行说明。
首先，在图2A所示工艺中，制备这样的支撑基板101，即其由例如铜等导电材料制成，并具有200μm的厚度。
然后，在图2B所示工艺中，通过光刻法在支撑基板101上形成抗蚀图案(图中未示出)，接着将该抗蚀图案作为掩模，通过电解电镀形成具有这样的结构的电极102：即，例如，由金层102a、镍层102b和铜层102c层压形成的结构。在电解电镀中，由于支撑基板101作为电流通路，因而支撑基板101优选由导电材料制成，更优选由例如铜等低电阻材料制成。
然后，在图2C所示工艺中，在支撑基板101上形成由预浸渍材料制成的加强层103，以用其覆盖电极102。在形成加强层103之后，通过例如激光器形成导通孔103A，以便于暴露电极102。
在图2D所示工艺中，根据需要进行去污工艺，以除去导通孔的残留材料，并对加强层103进行表面处理，然后，通过无电镀工艺(化学镀工艺)在加强层103的表面和电极102的表面上形成铜的种晶层(seed layer)104。
然后，在图2E所示工艺中，通过光刻法形成抗蚀图案(图中未示出)。然后，采用抗蚀图案作为掩模，通过铜的电解电镀在导通孔103A中形成导通塞105a，并在加强层103上形成与导通塞105a连接的图案配线105b，以形成配线部分105。
在形成配线部分105之后，分离抗蚀图案，以通过蚀刻除去暴露的多余种晶层。
然后，在图2F所示工艺中，在加强层103上形成由例如热固环氧树脂制成的绝缘层106(增层)，用以覆盖其配线部分105处。此外，在绝缘层中，通过激光器形成导通孔106A，以便暴露图案配线105b的一部分。
然后，在图2G所示工艺中，根据需要，以与图2D所示工艺相同的方式，进行去污工艺，以除去导通孔的残留材料，并对绝缘层106进行表面处理，然后，通过无电镀工艺在绝缘层106的表面和图案配线105b暴露的表面上形成铜的种晶层107。
然后，在图2H所示工艺中，以与图2E中所示工艺相同的方式，通过光刻法形成抗蚀图案(图中未示出)。然后，采用抗蚀图案作为掩模，通过铜的电解电镀在导通孔106A中形成导通塞108a，并在绝缘层106上形成与导通塞108a连接的图案配线108b，以形成配线部分108。
在形成配线部分108之后，从种晶层剥离抗蚀图案，以通过蚀刻除去暴露的多余种晶层。
然后，在图2I所示工艺中，在绝缘层106上形成由例如热固环氧树脂制成的绝缘层(增层)106a，以便于用其覆盖配线部分108。由于绝缘层106a基本上与绝缘层106形成为浑然一体，因此绝缘层106是指在图2I的工艺之后，包括绝缘层106a的层。
随后，在图2J所示工艺中，通过例如激光器在绝缘层106上形成开口部106B，以便于暴露图案配线108b的一部分。
然后，在图2K所示工艺中，根据需要进行去污工艺，以除去开口部分的残留材料，并对绝缘层106进行表面处理，然后，通过例如电解电镀工艺在开口部分106B中形成焊接连接部分109。
然后，在图2L所示工艺中，在配线部分108上安装具有柱形凸点111(由例如金制成)的半导体芯片110，以使柱形凸点111与焊接连接部分109相对应。在这种情况下，若需要，优选进行焊接连接部分109的回流过程，以成功实现焊接连接部分109与柱形凸点111之间的电连接。此外，根据需要，优选在半导体芯片110和绝缘层106之间形成底部填充层110A。
然后，在图2M所示工艺中，在绝缘层106上形成由例如热固环氧树脂材料制成的绝缘层(增层)106b，以便用其覆盖半导体芯片110。由于绝缘层106b基本上与绝缘层106形成为浑然一体，因此绝缘层106是指在图2M的工艺之后，包括绝缘层106b的层。
其后，在图2N所示工艺中，通过例如激光器在绝缘层106上形成导通孔106C，以便于暴露图案配线108b的一部分。
然后，根据需要进行去污工艺，以除去导通孔的残留材料，并对绝缘层106进行表面处理，然后，通过无电镀工艺在绝缘层106的表面和图案配线108b的表面上形成铜的种晶层112。
在图2O所示工艺中，以与图2H中所示工艺相同的方式，通过光刻法形成抗蚀图案(图中未示出)。然后，采用抗蚀图案作为掩模，通过铜的电解电镀在导通孔106C中形成导通塞113a，并在绝缘层106上形成与导通塞113a连接的图案配线113b，以形成配线部分113。
配线部分113形成后，从种晶层剥离抗蚀图案，以通过蚀刻除去暴露的多余种晶层。
然后，在图2P所示工艺中，在绝缘层106上形成由例如热固环氧树脂制成的绝缘层(增层)106c，以用其覆盖配线部分113。由于绝缘层106c基本上与绝缘层106形成为浑然一体，因此绝缘层106是指在图2P工艺之后，包括绝缘层106c的层。
此外，在绝缘层106c上形成由例如预浸渍材料制成的加强层114。在形成加强层114之后，通过如激光器在加强层114和绝缘层106中形成导通孔114A，以暴露图案配线113b。
然后，在图2Q所示工艺中，根据需要进行去污工艺，以除去导通孔的残留材料，并对绝缘层106和加强层114进行表面处理，然后，通过无电镀工艺在导通孔的内壁表面、加强层114的表面和图案配线113b的表面上形成铜的种晶层115。
然后，在图2R所示工艺中，以与图2O中所示工艺相同的方式，通过光刻法形成抗蚀图案(图中未示出)。然后，采用抗蚀图案作为掩模，通过铜的电解电镀在导通孔114A中形成导通塞116a，并在加强层114上形成与导通塞116a连接的图案配线116b，以形成配线部分116。
在形成配线部分116之后，从种晶层剥离抗蚀图案，以通过蚀刻除去暴露的多余种晶层。
然后，在图2S所示工艺中，形成具有开口部117A的阻焊层117，以便用其覆盖加强层114，其中，图案配线116b的一部分在开口部分得以暴露。
然后，在图2T所示工艺中，在暴露于开口部117A的图案配线116b上形成由例如镍/金制成的电极118。
然后，在图2U所示工艺中，通过例如湿法蚀刻工艺去除支撑基板101。然后，在图2V所示工艺中，形成具有开口部119A的阻焊层119，以便用其覆盖加强层103，其中，电极102暴露于开口部119A处。
此后，在电极102中形成焊球120，这样便可以形成图1所示的配线基板100。
通过采用无芯结构(除去支撑基板的结构)，可将普通增层法适用于上述制造方法中，因此可以实现薄型化、紧凑和轻量的配线基板，并且可通过加强层103和114减少翘曲。因此，可以形成具有微细化的配线部分和薄型化的配线基板。
此外，加强层103优选形成为其厚度大于加强层114的厚度，这是因为这样的缘故：即，在配线基板的制造过程中，越往下层，产生热应力的次数增加。例如，绝缘层106通过层压热固树脂材料而形成。在上述实施例中，尽管省略了其描述，每次对热固树脂材料进行层压时，优选提供热固化处理。因此，由于在配线基板的下侧(下层侧)的加强层产生热应力的次数增加，所以将下侧的加强层优选形成为厚度大于上侧(上层侧)的加强层，以减少翘曲。
作为配线基板100厚度的一个实例，举例来说，当加强层103的厚度设为80μm、将加强层114的厚度设为40μm时，可形成具有440μm总厚度的配线基板。
应该理解，层压配线的数量并不局限于本实施例中所描述的数量，可进行多种改变和设定。
此外，在本实施例中，通过蚀刻去除由例如铜制成的支撑基板101。然而，可供选择地，例如可以通过制备在其上贴有粘性剥离带的支撑基板101，使支撑基板101在其与加强层102相接触的一侧具有剥离层。优选地，可通过加热降低剥离层的粘合强度。在这种情况下，在如图2U所示，将支撑基板101从加强层103上除去的步骤中，通过用例如烘箱加热整个配线基板，可以将加强层103从剥离层剥离。
[第二实施例]
在第一实施例中所述的配线基板可形成为下述的结构，以便更大程度上减少翘曲。
图3为示意性示出根据第二实施例的配线基板100A的剖视图。在图中，前面描述的部分用同样的参考标号表示，并省略其说明。
参照图3，在根据本实施例的配线基板100A中，在绝缘层106中嵌入用于加强绝缘层106的加强层121，该加强层形成于加强层103和加强层114之间。
另外，在加强层121中形成可穿过导通塞113a的开口部121A。这样，除了第一实施例所示结构外，通过在绝缘层106中进一步加入加强层，从而使配线基板的刚度得到更大程度提高，并更大程度增强抑制配线基板的翘曲的效果。
此外，当制造根据本实施例的配线基板100A时，在第一实施例的所述制造方法中，可在图2L所示工艺之后加入形成加强层121的工艺。随后的工艺与第一实施例的工艺相同。这样，可以制造配线基板100A。
此外，加强层121由例如与加强层103和114类似的预浸渍材料制成，但也可以使用成型树脂或金属材料形成。
[第三实施例]
近年来，出现了这样的问题，即：高速运转的半导体芯片产生大量热量，因此，内置有半导体芯片的配线基板有时会发生翘曲。
这样，当将用于散发半导体芯片热量的散热部分添加到第一实施例或第二实施例所示的配线基板时，因所产生热量造成半导体芯片损坏或性能不佳的情况将显著减少，由于所产生热量造成的配线基板的翘曲也得到减少。
图4为示意性示出根据本发明第三实施例的配线基板100B的剖视图。在图中，前面描述的部分由同样的参考标号表示，并省略其说明。
参照图4，在根据本实施例的配线基板100B中，形成散热部分200，以散发(冷却)半导体芯片110的热量。散热部分200包括金属层201、散热导通塞202和电极203，该金属层形成于半导体110上，该散热导通塞202与金属层201连接且以直立于金属层201上的方式形成，该电极203形成于散热导通塞202上并由例如镍/金制成。
金属层201具有铬/铜或钛/铜结构，并形成于半导体芯片110的器件表面的背侧。此外，散热导通塞202由例如铜制成，与金属层201连接并以直立于金属层201上的方式形成，从而使金属层201的侧面与绝缘层106、加强层114和阻焊层117接触。
如上所述，由于金属层201和散热导通塞202的形成，所以可以有效地散发半导体芯片110所产生的热量。因此，可以有效抑制因发热造成的半导体芯片的损坏或性能不佳、或配线基板的翘曲。
此外，在散热导通塞202上形成电极203，该导通塞在阻焊层117中形成的开口部得以暴露。举例来说，在电极203上，根据需要形成焊球。这样，可将电极与有待连接到配线基板的对象(诸如母板等)连接。例如，当散热导通塞202通过电极203与待连接对象连接时，散热效果更强，这样可以将半导体芯片中产生的热量有效地排出到待连接对象。
现在，将参照图5A至5J，按照工艺规程，对配线基板100B的制造方法进行说明。在图中，前面描述的部分由同样的参考标号表示，并省略其说明。未说明部分则与第一实施例中相同。
图5A所示工艺与第一实施例中所述制造方法的图2M所示工艺相对应。也就是说，通过进行第一实施例中图2A至图2M所示工艺，可达到图5A所示的状态。然而，在本实施例中，在将半导体芯片110装于配线部分上之前，通过溅射法在半导体芯片110的器件形成表面的背侧形成金属层201，该金属层201具有由例如铬/铜或钛/铜制成的结构。
然后，在图5B所示工艺中(该工艺与第一实施例中图2N所示工艺相对应)，在绝缘层106上形成导通孔106C，通过例如激光器形成延伸至金属层201的导通孔106D。
在这种情况下，金属层的功能是充当激光的阻挡层，以防止半导体芯片上形成的器件被激光损坏。即，金属层201有助于散热，并在配线基板的制造过程中充当半导体芯片器件的保护层。此外，金属层有效地提高了散热导通塞与半导体芯片之间的粘合力，该导通塞在随后工艺中形成于导通孔中。
然后，根据需要进行去污工艺，以除去导通孔的残留材料，并对绝缘层106进行表面处理，然后，通过无电镀工艺在包括导通孔内壁表面的绝缘层106的表面、图案配线108b的表面和金属层201的表面上形成铜的种晶层112。
然后，在图5C所示工艺中(该工艺与第一实施例中图20所示工艺相对应)，形成配线部分113，并在导通孔106D中形成散热导通塞202A。
在图5D所示工艺中(该工艺与第一实施例中图2P所示工艺相对应)，以与第一实施例相同的方式形成绝缘层106c，以在绝缘层106c上形成由例如预浸渍材料制成的加强层114。此外，形成导通孔114A，通过例如激光器在预浸渍材料114上形成导通孔114B。
然后，在图5E所示工艺中(该工艺与第一实施例中图2Q所示工艺相对应)，若需要则进行去污工艺，以除去导通孔的残留材料，并对绝缘层106和加强层114进行表面处理。然后，在导通孔114A和114B的内壁表面、加强层114的表面、图案配线113b的表面和散热导通塞202A的表面上形成铜的种晶层115。
然后，在图5F所示工艺中(该工艺与第一实施例中图2R所示工艺相对应)，通过铜的电解电镀工艺形成配线部分116，并形成散热导通塞202B，以层压在散热导通塞202A上。这样便形成包括散热导通塞202A和202B的散热导通塞202。
在形成配线部分116和散热导通塞202之后，剥离抗蚀图案，以通过蚀刻工艺除去暴露的多余种晶层。
在图5G至5J所示的随后工艺中，进行与第一实施例中图2S至2V所示工艺相对应的工艺，以便形成配线基板100B。
在本实施例中，除了在图5G所示工艺中，在阻焊层117上形成从其暴露散热导通塞202的开口部117B，并且在图5H所示工艺中，当形成电极118时，在散热导通塞202上形成电极203之外，可以以与第一实施例中相同的方式形成所述配线基板。
与第一实施例的制造方法相比，在根据本实施例的制造方法中，可以在不增加工艺数目的情况下，形成半导体芯片的散热部分。
此外，应该理解，散热部分的结构不仅限于本实施例，并且，例如，该散热部分的材料(金属材料的种类)或其结构(散热导通塞的数量、位置等)可进行多种变型与更改。
以上描述了优选实施例，然而，本发明并不局限于上述具体实施例，并且在与权利要求书的要旨一致的的范围内，可以进行多种变型和更改。
根据本发明，可实现内置有半导体芯片的配线基板的薄型化，并抑制所述配线基板的翘曲。
对所属领域的技术人员而言，显然，在未背离本发明的要旨或保护范围的情况下，可对本发明的所述优选实施例做出多种变型和更改。这样，本发明旨在包含与所附权利要求书及其等同内容的保护范围一致的本发明的所有变型和更改。
本申请以2005年6月2日提交的日本专利申请No.2005-162547为基础要求外国优先权，其全部内容在此以引用的方式并入本文。

Claims (12)

1. 一种配线基板，包括：
半导体芯片；
绝缘层，在其内嵌有半导体芯片；
配线，其与所述半导体芯片连接；以及
加强层，其用于加强所述绝缘层，并且所述加强层分别形成于所述绝缘层的正面侧和所述绝缘层的背面侧。
2. 根据权利要求1所述的配线基板，其中，
所述加强层由预浸渍材料制成。
3. 根据权利要求1所述的配线基板，其中，
在所述加强层中形成于所述绝缘层的背面侧的一个加强层具有开口部，并且
在所述开口部中形成有与所述配线连接的电极。
4. 根据权利要求1所述的配线基板，其中，
在所述加强层中形成于所述绝缘层的正面侧的另一个加强层之上，形成有与所述配线连接的电极。
5. 根据权利要求1所述的配线基板，还包括：
附加加强层，其用于加强所述绝缘层，所述附加加强层嵌入在所述绝缘层中。
6. 根据权利要求1所述的配线基板，还包括：
散热部分，其用于散发所述半导体芯片的热量。
7. 根据权利要求6所述的配线基板，其中，
所述散热部分包括在所述半导体芯片上形成的金属层以及与所述金属层连接的散热导通塞。
8. 根据权利要求1所述的配线基板，其中，
在所述加强层中形成于所述绝缘层的背面侧的一个加强层形成为厚于所述加强层中形成于所述绝缘层的正面侧的另一个加强层。
9. 一种配线基板的制造方法，所述方法包括：
在支撑基板上形成第一加强层，所述第一加强层用于加强绝缘层；
在所述第一加强层上形成所述绝缘层和配线，半导体芯片嵌入在所述绝缘层中，所述配线与所述半导体芯片连接；
在所述绝缘层上形成第二加强层，所述第二加强层用于加强所述绝缘层；以及
去除所述支撑基板。
10. 根据权利要求9所述的配线基板的制造方法，还包括：
形成第三加强层，以嵌入所述绝缘层中，所述第三加强层用于加强所述绝缘层。
11. 根据权利要求9所述的配线基板的制造方法，还包括：
在所述半导体芯片上形成散热部分，所述散热部分用于散发所述半导体芯片的热量。
12. 根据权利要求9所述的配线基板的制造方法，其中，
所述第一加强层形成为厚于所述第二加强层。
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