CN102132639A - 电子部件内置线路板及其制造方法 - Google Patents

电子部件内置线路板及其制造方法 Download PDF

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Publication number
CN102132639A
CN102132639A CN2009801326496A CN200980132649A CN102132639A CN 102132639 A CN102132639 A CN 102132639A CN 2009801326496 A CN2009801326496 A CN 2009801326496A CN 200980132649 A CN200980132649 A CN 200980132649A CN 102132639 A CN102132639 A CN 102132639A
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mentioned
built
circuit board
electronic parts
pattern layers
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CN2009801326496A
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古谷俊树
古泽刚士
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Ibiden Co Ltd
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Ibiden Co Ltd
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    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
    • H05K1/187—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding the patterned circuits being prefabricated circuits, which are not yet attached to a permanent insulating substrate, e.g. on a temporary carrier
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Abstract

本发明提供一种电子部件内置线路板及其制造方法。该电子部件内置线路板(1)包括导体图案层(40)、设置于导体图案层(40)且与用倒装法安装的电子部件(2)电接合的连接端子(80)、及形成在导体图案层(40)上的阻焊剂层(112)。而且，该阻焊剂层(112)形成在导体图案层(40)上的连接端子(80)的周围，且在导体图案层(40)上的其他区域中的至少一部分区域上不形成导体图案层(40)。因此，能够保护连接端子(80)，从而能够确保导体之间的绝缘性。并且，并未在导体图案(40)的整个表面上形成阻焊剂层(112)，因此，能够降低基板的翘曲。

Description

电子部件内置线路板及其制造方法
技术领域
本发明涉及一种在内部收容有半导体元件等电子部件的电子部件内置线路板。
背景技术
近年来，电子设备的高性能化、小型化得到发展，与此同时，对安装在电子设备内部的线路板的高功能化、高集成化的要求越来越高。
对于上述状况，提出了各种将IC芯片等电子部件收容(内置)在线路板内的技术(例如专利文献1中公开的多层线路板等)。
像专利文献1中公开的那样，通过将电子部件内置在线路板中，能够使多层线路板高功能化和高密度化。即，通过在内部收纳电子部件，能够在表层的安装区域中安装其他的电子部件等，从而能够实现高功能化。
另外，通过内置电子部件，也能够使多层线路板自身减小，与以往的多层线路板相比，能够实现线路高密度化。并且，由于能够减小布线长度，因此，也能够期待提高性能。
专利文献1：日本特开2004-7006号公报
但是，在线路板的制造工艺中，出于防止焊锡附着、维持导体之间的绝缘性、保护导体等目的，公知有在形成的导体图案上涂覆阻焊剂的方法。特别是出于细间距化的目的，期望利用阻焊剂来保护包括用于与内置的电子部件电连接的连接端子的导体图案层。
另一方面，构成阻焊剂的材料(绝缘性树脂)的热膨胀率高于构成导体图案的金属的热膨胀率。因而，在形成有上述连接端子的导体图案层中，在整个表面上都形成有阻焊剂时，有可能由两者的热膨胀率不同导致线路板发生翘曲。
发明内容
本发明即是鉴于上述以往问题而做成的，其目的在于提供一种能够谋求细间距化并能够防止发生翘曲的、连接可靠性等品质优良的电子部件内置线路板及其制造方法。
本发明的电子部件内置线路板利用倒装法安装而内置有电子部件，其特征在于，该电子部件内置线路板包括：导体图案层、设置于该导体图案层且与上述电子部件电接合的连接端子、形成在上述导体图案层上的阻焊剂层，上述阻焊剂层形成在上述导体图案层上的上述连接端子的周围，在上述导体图案层上的其他区域的至少一部分区域上不形成上述阻焊剂层。
优选为，上述连接端子包括由与上述导体图案层不同的金属形成在上述导体图案层上的接合层。
上述接合层可以由焊锡构成。
优选为，上述阻焊剂层覆盖上述导体图案层的上述连接端子形成区域的至少一部分。
优选为，上述电子部件被绝缘材料所覆盖，在该绝缘材料上形成有通孔导体。
在这种情况下，上述导体图案层可以以不自上述绝缘材料的表面突出的状态形成。
上述导体图案层的表面可以粗化。
另外，本发明的电子部件内置线路板的制造方法的特征在于，包括以下工序：在支承体上配置金属箔而成的层叠基材的上述金属箔上形成导体图案层；在上述导体图案层上的一部分区域形成设有规定的开口部的阻焊剂层；通过在与上述阻焊剂层的开口部相对应的上述导体图案层上设置接合层，形成连接端子；将上述电子部件以该电子部件的电路形成面和上述连接端子的形成面相对的方式配置在上述层叠基材上，而使上述电子部件和上述连接端子电连接；用绝缘材料包覆上述安装后的电子部件；除去上述支承体；除去暴露的上述金属箔。
上述接合层优选由与上述导体图案层不同的金属构成。
在这种情况下，可以由焊锡形成上述接合层。
上述电子部件内置线路板的制造方法可以还包括在用上述绝缘材料包覆上述电子部件之后，在上述绝缘材料中设置贯穿孔而形成通孔导体的工序。
可以利用电解电镀形成上述导体图案层。
上述电子部件内置线路板的制造方法可以还包括在形成上述导体图案层之后，形成上述阻焊剂层之前，将上述导体图案层的表面粗化的工序。
上述电子部件内置线路板的制造方法可以还包括在安装上述电子部件之后，在上述连接端子的周围填充绝缘性树脂的工序。
另外，在上述两发明中，优选在上述电子部件上形成用于与上述连接端子接合的凸块。在这种情况下，上述凸块既可以以格子状配置在电路形成面上(所谓的区域阵列(area array)型)，也可以配置在电路形成面的端部(所谓的围绕(peripheral)型)。
采用本发明，能够提供一种能谋求细间距化并能够防止发生翘曲的、连接可靠性等品质优良的电子部件内置线路板。
附图说明
图1A是表示支承基材的构造的剖视图。
图1B是表示在支承基材上形成有第1基底层和第2基底层的情形的剖视图。
图1C是表示在图1B中的基板上层压有感光性抗蚀剂层的情形的剖视图。
图1D是表示在图1B中的基板上形成有抗镀层的情形的剖视图。
图1E是表示在图1D中的基板上形成有镀铜层的情形的剖视图。
图1F是表示自图1E中的基板剥离抗镀层之后的情形的剖视图。
图1G是表示在图1F中的基板上形成有阻焊剂层的情形的剖视图。
图1H是表示在图1G中的基板上形成有接合层的情形的剖视图。
图2A是表示电子部件的安装工序的剖视图。
图2B是表示填充填底材料之后的情形的剖视图。
图3A是表示层叠工序的剖视图(之一)。
图3B是表示层叠工序的剖视图(之二)。
图3C是表示层叠工序的剖视图(之三)。
图4A是表示自图3C中的基板剥离载体之后的情形的剖视图。
图4B是表示在图4A中的基板上形成有贯穿孔的情形的剖视图。
图4C是表示对图4B中的基板实施无电解镀铜之后的情形的剖视图。
图4D是表示在图4C中的基板上形成有抗镀层的情形的剖视图。
图4E是表示在图4D中的基板上形成有镀铜膜和通孔导体的情形的剖视图。
图4F是表示本发明一个实施方式的电子部件内置线路板的构造的剖视图。
图5A是表示由图4F中的电子部件内置线路板制造多层线路板的工序的剖视图(之一)。
图5B是表示由图4F中的电子部件内置线路板制造多层线路板的工序的剖视图(之二)。
图5C是表示由图4F中的电子部件内置线路板制造多层线路板的工序的剖视图(之三)。
图5D是表示由图4F中的电子部件内置线路板制造多层线路板的工序的剖视图(之四)。
图5E是表示由图4F中的电子部件内置线路板制造多层线路板的工序的剖视图(之五)。
图5F是表示使用了图4F中的电子部件内置线路板的多层线路板的构造的工序的剖视图。
图6是用于说明本实施方式的阻焊剂层形成形态的俯视图。
图7是用于说明另一实施方式的阻焊剂层形成形态的俯视图(之一)。
图8是用于说明另一实施方式的阻焊剂层形成形态的俯视图(之二)。
图9是用于说明另一实施方式的阻焊剂层形成形态的俯视图(之三)。
附图标记说明
1、电子部件内置线路板；2、电子部件；3、绝缘材料；4、填底材料；5、填充树脂；20、凸块；40、50、60、70、导体图案；80、连接端子；81、焊盘；82、接合层；90、通孔导体；91、第1内层的通孔连接盘；92、第2内层的通孔连接盘；93、第1外层的通孔连接盘；94、第2外层的通孔连接盘；112、阻焊剂层。
具体实施方式
下面，参照附图说明本发明的实施方式的电子部件内置线路板及其制造方法。
图4F是本实施方式的电子部件内置线路板1的概略剖视图。该电子部件内置线路板1例如可用作多层印刷线路板的芯基板等。
电子部件内置线路板1由电子部件2、绝缘材料3、填底材料4、填充树脂5、内层的导体图案40、50、阻焊剂层112、外层的导体图案60、70、连接端子80、通孔导体90构成。
电子部件2是倒装芯片(flip chip)，该电子部件2具有排列成区域阵列型的多个凸块20。凸块20例如是厚度约30μm的柱形金凸块。
绝缘材料3是在玻璃纤维、芳香族聚酰胺纤维等加强材料中浸渗环氧树脂、聚酯树脂、聚酰亚胺树脂、双马来酰亚胺-三嗪树脂(BT树脂)、酚醛树脂等树脂而成的板材，在本实施方式中其由预浸料构成。
填底材料4例如是含有二氧化硅、氧化铝等无机填料的绝缘性树脂，起到确保电子部件2的固定强度、并吸收因电子部件2和绝缘材料(例如绝缘材料3、填充树脂5)的热膨胀率差别而产生的变形的作用。填底材料4优选由热固性树脂和40～90wt％的无机填料构成。另外，填料的规格(平均粒径)优选为0.1～3.0μm。
填充树脂5优选由热固性树脂和无机填料构成。无机填料例如能够采用Al2O3、MgO、BN、AlN或SiO2等。热固性树脂例如优选为耐热性较高的环氧树脂、酚醛树脂或者氰酸酯树脂，其中，特别优选耐热性优良的环氧树脂。
阻焊剂层112例如能够将采用了丙烯酸-环氧系树脂的感光性树脂、将环氧树脂作为主体的热固性树脂、紫外线固化型树脂等作为材料，利用丝网印刷、喷涂(spray coating)、辊涂(roll coating)等来形成。或者也可以通过对采用了丙烯酸-环氧类树脂的感光性干膜进行真空层压等来形成。
由铜等构成的导体图案40形成在电子部件内置线路板1的第1面侧(与电子部件2的电路形成面相对的一侧)的内部(以下称作第1内层)。导体图案40的厚度约为15μm。导体图案40的一部分可用作与构成连接端子80的焊盘81、第1内层的与通孔导体90相连接的通孔连接盘91。
由铜等构成的导体图案50形成在电子部件内置线路板1的第2面(第1面的相反侧的主面)的内侧(以下称作第2内层)，该导体图案50的一部分成为第2内层的与通孔导体90相连接的通孔连接盘92。导体图案50的厚度约为15μm。第1内层的通孔连接盘91和第2内层的通孔连接盘92通过通孔导体90电连接。
由铜等构成的导体图案60形成在电子部件内置线路板1的第1面上(以下称作第1外层)，该导体图案60的一部分成为第1外层的与通孔导体90相连接的通孔连接盘93。导体图案60的厚度约为20μm。
由铜等构成的导体图案70形成在电子部件内置线路板1的第2面上(以下称作第2外层)，该导体图案70的一部分成为第2外层的与通孔导体90相连接的通孔连接盘94。导体图案70的厚度约为20μm。
连接端子80是用于与电子部件2的凸块20电连接的端子，其由焊盘81和接合层82构成。焊盘81的厚度约为15μm，接合层82的厚度约为15μm。
接合层82利用与焊盘81不同的金属形成在焊盘81上(即导体图案40上)。例如既可以通过采用了焊锡、锡、镍、金等金属、或者它们的合金等的电解电镀等来形成接合层82，也可以通过印刷焊锡膏、进行回流焊来形成接合层82。或者，也可以通过组合上述方法，而以多个层构成接合层82。但是，接合层82的最表层部优选由焊锡构成。
如上所述地构成的电子部件内置线路板1的特征在于，阻焊剂层112并未形成于导体图案层的整个表面上，而是局部地形成在导体图案层的的表面上。下面，参照图1A～图4E说明电子部件内置线路板1的制造方法。
(1)连接端子80的形成工序(图1A～图1H)
首先，准备图1A所示的支承基材100。支承基材100是使用粘接剂(剥离层)将铜箔101和由铜构成的载体102能够剥离(分开)地粘接而成的、所谓的带载体的铜箔。在此，铜箔101的厚度约为5μm，载体102的厚度约为70μm。另外，载体102并不限定于铜，也能够采用绝缘材料等。
接着，使用添加法在支承基材100的铜箔101上形成用于安装电子部件2的连接端子80。
另外，在利用添加法形成连接端子80之前，如图1B所示，利用无电解电镀、电解电镀、溅射等方法将镍等金属在支承基材100的铜箔101的整个表面上形成为厚度约为1μm来作为第1基底层110。
由此，能够防止由蚀刻导致的侵蚀，从而能够形成精细图案(fine pattern)。
另外，在像本实施方式这样地形成阻焊剂层112的情况下，如图1B所示，利用无电解电镀、溅射等方法将钛等金属在第1基底层110的整个表面上形成为厚度约为0.1μm来作为第2基底层111。由此，能够得到提高与阻焊剂层112的密合性这样的效果。
在此，添加法是指通过在没有形成抗镀层图案的部分电镀成长之后，除去抗镀层，从而形成导体图案的方法。
下面，具体说明采用该添加法形成连接端子80的过程。
在图1B中的基板的第2基底层111上层压干膜状的感光性抗蚀剂层103(参照图1C)。然后，在层压后的感光性抗蚀剂层103上密合掩模膜(mask film)，在紫外线下曝光并在碱性水溶液中显影。结果，形成仅是相当于导体图案40的部分开口的抗镀层104(参照图1D)。
接着，将图1D中的基板水洗，使其干燥之后进行电解镀铜，形成厚度约为15μm的镀铜层105(参照图1E)。
然后，通过剥离抗镀层104，能够得到形成有导体图案40和焊盘81的基板(参照图1F)。
然后，在图1F中的基板表面涂敷或者层压液状或干膜状的感光性抗蚀剂层(阻焊剂层)，形成厚度约为20μm的阻焊剂层。然后，使形成有规定图案的掩模膜密合在阻焊剂层的表面，用紫外线曝光并在碱性水溶液中显影。
结果，在图1F中的基板表面形成阻焊剂层112(参照图1G)。图6是表示图1G中的基板的一部分的俯视图。如图6所示，阻焊剂层112形成在图1G中的基板表面的与电子部件2的电路形成面相对应的区域。而且，在阻焊剂层112中设有多个用于使各焊盘81的表面暴露的开口部61。更严密地讲，阻焊剂层112的开口部61并未使各焊盘81的整个表面区域暴露，各焊盘81上方的至少一部分被阻焊剂层112所覆盖。
接着，在焊盘81上形成接合层82(参照图1H)。在本实施方式中，接合层82通过印刷焊锡膏并进行回流焊而形成。
此时，如上所述，阻焊剂层112形成在焊盘81的周围，因此，能够防止焊锡向除焊盘81之外的部分流出，从而易于在焊盘81上形成均匀且较高的接合层82。
像以上那样，能够得到用于与电子部件2的凸块20接合的连接端子80。
(2)电子部件2的安装工序(图2A、图2B)
接着，以面朝下(face down)的方式在图1H中的基板上载置电子部件2，使电子部件2的凸块20和连接端子80接合地安装该电子部件2(参照图2A)。
如上所述，接合层82均匀且较高地形成，因此，能够确保电子部件2的凸块20和连接端子80的连接可靠性。
在安装电子部件2之后，向电子部件2和基板之间产生的间隙中填充填底材料4(参照图2B)。
如上所述，填底材料4例如是含有二氧化硅、氧化铝等无机填料的绝缘性树脂。
(3)层叠工序(图3A～图3C)
接着，将绝缘材料30a和绝缘材料30b载置在图2B中的基板的电子部件2的安装面上(参照图3A)。绝缘材料30a、30b是在玻璃布等加强材料中浸渗树脂而成的板材(本实施方式中是预浸料)。绝缘材料30a与电子部件2的形状相结合地实施了除心加工，该绝缘材料30a以其安装面在平行的方向上包围电子部件2的形态载置。除心加工优选为冲裁加工法(冲孔)。另外，也可以使用机械钻头、激光等。
另一方面，绝缘材料30b未实施除心加工，为片状，其载置在绝缘材料30a上和电子部件2的与凸块20形成面相反的面上。
在载置绝缘材料30a、30b之后，将形成有导体图案50的基板500以导体图案50的形成面朝向绝缘材料30b侧地层叠在绝缘材料30b上(参照图3B、图3C)。作为该层叠方式，例如能够采用高压釜方式、水冲压方式等。
简单说明基板500的制造方法。首先，准备与支承基材100相同构造的支承基材(由厚度约为5μm的铜箔501和厚度约为70μm的载体502构成)。然后，在该支承基材上层压干膜状的感光性抗蚀剂层，然后，在层压的感光性抗蚀剂层上密合形成有规定图案的掩模膜并曝光、显影，从而形成仅是相当于导体图案50的部分开口的抗镀层。
然后，在将形成抗镀层后的基板水洗干燥之后进行电解镀镍等，形成厚度约为1μm的基底层503。然后，再进行电解镀铜，在基底层503上形成厚度约为15μm的镀铜层。然后，在除去抗镀层并水洗干燥时，能够得到形成有导体图案50的基板500。
在上述层叠时通过加压，绝缘材料30a和绝缘材料30b熔合，如图3C所示地形成绝缘材料3。另外，此时自绝缘材料30a、30b流出树脂成分，而使在电子部件2和绝缘材料30a、30b之间产生的空隙部被填充树脂5所填充。
(4)后工序(图4A～图4E)
接着，自图3C中的基板剥离(分离)载体102和载体502，得到图4A中的基板。然后，利用采用机械钻头等的已知的开孔法在图4A的基板上开设贯穿孔106(参照图4B)。在形成贯穿孔106之后，对图4B中的基板实施无电解镀铜，在两主面上及贯穿孔106的内壁上形成镀铜层113(参照图4C)。
然后，在图4C中的基板的两主面上层压干膜状的感光性抗蚀剂层，在该感光性抗蚀剂层上密合掩模膜，并进行曝光、显影。于是，形成仅与导体图案60相当的部分开口的抗镀层107、及仅与导体图案70相当的部分开口的抗镀层108(参照图4D)。
接着，在将图4D中的基板水洗并干燥之后进行电解镀铜，除去抗镀层107和108。于是，如图4E所示地形成镀铜膜109和通孔导体90。然后，使用能够选择性地蚀刻铜的蚀刻液除去图4E中的基板两主面上的不需要的镀铜层113、铜箔101和铜箔501。接着，使用能够选择性地蚀刻镍、钛等与铜不同的金属的蚀刻液除去第1基底层110和第2基底层111。
由此，能够得到形成有导体图案60(第1外层的通孔连接盘93)和导体图案70(第2外层的通孔连接盘94)的图4F所示的电子部件内置线路板1。
由于在蚀刻除去第1基底层110和第2基底层111时，使用能够选择性地蚀刻与铜不同的金属的蚀刻液，因此，导体图案40不会受到蚀刻的影响而被保护。
并且，由于焊盘81埋设在阻焊剂层112中，不自阻焊剂层112的表面突出，因此，蚀刻时难以引起图案变细，能够维持精细图案。
如上所述地制造的电子部件内置线路板1具有如下的优良的特征。
(1)由于收容(内置)电子部件2，因此，能够在表层的安装区域安装其他的电子部件等，从而能够实现高功能化。另外，通过倒装法安装内置的电子部件，能够谋求薄型化(小型化)。
(2)另外，通过(a)预先在支承基材100上形成电子部件安装用的连接端子80，(b)支承基材100的厚度较大(约75μm)，(c)利用添加法形成导体图案40和连接端子80等，能够以细间距(例如50μm)形成导体图案40和连接端子80。另外，由于支承基材100的载体102能够通过剥离容易地除去，因此，能够在除去无用的金属层时极力降低有可能对连接端子80施加的损伤。并且，由于形成的连接端子80和导体图案40在后工序中不被蚀刻等，因此，能够保持形成时的图案形状。因而，能够谋求提高图案精度。
(3)另外，由于收容的电子部件2被填底材料4、绝缘材料3所包覆、密封，因此固定强度较高。因此，在将电子部件内置线路板1作为芯基板的表面积层等多层化工序中，容易处理，而且，即使进行蚀刻等，也能够极力防止对电子部件2造成的影响。
(4)另外，电子部件内置线路板1具有绝缘材料(填底材料4和绝缘材料3)在电子部件2的安装面的下方及上方夹入该电子部件2的形态的构造(对称构造)。采用该对称构造时，能够缓和由压力(热量、振动冲击、落下冲击等)导致的应力，从而能够确保对于耐翘曲性。
并且，由于在电子部件内置线路板1的第1面上和第2面上分别形成有导体图案60和导体图案70，因此，耐翘曲性更高。
(5)另外，由于在导体图案40的形成层中用阻焊剂层112涂覆连接端子80的周围，因此，不会使不必要的部分附有焊锡，能够保护连接端子80，确保导体之间的绝缘性。并且，在导体图案40的形成层中，阻焊剂层112未形成于整个面，设有非形成部。即，将热膨胀率较高的阻焊剂的形成区域仅限制在必不可少的区域中。因此，能够降低基板的翘曲。
图5F是将图4F中的电子部件内置线路板1用作芯基板的多层线路板600的概略剖视图。参照图5A～图5E简单说明该多层线路板600的制造方法。
首先，在图4F中的电子部件内置线路板1的两主面上(第1面和第2面上)载置在玻璃布等加强材料中浸渗树脂而成的片状的板材(本实施方式中是预浸料)，再在其上载置轧制铜箔或电解铜箔，加热压接。结果，形成厚度约为40μm的绝缘层601、602、及厚度约为12μm的铜箔610、611(参照图5A)。
此时，由第1外层的通孔连接盘93和第2外层的通孔连接盘94挤出的树脂量与进入到通孔导体90的内部(空洞)中的树脂量相抵消。因而，绝缘层601和602的表面平坦化。
接着，利用二氧化碳(CO2)激光、UV-YAG激光等，在图5A中的基板两主面的规定部位形成激光通路孔(盲孔)612、613(参照图5B)。
然后，对图5B的基板的整个表面进行无电解镀铜，在两主面上及激光通路孔612和613的内表面形成镀铜层620(参照图5C)。
然后，在形成抗镀层621、622之后(参照图5D)进行电解镀铜，形成通路孔603、604和镀铜层614、615(参照图5E)。
然后，在图5E中的基板中，除去抗镀层621、622，蚀刻除去两主面上的无用的铜箔610、611和镀铜层620时，能够得到形成有导体图案605、606的多层线路板600(参照图5F)。
另外，本发明并不限定于上述实施方式，能够在不脱离本发明主旨的范围内进行各种变更。
例如，阻焊剂层112的形成形态并不限定于图6所示的形态。例如在电子部件2的凸块20排列成围绕型的情况下，也可以如图7所示地将阻焊剂层112的开口部61做成矩形框状。
在这种情况下，既可以如图8所示地由阻焊剂层112覆盖各焊盘81之间的区域，也可以如图9所示地在与电子部件2的电路形成面相对应的区域的中央部设置非形成区域。
另外，为了提高阻焊剂层和导体图案层的密合性，也可以在形成阻焊剂层之前利用黑化处理、化学蚀刻处理(CZ处理)等表面粗化法将导体图案层的表面粗化。
另外，上述实施方式的多层线路板600在电子部件内置线路板1的两主面上分别层叠绝缘层601、602和由导体图案605、606构成的层各1层，但并不限定于该构造。即，也可以层叠两层以上，两主面上的层叠数也可以不同。并且，也可以仅层叠在一侧的主面上。
本申请以2008年11月6日做出的美国临时专利申请61/112035为基础。在本说明书中，参照编入该说明书、权利要求范围、整个附图。
工业实用性
本发明的技术能够广泛地应用于将电子部件收容在内部的线路板。

Claims (18)

1.一种电子部件内置线路板，该电子部件内置线路板利用倒装法安装而内置有电子部件，其特征在于，
该电子部件内置线路板包括：导体图案层、设置于该导体图案层且与上述电子部件电接合的连接端子、形成在上述导体图案层上的阻焊剂层；
上述阻焊剂层形成在上述导体图案层上的上述连接端子的周围，在上述导体图案层上的其他区域中的至少一部分区域上不形成上述阻焊剂层。
2.根据权利要求1所述的电子部件内置线路板，其特征在于，
上述连接端子包括由与上述导体图案层不同的金属形成在上述导体图案层上的接合层。
3.根据权利要求2所述的电子部件内置线路板，其特征在于，
上述接合层由焊锡构成。
4.根据权利要求1所述的电子部件内置线路板，其特征在于，
上述阻焊剂层覆盖上述导体图案层的上述连接端子形成区域的至少一部分。
5.根据权利要求1所述的电子部件内置线路板，其特征在于，
上述电子部件被绝缘材料所覆盖，在该绝缘材料上形成有通孔导体。
6.根据权利要求5所述的电子部件内置线路板，其特征在于，
上述导体图案层不自上述绝缘材料的表面突出。
7.根据权利要求1所述的电子部件内置线路板，其特征在于，
在上述电子部件上形成有用于与上述连接端子接合的凸块。
8.根据权利要求1所述的电子部件内置线路板，其特征在于，
上述导体图案层的表面被粗化。
9.根据权利要求7所述的电子部件内置线路板，其特征在于，
上述电子部件的凸块配置在电路形成面的端部。
10.一种电子部件内置线路板的制造方法，其特征在于，
包括以下工序：
在支承体上配置金属箔而成的层叠基材的上述金属箔上形成导体图案层；
在上述导体图案层上的一部分区域形成设有规定的开口部的阻焊剂层；
通过在与上述阻焊剂层的开口部相对应的上述导体图案层上设置接合层，形成连接端子；
将上述电子部件以该电子部件的电路形成面和上述连接端子的形成面相对的方式配置在上述层叠基材上，而使上述电子部件和上述连接端子电连接；
用绝缘材料包覆上述安装后的电子部件；
除去上述支承体；
除去暴露的上述金属箔。
11.根据权利要求10所述的电子部件内置线路板的制造方法，其特征在于，
上述接合层由与上述导体图案层不同的金属构成。
12.根据权利要求11所述的电子部件内置线路板的制造方法，其特征在于，
上述接合层由焊锡构成。
13.根据权利要求10所述的电子部件内置线路板的制造方法，其特征在于，
该电子部件内置线路板的制造方法还包括在用上述绝缘材料包覆上述电子部件之后，在上述绝缘材料中设置贯穿孔而形成通孔导体的工序。
14.根据权利要求10所述的电子部件内置线路板的制造方法，其特征在于，
上述导体图案层利用电解电镀形成。
15.根据权利要求10所述的电子部件内置线路板的制造方法，其特征在于，
在上述电子部件上形成有用于与上述连接端子接合的凸块。
16.根据权利要求10所述的电子部件内置线路板的制造方法，其特征在于，
该电子部件内置线路板的制造方法还包括在形成上述导体图案层之后，形成上述阻焊剂层之前，将上述导体图案层的表面粗化的工序。
17.根据权利要求10所述的电子部件内置线路板的制造方法，其特征在于，
该电子部件内置线路板的制造方法还包括在安装上述电子部件之后，在上述连接端子的周围填充绝缘性树脂的工序。
18.根据权利要求15所述的电子部件内置线路板的制造方法，其特征在于，
上述电子部件的凸块配置在电路形成面的端部。
CN2009801326496A 2008-11-06 2009-03-10 电子部件内置线路板及其制造方法 Pending CN102132639A (zh)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103681526A (zh) * 2012-09-21 2014-03-26 Tdk株式会社 半导体ic内藏基板及其制造方法
CN105188252A (zh) * 2014-02-25 2015-12-23 摩托罗拉解决方案公司 用于使印刷电路板的大小小型化的装置和方法

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102009032895B4 (de) 2009-07-10 2016-06-23 Chevita Tierarzneimittel-Gesellschaft M.B.H. Zusammensetzung und Verfahren zur Prävention und Behandlung von Feuerbrand
US8653670B2 (en) 2010-06-29 2014-02-18 General Electric Company Electrical interconnect for an integrated circuit package and method of making same
US9570376B2 (en) 2010-06-29 2017-02-14 General Electric Company Electrical interconnect for an integrated circuit package and method of making same
US8643154B2 (en) * 2011-01-31 2014-02-04 Ibiden Co., Ltd. Semiconductor mounting device having multiple substrates connected via bumps
KR101144610B1 (ko) * 2011-08-02 2012-05-11 한국기계연구원 투명 전극의 전도성 메쉬 매설 방법
US8946072B2 (en) * 2012-02-02 2015-02-03 Taiwan Semiconductor Manufacturing Company, Ltd. No-flow underfill for package with interposer frame
US8766461B1 (en) * 2013-01-16 2014-07-01 Texas Instruments Incorporated Substrate with bond fingers
JPWO2014118917A1 (ja) * 2013-01-30 2017-01-26 株式会社メイコー 部品内蔵基板の製造方法
US9659891B2 (en) 2013-09-09 2017-05-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device having a boundary structure, a package on package structure, and a method of making
US10037941B2 (en) * 2014-12-12 2018-07-31 Qualcomm Incorporated Integrated device package comprising photo sensitive fill between a substrate and a die
US10475750B2 (en) * 2016-04-02 2019-11-12 Intel Corporation Systems, methods, and apparatuses for implementing an organic stiffener with an EMI shield for RF integration
WO2019154822A1 (en) 2018-02-06 2019-08-15 Bjoersell Sten Manufacture of electronic circuits

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58148434A (ja) * 1982-02-26 1983-09-03 Mitsubishi Electric Corp 電気部品実装基板の製造方法
JPS61127671U (zh) * 1985-01-29 1986-08-11
JPH0247087U (zh) * 1988-09-27 1990-03-30
JPH0268474U (zh) * 1988-11-15 1990-05-24
JPH08242064A (ja) * 1995-03-01 1996-09-17 Ibiden Co Ltd プリント配線板
EP1843650B1 (en) * 1998-09-03 2012-03-07 Ibiden Co., Ltd. Method of manufacturing a multilayered printed circuit board
EP1259103B1 (en) * 2000-02-25 2007-05-30 Ibiden Co., Ltd. Multilayer printed wiring board and method for producing multilayer printed wiring board
JP3916854B2 (ja) * 2000-06-28 2007-05-23 シャープ株式会社 配線基板、半導体装置およびパッケージスタック半導体装置
JP3547423B2 (ja) * 2000-12-27 2004-07-28 松下電器産業株式会社 部品内蔵モジュール及びその製造方法
JP3553043B2 (ja) * 2001-01-19 2004-08-11 松下電器産業株式会社 部品内蔵モジュールとその製造方法
JP2002237682A (ja) * 2001-02-08 2002-08-23 Cmk Corp 部品実装用凹部を備えた多層プリント配線板及びその製造方法
JP3709882B2 (ja) * 2003-07-22 2005-10-26 松下電器産業株式会社 回路モジュールとその製造方法
JP2005129663A (ja) * 2003-10-22 2005-05-19 Internatl Business Mach Corp <Ibm> 多層配線基板
JP2006310421A (ja) * 2005-04-27 2006-11-09 Cmk Corp 部品内蔵型プリント配線板とその製造方法
US7640655B2 (en) * 2005-09-13 2010-01-05 Shinko Electric Industries Co., Ltd. Electronic component embedded board and its manufacturing method
JP4766049B2 (ja) * 2005-09-20 2011-09-07 株式会社村田製作所 部品内蔵モジュールの製造方法および部品内蔵モジュール
JP2007214230A (ja) * 2006-02-08 2007-08-23 Cmk Corp プリント配線板

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103681526A (zh) * 2012-09-21 2014-03-26 Tdk株式会社 半导体ic内藏基板及其制造方法
CN103681526B (zh) * 2012-09-21 2016-06-29 Tdk株式会社 半导体ic内藏基板及其制造方法
US9635756B2 (en) 2012-09-21 2017-04-25 Tdk Corporation Circuit board incorporating semiconductor IC and manufacturing method thereof
CN106024725B (zh) * 2012-09-21 2018-12-28 Tdk株式会社 半导体ic内藏基板及其制造方法
CN105188252A (zh) * 2014-02-25 2015-12-23 摩托罗拉解决方案公司 用于使印刷电路板的大小小型化的装置和方法

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