WO2019154822A1

WO2019154822A1 - Manufacture of electronic circuits

Info

Publication number: WO2019154822A1
Application number: PCT/EP2019/052813
Authority: WO
Inventors: Sten BJÖRSELL
Original assignee: Bjoersell Sten
Priority date: 2018-02-06
Filing date: 2019-02-05
Publication date: 2019-08-15

Abstract

A method of manufacturing a multi-layer circuit includes providing a first layer (11, 15) with an insulating substrate (11) and conductors (15, 16). This may ultimately form an external layer for a circuit. A solder mask (30, 31) is applied to expose conductor areas (19, 20) to provide component pads. Solder paste (42) is deposited in mask openings to provide solder deposits on the component pads. Components (40, 41) are placed on the solder paste deposits. The solder paste is caused to reflow by heating and it is cooled to cure the solder to secure the components in place. One or more solid resin layers (50) with holes (60) for the components (40) are placed over the first layer, and the assembly is pressed to cause flow of resin (53) from the resin layer or layers (50) around the components to encapsulate the components.

Description

“Manufacture of Electronic Circuits”

Introduction

The invention relates to manufacture of circuits.

US Patent No. US7485489 describes an approach to manufacturing circuits, in which components are embedded using prepreg resin flow. At least one electrical connection can be made to the component through an external layer by drilling a via through layers and plating the via so that the plating inter-connects a conductor land and a component terminal.

JP2006-310421 (Nippon) describes a manufacturing method for a component board in which there is thermo-compression bonding with applied pressure.

US2010/108371 (Ibiden) describes manufacturing of a wiring board with flip-chip components.

US2011/0193203 (Renesas) describes a multilayer wiring board in which a semiconductor chip is embedded.

The invention is directed towards increasing versatility in manufacture of electronic circuits. Another objective is to provide improved robustness and resistance to de-lamination in the circuit.

Summary of the Invention

We describe a method of manufacturing a multi-layer circuit, comprising:

(a) providing a first layer with an insulating substrate and conductors,

(b) applying a solder mask to the first layer, in which the mask leaves one or more component pads exposed,

(c) depositing solder paste on said one or more component pads,

(d) placing one or more SMT components on said solder paste,

(e) heating to reflow the solder paste, and cooling to cure the paste to provide solder which secures the components in place,

(f) placing over the first layer one or more solid uncured resin layers with clearances or the components, wherein said resin layer and said solder mask are of a compatible composition for bonding under application of heat, (g) pressing to cause flow of resin from the one or more resin layer around the components to encapsulate the components and bond the resin to the solder mask, wherein the solder mask is of a type of material to both prevent oxidation of the first layer conductors and to also bond with the resin during and after resin flow, and

(h) making electrical connections between external conductors and said conductors on the first layer to provide electrical paths from the external conductors and said component pads,

wherein the solder mask is only partially cured before step (g) so that it is more susceptible to cross-linking with a resin in step (g) than if it were fully cured.

Preferably, the duration of solder reflow of step (e) is in the range of 2 to 30 seconds, so that the solder mask retains its cross-linking ability after solder reflow.

Preferably, the steps (c) to (e) are performed at a temperature not exceeding a maximum temperature, for example l50°C.

Preferably, the solder mask is of an epoxy material and said resin of step (f) comprises a compatible epoxy. Preferably, the solder mask comprises UV imageable and bondable solder mask. Preferably, the first layer of step (a) comprises tracks and component pads.

Preferably, the first layer of step (a) comprises pads for subsequent vertical connectivity to the tracks. Preferably, the solder paste of step (c) has a melting point higher than a temperature of the subsequent encapsulation press temperature in step (g). Preferably, the solder reflow temperature of step (e) is in the range of l85°C to 250°C.

Preferably, an adhesive is used to additionally secure the components in place.

Preferably, the method comprises the further step of anti- oxidation treatment after solder masking, so that conductors which are not covered by the solder mask are protected from oxidation, and in which pads on the first layer for vertical connectivity are masked. In one example, the anti- oxidation treatment is by immersion.

Preferably, the method comprises the further step of in-circuit testing after component placement. Optionally, step (b) includes the mask leaving gaps on the tracks for in-circuit testing contact pins. Preferably, the conductors on the first layer include connectivity pads for said vertical connectivity, and said pads are covered by the mask, and wherein said in-circuit testing gaps are spaced apart from said connectivity pads, and wherein the in-circuit testing gaps are protected from oxidation by a treatment used to protect the solder pads, by immersion in an anti- oxidation solution.

Preferably, the pressing step (g) is performed at a temperature lower than the solder melting point, to prevent component displacement during pressing.

Optionally, the step (g) encapsulation is performed at a temperature at least lO°C lower than melting point of the solder. Preferably, the resin layers (50) comprise woven glass weave impregnated with resin.

Optionally, the step (h) comprises drilling a via and lining the via to provide plated through holes for vertical connectivity between the first layer conductors and any other layer or layers.

Preferably, the conductors on the first layer include connectivity pads for said vertical connectivity by provision of plated through holes through said pads.

Preferably, the method comprises steps of providing at least one external layer having conductors, and said step (h) provides electrical connections between the conductors of said external layer to said conductors in the first layer.

Preferably, top and bottom external layers with conductors are provided, and connections are made from said conductors of both said external layers to said first layer and/or to an additional layer between said external layers.

Optionally, the solder reflow temperature is in the range of l85°C to 250°C, and said resin flow temperature is at least 5°C lower than the solder reflow temperature.

Preferably, the method comprises the further steps of repeating steps (a) to (g) for each of a plurality of layers to provide second and optionally subsequent layers with encapsulated components, or providing subsequent layers with components and performing resin flow simultaneously for some or all internal layers.

Preferably, components are placed on only one side of an insulating substrate, both sides of said substrate are solder masked to achieve oxidation protection and bondability of both sides to said resin and to avoid exposure of components and solder joints to oxide treatment chemicals that may deteriorate both components and solder_^

We also describe a multi-layer circuit manufactured by a method including the steps of a method of any embodiment. In one example, we describe a multi-layer circuit comprising a substrate having an internal surface, solder mask on part of said substrate surface, encapsulated components placed on solder in electrical connection with conductors on the substrate, wherein the components are encapsulated in resin which bonds with the solder mask.

In one example, the circuit includes an external conductor, and said external conductor is connected to said substrate conductors by plated through holes.

The circuit may comprise an interposer and said components include resistors for electrical terminations for a device.

We also describe a device comprising a circuit of any embodiment.

Additional Statements

In one aspect, we describe a method of manufacturing a multi-layer circuit, comprising providing a first layer with an insulating substrate and conductors, and applying a solder mask to the first layer which leaves one or more component pads exposed. Solder paste may be deposited on one or more component pads, one or more SMT components placed on the solder paste, which is re- flowed. Uncured resin layers are placed, with clearances for the components, and there is pressing to cause flow of the one or more resin layer around the components to encapsulate the components and bond the resin to the solder mask. Preferably, the solder mask is of a type of material to both prevent oxidation of the first layer conductors and to also bond with the resin during and after resin flow. In one embodiment electrical connections are made between external conductors and the conductors on the first layer to provide electrical paths from the external conductors and said component pads. In one aspect, we describe a method of manufacturing a multi-layer circuit, comprising:

(a) providing a first layer with an insulating substrate and conductors,

(b) applying a solder mask to the first layer which leaves one or more component pads exposed,

(c) depositing solder paste on said one or more component pads,

(d) placing one or more SMT components on said solder paste,

(e) heating to reflow the solder paste, and cooling to cure the solder which secures the components in place,

(f) placing over the first layer one or more solid uncured resin layers with clearances for the components, wherein said resin layer and said solder mask are of a compatible composition for bonding under application of heat,

(g) pressing to cause flow of the one or more resin layer around the components to encapsulate the components and bond the resin to the solder mask, wherein the solder mask is of a type of material to both prevent oxidation of the first layer conductors and to also bond with the resin during and after resin flow, and

(h) making electrical connections between external conductors and said conductors on the first layer to provide electrical paths from the external conductors and said component pads.

Preferably, the first layer of step (a) comprises tracks and component pads and, optionally, plated through connections. Preferably, the first layer of step (a) comprises pads for subsequent vertical connectivity to the tracks.

Preferably, the step (b) includes partially curing the solder mask, so that it is more susceptible to cross-linking with a resin than if it were fully cured. Preferably, the partial curing is performed at a temperature not exceeding a maximum temperature, for example l50°C.

The solder paste of step (c) may have a melting point higher than a temperature of the subsequent encapsulation press temperature in step (g). Preferably, the solder mask is of an epoxy material and said resin of step (f) comprises a compatible epoxy. The solder reflow temperature of step (e) may be in the range of l85°C to 250°C.

Preferably, the duration of solder reflow of step (e) is in the range of 2 to 30 seconds, so that the solder mask retains its cross-linking ability after solder reflow. An adhesive may be used to additionally secure the components in place. The method may have the further step of anti-oxidation treatment, so that conductors which are not covered by the solder mask are protected from oxidation, and in which pads on the first layer for vertical connectivity are masked. The anti-oxidation treatment may be by any suitable type of immersion. The method may have the further step of in-circuit testing after component placement. The step (b) may include the mask leaving gaps on the tracks for in-circuit testing contact pins.

Preferably, the gaps are spaced apart from locations for vertical connectivity to the tracks, and wherein the test gaps are protected from oxidation by a treatment used to protect the solder pads, by immersion in anti-oxidation solution or HASL The conductors may be on the first layer and include pads for said vertical connectivity, and these pads are covered by the mask.

The pressing step (g) may be performed at a temperature lower than the solder melting point, to prevent component displacement during pressing. The step (g) encapsulation may be performed at a temperature at least lO°C lower than melting point of the solder. The resin layers may comprise woven glass weave impregnated with resin.

The step (h) may comprise drilling a via and lining the via to provide plated through holes for vertical connectivity between the first layer conductors and any other layer(s). The method may comprise steps of providing at least one external layer having conductors, and said step (h) provides electrical connections between the conductors of said external layer to said conductors in the first layer.

Preferably, top and bottom external layers with conductors are provided, and connections are made from said conductors of both said external layers to said first layer and/or to additional layer(s) between said external layers.

Preferably, the solder reflow temperature is in the range of l85°C to 250°C, and said resin flow temperature is at least 5°C lower than the solder reflow temperature.

The method may comprise further steps of repeating steps (a) to (g) for each of a plurality of layers to provide second and possibly subsequent layers with encapsulated components, or providing subsequent layers with components and performing resin flow simultaneously for some or all internal layers. The solder mask may comprise UV imageable bondable solder mask. We also describe a multi-layer circuit manufactured by a method including the steps of any embodiment. We also describe a multi-layer circuit comprising a substrate having an internal surface, solder mask on part of said substrate surface, encapsulated components placed on solder in electrical connection with conductors on the substrate, wherein the components are encapsulated in resin which bonds with the solder mask.

The circuit may have an external conductor, and said external conductor is connected to said substrate conductors by plated through holes.

The circuit of any embodiment may be incorporated in a device of any of a wide range of types, including communication devices, servers, sensors, any type of user device, and the invention includes any such device.

Detailed Description of the Invention

The invention will be more clearly understood from the following description of some embodiments thereof, given by way of example only with reference to the accompanying drawings in which :-

Fig. 1 is a perspective view of a first layer provided at initial stages of manufacture of a multi-layer circuit;

Fig. 2 is a cross-sectional view through the layer in the direction of the arrows A-A, showing conductors leading from edges to terminals or lands;

Fig. 3 is a sectional view in the same plane after application of a solder mask;

Fig. 4 is a plan view after application of a solder mask;

Fig. 5 is a sectional view showing the layer after solder paste is applied and placement of a component;

Fig. 6 is a perspective view showing placement of a prepreg layer and an external layer;

Fig. 7 is a sectional view showing the layers after pressing; Fig. 8 is a staggered cross-sectional view showing the layers after resin flow and drilling of vias and plating them to interconnect external pads to the internal layer conductors to provide a final product;

Fig. 9 is a plot of both pressure and temperature vs. time for a pressing operation to cause resin flow during board manufacture;

Fig. 10 is a set of plots for temperature vs. time in minutes for zones of SMT lead- free soldering; and

Fig. 11 is a diagrammatic cross-sectional view of a circuit manufactured according to the invention and on which is mounted a ball grid array (BGA).

In a manufacturing process, a circuit is built up with multiple layers, one or more of which have components and associated conductors on the internal layers and linked with external layers.

First Layer

Referring to Figs. 1 and 2 a first layer comprises:

11, laminate,

12, underlying copper,

14, Cu conductors.

In this example the circuit is for an interposer to act as a terminator for a PCB and a ball grid array (BGA), the main purpose of the interposer being to provide resistances on the conductor terminations. Hence, many of the components which are encapsulated are resistors.

The Cu conductors 14 include tracks 15, 16, 17 and 18 leading to pads 19, 20, 21, and 22 respectively. There are also disc-shaped pads 25 for subsequent plated through hole (PTH) connectivity, as described in more detail below. The first layer may, for example, comprise one side of a multilayer core such as a double-sided fibreglass epoxy sheet with copper foil 332 g/m² (1 oz /sq ft). Typically etched on both sides to later be pressed together with prepreg and copper foils, sometimes with several other cores, all interspaced with prepreg to bond them together during the hot multilayer pressing step. Copper patterns are etched by standard photoresist methods involving photomechanic al and chemical selective removal. After solder masking the solder pads and all exposed copper is immersed in anti-oxidation treated at the same time as described for solder pads earlier.

Solder Mask

As shown in Figs. 3 and 4 a solder mask 30 is applied, including over the tracks 15 to 18 and the pads 25. The mask 30 leaves gaps over the pads 19 to 22 and any other SMT component pads, however not over the pads 25.

Additionally, openings 35, 36, 37, and 38 in the solder mask 30 are added. The openings 35, 36, 37, and 38 are away from plated through hole (PTH) locations at the pads 25 to avoid risk of metals from surface treatment contaminating the chemical baths subsequently used to metallize the holes. These openings are for in-circuit electrical testing of the assembly before encapsulation, which is described in more detail below. The solder mask openings are made photo-mechanically and best with LDI (Laser Direct Imaging) that can provide resolution of openings 50 pm and less.

Fig. 4 shows that the copper tracks 15, 16, 17, and 18 are covered with solder mask 30 except at the test points 35, 36, 37 and 38. In the embodiment illustrated, the pads to which components are to be soldered are large squares 19, 20, 21 and 22.

The solder mask 30 performs the multiple purposes of:

(a) preventing solder bridging during reflow soldering,

(b) protection of the copper from oxidation,

(c) preventing chemical solutions from contaminating subsequent via-lining processes, and

(d) allowing subsequent bonding of resin during and after resin flow, as described in more detail below.

In order to achieve the objectives, the mask properties are photo-imageable, curable and bondable. Regarding objective (d) the solder mask cures sufficiently for standard solder mask purposes up to about l50°C while also retaining cross linking capability for subsequent bonding to prepreg during pressing. The mask 30 is partially cured at a temperature of just less than l50°C for a duration of, for example, 45 minutes. This allows it to perform its masking functions, but it is not fully cured. Therefore, during the subsequent resin flow it is particularly well able to bond by cross-linking with prepreg resin. Importantly, the mask is not allowed or caused to cure before cross-linking bonding with the resin flowing from the prepreg during pressing. Hence, in the processing before resin flow the times and elevated temperatures are controlled to ensure that they do not cause premature mask curing, thereby ensuring that the cross-linking properties remain.

Oxidation Protection Treatment

There is then oxidation protection treatment by immersion so that the conductor surfaces which are not covered by the solder mask 30 are protected from oxidation. Hence, bare copper is treated to provide solderability. Alternatively, oxidation treatment of inner layer copper 14 to achieve bond strength between copper and prepreg at pressing may be done instead of application of the solder mask, but it is not selective.

Solder Paste

Referring to Fig. 5 solder paste 42 is applied on the pads 19 to 22 respectively, according to the mask 30 and a screen printing stencil with openings for the pad locations. The solder paste preferably has a melting point over the subsequent encapsulation (described below) press temperature.

Component Placement

Electronic components 40 are placed on the solder deposits and across opposing pads 19/20 and 21/22, using conventional surface mount technology equipment.

After the solder paste 42 and the components 40 have been applied, the components 40 are soldered to the printed circuit board (PCB) by reflowing in a standard SMT (surface mount technology) soldering oven. The parameters are those suitable for the particular solder paste 42. The components 40 are thereby electrically connected to the tracks 15, 16, 17, and 18 and securely held in place. In one embodiment, the solder reflow temperature is in the range of l85°C to 250°C. The duration of solder reflow is short enough (for example, 2 to 30 seconds) for the SMT solder requirements, but not long enough for curing of the solder mask. Therefore, the solder mask retains a-cross -linking ability after solder reflow.

In-circuit Testing

There is then in-circuit testing. This does not use copper pads (25) that later during the circuit completion process are drilled. That is why the openings 35-38 are provided as test points on the Cu conductors 14. Hence, the parts of the conductors 14 that will be connected by the PTH processing are fully covered by the solder mask 30 before drilling, and therefore there is no need for any other protection such as oxide protection. Because of this, during drilling there is no risk of oxidation protection material contaminating the chemical processes to line the drilled vias. This avoids exposure of pads coated with oxide-resistant metal or coating to chemical solutions that could be contaminated by such metals. Also, it avoids exposing and thus potential corrosion of these metals that could cause voids in PTHs.

The test points consist of the openings 35-38, which are of sufficient size to expose copper to be coated with protection coating (e.g. HASL, Immersion Tin, Immersion Silver) used before soldering and before testing. If permissible and required, test points can be enlarged.

The testing is best exemplified in Fig. 4 in which the openings 35, 36, 37 and 38 on the tracks 15, 16, 17 and 18 on either side of each resistor allow testing if close enough to nominal effective values if single, or otherwise depending on how connected.

The testing, after the components are soldered in place on the large pads 19-22, can (for small volume runs) best take place with a "Flying probe tester" that is programmed to put probes on the relevant test points 35, 36, 37 and 38 and do the actual testing by means of algorithms for which suitable hardware and software are built into these ready-made machines. Resistances, inductances, capacitances etc., can hence be measured as required before pressing to maximize end yield.

Resin Sheets

As shown in Figs. 6 and 7, a prepreg (solid resin with embedded fibres) layer 50 is applied. The prepreg layer 50 has an aperture 60 to accommodate the components 40. The prepreg layer 50 comprises woven glass weave impregnated with resin, fully compatible with the solder mask resin.

In other examples, two or more prepreg layers may be applied to achieve required thickness for component clearance thickness and resin volume requirements.

A top layer 55 is then applied, as an external layer. The top external layer comprises a main body of laminate and copper, or copper foil over underlying prepreg 50. There are pads 71 and 72, later formed by PCB processes on the top surface, shown in Fig. 7. Resin Flow - Encapsulation

The assembly is then pressed at up to approximately 30,000 kPa (30 Bar) pressure and up to approximately 200°C temperature as maximums, to flow and set the resin 53 in the prepreg layer 50, depending on the resin system employed. The lamination (pressing) cycle is started under partial vacuum to avoid air and moisture inadvertently being encapsulated in the finished products. The pressing step may be as described in my earlier patent US7485489. The result of the pressing operation is that resin 53 flows from the sheets 50 as resin melts, the resin 53 flowing into cavities beneath and over the components 40. In general much of the bulk of the original resin layer or sheet 50 remains in place, but it will be thinner due to the outflow of resin 53.

The pressing is performed so that the temperature at the internal layer remains at least 5°C, and preferably at least l0°C below the solder melting point. If there is a risk that the solder melt temperature will be too close to the pressing temperature, the components can also be glued in addition to being soldered. Alternatively, a solder with higher melting point can be used.

Advantageously, there is bonding of the solder mask 30 to the prepreg 50. Excellent bonding of the solder mask 30 to the prepreg 50 is achieved when both the prepreg and the mask 30 are epoxy-based. As mentioned above, advantageously, the solder mask is not fully cured, and this aids the bonding between the solder mask 30 and the prepreg 50, resulting in a particularly effective bond.

As noted above, the conditions are that the solder mask 30 curing temperature, before pressing, does not exceed l50°C, and so it has an excellent cross-linking ability with the resin during encapsulation. The multilayer press temperature is maintained at l80°C for FR4 for a minimum time of approximately 45 minutes. This causes the mask to cure, but not before it has cross- linked for excellent bonding with the resin.

Advantages of how the solder mask is used in the method include:

Cores with inner layers for multilayers can be prepared and processed with standard SMT assembly processes, the same as for standard outside layers of PCBs;

No exposure of solder or electronic components to often harsh chemical baths for copper oxide treatment with resulting unpredictable build-up of contaminations; No potential deterioration of solder joints and/or components from exposure to harsh chemical baths;

The use of oxide treatment of inner layer copper before pressing is not selective like photoimageable solder mask is, and cannot therefore prevent solder bridging protection, most important with high solder pin density.

In Fig. 7 the components 40 and 41 are completely encapsulated by prepreg resin which has flowed and cured, represented by the numeral 51, and the top (external layer) 55 and the lowermost part 12 form external parts of the circuit. Figs. 7 and 8 show what remains of the prepreg after resin flow between structures 11 and 55. The body 51 to the sides of the component are shaded more heavily than under the components because it has more glass fibre content, the material under the component having little or no fibre, only flowed and cured resin from the prepreg.

Electrical connection of external pads and other conductors to the tracks 14 is achieved by drilling through the pads 71 and 72 and all or part of the layers through to the bottom conductive sub-layer 12. The example via holes are plated by standard PCB plating methods to provide plated through holes 77 and 78 with through holes 75 and 76 respectively.

In various embodiments, there may be an external layer, and if there is it may not have external copper. For example, the layer 55 may be replaced by a copper foil applied over the prepreg and etched according to the electrical requirements.

Where there is an external layer, it may be a single or a double copper cladded core etched to electrical requirements, and plated through before and/or after pressing, to electrical requirements. All the variants that a multilayer can be built with can also be applied with suitable components on one or more internal layers provided these are soldered and kept in place and prepreg is opened up for them so that no direct mechanical pressure to components is ever applied during pressing, only symmetric liquid pressure later during the prepreg resin flow phase. Once encapsulated in a pressing, the components are protected from chemicals in subsequent processing, in case of repeat embedding of a PCB with embedded components.

Fig. 8 shows example PTHs 77 and 78 and the conduction paths for this (small) example cross- section are therefore:

71 - 77 - 15 - 19 - 42 - 40, and from 71-12 (via the PTH 77); and 72 - 78 - 16 - 20 - 42 - 40, and from 72 to 12 (via the PTH 78).

The PTHs 77 and 78 are examples to illustrate the process methodology. PTH holes can be at any of a wide variety of locations interconnecting nearly any layers according to the circuit design. The left hand PTH 77 is not in the same plane as the PTH 78, it is offset from the conductor track 15 because it does not coincide with the test point 35.

Referring to Fig. 9, temperature and pressure profile is shown for one example of pressing for resin flow. With an applied pressure of about 2MPa the internal temperature rises to about 200°C for a duration of about 80 mins to 90 mins. This ensures full resin flow into the cavities below and above the components 40, and of course full cross-linking of the resin with the mask 40 which is initially only partially cured, and thermosetting of resin.

Referring to Fig. 10, some temperature plots are shown for the SMT component soldering. The zones Zl to Z6 are set up for gradual heating of the board and components. The zones are consecutive areas with gradually rising temperature in a continuous oven to achieve smooth temperature rise of the board for assembly. Small isolated areas and larger areas attached to heat sinks inside the board will then be heated up more evenly

Referring to Fig. 11, an example end product of the manufacturing method is illustrated. This is a circuit 100 on which is mounted a ball grid array (BGA) 200, and in which the circuit 100 is an interposer for the BGA 200. The circuit 100 comprises cured resin 101 in three main layers, and which during the method provided the outflow resin for surrounding components 110, in this case resistors and capacitors. There are through holes 102 to act as side edges of the circuit 100, and PTHs 120 for connectivity through the circuit 100. There are also PTHs 120 which terminate within the circuit, for connection of an external conductor 125 to an internal component 110.

In general, the invention is particularly suited to applications requiring terminations of transmission lines, as in the BGA example.

It will be appreciated that the buried and encapsulated components are electrically connected with standard soldering technology and methods, instead of drilling and plating directly to the component, but can of course be combined with that. The soldering methods include the application of the solder paste deposits, and subsequent solder reflow, all performed using standard solder equipment and process parameters.

The maximum pressing temperature is typically l80°C to 200°C, whereas the melting point of lead-free solder is typically higher, preventing unwanted movement of components during resin flow stage. Using a solder with a higher melting point than the pressing temperature allows the use of standard soldering technology also for components inside the PCB.

When the PCB is completed and soldered at temperatures sufficient to melt the primary solder joints, solder joints are already encapsulated in set resin, disabling movement but-allowing expansion.

The solder mask is used on the inner layers for the purpose of enabling selective surface treatment of solder pads and test points, preventing unwanted solder bridging, and providing oxidation protection of copper before soldering and/or testing and it also replaces bond- promoting oxide treatment of copper surfaces with a bondable solder mask. When only one side of a component carrying core has components, both sides are solder masked to achieve oxidation protection and bondability of both sides to avoid exposure of components and solder joints to oxide/treatment chemicals that may deteriorate both components and the chemicals. All copper pads for plated though holes on both sides are covered with solder mask for reasons already explained.

For components with small footprints and thickness, a suitable number of surrounding prepreg can be drilled instead of routed. For mass production, prepreg can of course alternatively be punched.

It will be appreciated that the diagrams illustrate only a very small part of a circuit. In practice there may be for example in the order of hundreds of components of any different type within an area of for example 20 mm x 20 mm, on one or several levels and not limited to that.

The use of the solder mask is particularly important both due to its standard function and due to its functions as a bonding agent avoiding the need for oxide treatment of copper which is covered by the mask. The solder mask is already bonded to copper on one side and resin will bond to suitably selected and cured solder mask on the other. For the application of controlled impedance traces, the traces themselves are typically manufactured with +/-l0% tolerance, and they must have matching termination resistors which can be impossible to fit on outside layers, for instance with high density BGAs.

Options used inside PCBs include carbon printed resistors and special etched resistance foil layers.

Carbon printing can only meet +/-20% tolerance, while resistance foil can provide +/-l0% or +/- 5% at high extra cost.

Standard resistors size 0.2 x 0.4 mm are however readily available with +/-l% tolerance in impedance at low cost, typically from less than 1 to 5 US$ cents each. The total worst case tolerance is the sum of the trace impedance tolerance. The method of the invention will render a worst case tolerance of +/-l l% with the use of internal resistors of tolerance +/- 1%, which is substantially better than standard methods while the nearest standard solution would have +/- 20% as a worst tolerance.

The invention is not limited to the embodiments described but may be varied in construction and detail. For example, there may be any desired number of layers with encapsulated components, depending on the desired circuit requirements. The resin flow during controlled pressure in a multilayer press is determined by the temperature, and the prepreg resin in each layer will flow as the temperature exceeds the point it starts to flow at, from near hot plates first, to the centre. Multilayer presses in general are controlled to continuously keep pressure and temperatures within preset intervals, adjusting for both expansion and contraction.

Components may also be glued when required, for instance if the melting point of the solder is below or too close to the pressing temperature.

Also, there may be none or only one external layer with conductors, again depending on the circuit requirements. If there are no external layers, external electrical connections from the conductors can be provided by insulated terminals attached after completion, induction coils or even thermal pads for power or energy harvesting and wireless signal transmission, depending on the application. In another embodiment, the test points are in the paths of the PTH drilling, but in or near the centres of the vias so that they are fully drilled out.

In summary, the method uses solder to bond and electrically connect components and solder mask and prepreg to protect and bond multilayer PCB together.

In various embodiments there may be multiple embedded component layers, provided by repeating the prepreg layer placement steps. When embedding multiple component layers, all layers and component layers can be prepared separately and combined in one single pressing or already pressed embedded layers can be pressed again, regarded as cores and pressed together as if just cores, or populated again before pressed again, repeatedly, according to the invention. The thermal expansion of the thermal set resins involved is combined with softening at elevated process temperatures which provides robustness of the proposed process. PCBs with buried embedded components inside can be re-embedded as already stated just above, but also sold as ready-made, and tested, cores or parts/modules that can be combined into standard multilayer PCBs for special functions or together be interleaved with cooling plates and pressed together for very high package densities and effective cooling.

Claims

1. A method of manufacturing a multi-layer circuit, comprising:

(a) providing a first layer with an insulating substrate (11) and conductors (12, 14),

(b) applying a solder mask (30) to the first layer, in which the mask leaves one or more component pads (19, 20) exposed,

(c) depositing solder paste (42) on said one or more component pads,

(d) placing one or more SMT components (40) on said solder paste,

(e) heating to reflow the solder paste (40), and cooling to cure the paste to provide solder which secures the components (40) in place,

(f) placing over the first layer one or more solid uncured resin layers (50) with clearances (60) for the components (40), wherein said resin layer and said solder mask are of a compatible composition for bonding under application of heat,

(g) pressing to cause flow of resin (53) from the one or more resin layer (60) around the components (40) to encapsulate the components and bond the resin (53) to the solder mask (30), wherein the solder mask is of a type of material to both prevent oxidation of the first layer conductors and to also bond with the resin (53) during and after resin flow, and

(h) making electrical connections between external conductors (71, 72, 12) and said conductors (14) on the first layer to provide electrical paths from the external conductors and said component pads (19, 20),

2. A method as claimed in claim 1 wherein the duration of solder reflow of step (e) is in the range of 2 to 30 seconds, so that the solder mask (30) retains its cross-linking ability after solder reflow.

3. A method as claimed in claims 1 or 2, wherein the steps (c) to (e) are performed at a temperature not exceeding a maximum temperature, for example l50°C.

4. A method as claimed in any preceding claim, wherein the solder mask (30) is of an epoxy material and said resin (53) of step (f) comprises a compatible epoxy.

5. A method as claimed in any preceding claim, wherein the solder mask (30) comprises UV imageable and bondable solder mask.

6. A method as claimed in any preceding claim, wherein the first layer of step (a) comprises tracks (15, 16, 17, 18) and component pads (19, 20).

7. A method as claimed in claim 6, wherein the first layer of step (a) comprises pads (25) for subsequent vertical connectivity to the tracks.

8. A method as claimed in any preceding claim, wherein the solder paste (42) of step (c) has a melting point higher than a temperature of the subsequent encapsulation press temperature in step (g).

9. A method as claimed in any preceding claim, wherein the solder reflow temperature of step (e) is in the range of l85°C to 250°C.

10. A method as claimed in any preceding claim, wherein an adhesive is used to additionally secure the components in place.

11. A method as claimed in any preceding claim, comprising the further step of anti oxidation treatment after solder masking, so that conductors (35, 36, 37, 38) which are not covered by the solder mask (30) are protected from oxidation, and in which pads (25) on the first layer for vertical connectivity are masked.

12. A method as claimed in claim 11, wherein the anti-oxidation treatment is by immersion.

13. A method as claimed in any preceding claim, comprising the further step of in-circuit testing after component placement.

14. A method as claimed in any preceding claim, wherein step (b) includes the mask (30) leaving gaps (35, 36, 37, and 38) on the tracks for in-circuit testing contact pins.

15. A method as claimed in claim 14, wherein the conductors on the first layer include connectivity pads (25) for said vertical connectivity, and said pads are covered by the mask (30), and wherein said in-circuit testing gaps (35, 36, 37, and 38) are spaced apart from said connectivity pads (25), and wherein the in-circuit testing gaps are protected from oxidation by a treatment used to protect the solder pads, by immersion in an anti oxidation solution.

16. A method as claimed in any preceding claim, wherein the pressing step (g) is performed at a temperature lower than the solder melting point, to prevent component displacement during pressing.

17. A method as claimed in any preceding claim, wherein the step (g) encapsulation is performed at a temperature at least l0°C lower than melting point of the solder (42).

18. A method as claimed in any preceding claim, wherein the resin layers (50) comprise woven glass weave impregnated with resin.

19. A method as claimed in any of any preceding claim, wherein the step (h) comprises drilling avia and lining (75, 76) the via to provide plated through holes (77, 78) for vertical connectivity between the first layer conductors (71, 72, 12) and any other layer or layers (14).

20. A method as claimed in claim 19, wherein the conductors on the first layer include connectivity pads (25) for said vertical connectivity by provision of plated through holes (76, 77) through said pads.

21. A method as claimed in any preceding claim, comprising steps of providing at least one external layer (55, 71, 72) having conductors, and said step (h) provides electrical connections between the conductors of said external layer to said conductors in the first layer.

22. A method as claimed in claim 21, wherein top and bottom external layers (71, 72, 12) with conductors are provided, and connections are made from said conductors of both said external layers to said first layer (12) and/or to an additional layer (14) between said external layers.

23. A method as claimed in any preceding claim, wherein the solder (42) reflow temperature is in the range of l85°C to 250°C, and said resin flow temperature is at least 5°C lower than the solder reflow temperature.

24. A method as claimed in any preceding claim, comprising the further steps of repeating steps (a) to (g) for each of a plurality of layers to provide second and optionally subsequent layers with encapsulated components, or providing subsequent layers with components and performing resin flow simultaneously for some or all internal layers.

25. A method as claimed in any preceding claim, wherein components are placed on only one side of an insulating substrate, both sides of said substrate are solder masked to achieve oxidation protection and bondability of both sides to said resin and to avoid exposure of components and solder joints to oxide treatment chemicals that may deteriorate both components and solder

26. A multi-layer circuit manufactured by a method including the steps of a method of any preceding claim.

27. A multi-layer circuit comprising a substrate having an internal surface, solder mask on part of said substrate surface, encapsulated components placed on solder in electrical connection with conductors on the substrate, wherein the components are encapsulated in resin which bonds with the solder mask.

28. A circuit as claimed in claim 27, comprising an external conductor, and said external conductor is connected to said substrate conductors by plated through holes.

29. A circuit as claimed in any of claims 26 to 28, wherein the circuit comprises an interposer and said components include resistors for electrical terminations for a device.

30. A device comprising a circuit as claimed in any of claims 26 to 29.