JP2006339421A - 配線基板および配線基板の製造方法 - Google Patents
配線基板および配線基板の製造方法 Download PDFInfo
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- JP2006339421A JP2006339421A JP2005162547A JP2005162547A JP2006339421A JP 2006339421 A JP2006339421 A JP 2006339421A JP 2005162547 A JP2005162547 A JP 2005162547A JP 2005162547 A JP2005162547 A JP 2005162547A JP 2006339421 A JP2006339421 A JP 2006339421A
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- wiring board
- layer
- wiring
- insulating layer
- semiconductor chip
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- 238000004519 manufacturing process Methods 0.000 title claims description 54
- 238000000034 method Methods 0.000 title claims description 43
- 230000003014 reinforcing effect Effects 0.000 claims abstract description 78
- 239000004065 semiconductor Substances 0.000 claims abstract description 76
- 239000000463 material Substances 0.000 claims description 24
- 239000000758 substrate Substances 0.000 claims description 24
- 230000017525 heat dissipation Effects 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 230000002787 reinforcement Effects 0.000 claims description 10
- 239000010410 layer Substances 0.000 description 186
- 238000010586 diagram Methods 0.000 description 29
- 229910000679 solder Inorganic materials 0.000 description 19
- 238000009713 electroplating Methods 0.000 description 8
- 229920005989 resin Polymers 0.000 description 7
- 239000011347 resin Substances 0.000 description 7
- 238000004381 surface treatment Methods 0.000 description 7
- 229920001187 thermosetting polymer Polymers 0.000 description 7
- 238000007772 electroless plating Methods 0.000 description 5
- 239000003822 epoxy resin Substances 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 230000020169 heat generation Effects 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 5
- 229920000647 polyepoxide Polymers 0.000 description 5
- 239000011162 core material Substances 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- -1 for example Substances 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
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- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
- H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49126—Assembling bases
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49128—Assembling formed circuit to base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
Abstract
【解決手段】 半導体チップを内蔵した配線基板であって、前記半導体チップが埋設された絶縁層と、前記半導体チップに接続される配線と、を有し、前記絶縁層の第1の側と、当該第1の側と反対側の第2の側とに、それぞれ当該絶縁層を補強する補強層が形成されていることを特徴とする配線基板。
【選択図】 図1
Description
101 支持基板
102,118 電極
103,114,121 補強層
105,108,113,116 配線部
105a,108a,113a,116a ビアプラグ
105b,108b,113b,116b パターン配線
106 絶縁層
110 半導体チップ
109 はんだ接続部
111 スタッドバンプ
117,119 ソルダーレジスト層
120 はんだボール
Claims (11)
- 半導体チップを内蔵した配線基板であって、
前記半導体チップが埋設された絶縁層と、
前記半導体チップに接続される配線と、
前記絶縁層の第1の側と、当該第1の側と反対側の第2の側とにそれぞれ形成された、当該絶縁層を補強する補強層と、を有することを特徴とする配線基板。 - 前記補強層はプリプレグ材よりなることを特徴とする請求項1記載の配線基板。
- 前記補強層のうち、前記第1の側に形成された補強層には開口部が形成され、当該開口部には、前記配線に接続される電極が形成されていることを特徴とする請求項1または2記載の配線基板。
- 前記補強層のうち、前記第2の側に形成された補強層上には、前記配線に接続される電極が形成されていることを特徴とする請求項1乃至3のうち、いずれか1項記載の配線基板。
- 前記絶縁層を補強する別の補強層が、前記絶縁層に埋設されていることを特徴とする請求項1乃至4のうち、いずれか1項記載の配線基板。
- 前記半導体チップの放熱を行う放熱手段がさらに形成されていることを特徴とする請求項1乃至5のうち、いずれか1項記載の配線基板。
- 前記放熱手段は、前記半導体チップ上に形成された金属層と、当該金属層に接続された放熱ビアプラグとを含むことを特徴とする請求項6記載の配線基板。
- 半導体チップが埋設された絶縁層を有する配線基板の製造方法であって、
支持基板上に、前記絶縁層を補強する第1の補強層を形成する第1の工程と、
前記第1の補強層上に、前記半導体チップが埋設された前記絶縁層と、前記半導体チップに接続される配線とを形成する第2の工程と、
前記絶縁層上に前記絶縁層を補強する第2の補強層を形成する第3の工程と、
前記支持基板を除去する第4の工程と、を有することを特徴とする配線基板の製造方法。 - 前記絶縁層に埋設される、前記絶縁層を補強する第3の補強層を形成する工程をさらに有することを特徴とする請求項8記載の配線基板の製造方法。
- 前記半導体チップ上に、当該半導体チップの放熱を行う放熱手段を形成する工程をさらに有することを特徴とする請求項8または9記載の配線基板の製造方法。
- 前記第1の補強層は、前記第2の補強層より厚く形成されることを特徴とする請求項8乃至10のうち、いずれか1項記載の配線基板の製造方法。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
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JP2005162547A JP4016039B2 (ja) | 2005-06-02 | 2005-06-02 | 配線基板および配線基板の製造方法 |
KR1020060045339A KR101160528B1 (ko) | 2005-06-02 | 2006-05-19 | 배선 기판 및 그 제조 방법 |
TW095119359A TWI408780B (zh) | 2005-06-02 | 2006-06-01 | 佈線板及其製造方法 |
US11/421,607 US7732712B2 (en) | 2005-06-02 | 2006-06-01 | Wiring board and method for manufacturing the same |
EP06011507.8A EP1740025B1 (en) | 2005-06-02 | 2006-06-02 | Wiring board and method for manufacturing the same |
CN2006100833472A CN1882224B (zh) | 2005-06-02 | 2006-06-02 | 配线基板及其制造方法 |
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JP2005162547A JP4016039B2 (ja) | 2005-06-02 | 2005-06-02 | 配線基板および配線基板の製造方法 |
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JP2006339421A true JP2006339421A (ja) | 2006-12-14 |
JP4016039B2 JP4016039B2 (ja) | 2007-12-05 |
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US (1) | US7732712B2 (ja) |
EP (1) | EP1740025B1 (ja) |
JP (1) | JP4016039B2 (ja) |
KR (1) | KR101160528B1 (ja) |
CN (1) | CN1882224B (ja) |
TW (1) | TWI408780B (ja) |
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2006
- 2006-05-19 KR KR1020060045339A patent/KR101160528B1/ko active IP Right Grant
- 2006-06-01 US US11/421,607 patent/US7732712B2/en not_active Expired - Fee Related
- 2006-06-01 TW TW095119359A patent/TWI408780B/zh not_active IP Right Cessation
- 2006-06-02 EP EP06011507.8A patent/EP1740025B1/en not_active Expired - Fee Related
- 2006-06-02 CN CN2006100833472A patent/CN1882224B/zh not_active Expired - Fee Related
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JP2009224739A (ja) * | 2008-03-19 | 2009-10-01 | Shinko Electric Ind Co Ltd | 多層配線基板およびその製造方法 |
JP2013236105A (ja) * | 2008-07-23 | 2013-11-21 | Nec Corp | コアレス配線基板、半導体装置及びそれらの製造方法 |
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JPWO2010101167A1 (ja) * | 2009-03-05 | 2012-09-10 | 日本電気株式会社 | 半導体装置及びその製造方法 |
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KR20160024802A (ko) * | 2014-08-25 | 2016-03-07 | 신꼬오덴기 고교 가부시키가이샤 | 전자 부품 장치 및 그 제조 방법 |
KR102331611B1 (ko) * | 2014-08-25 | 2021-11-30 | 신꼬오덴기 고교 가부시키가이샤 | 전자 부품 장치 및 그 제조 방법 |
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US11189552B2 (en) | 2017-11-01 | 2021-11-30 | Samsung Electronics Co., Ltd. | Semiconductor package |
Also Published As
Publication number | Publication date |
---|---|
US20060272854A1 (en) | 2006-12-07 |
JP4016039B2 (ja) | 2007-12-05 |
CN1882224A (zh) | 2006-12-20 |
TW200703591A (en) | 2007-01-16 |
CN1882224B (zh) | 2010-12-29 |
US7732712B2 (en) | 2010-06-08 |
KR101160528B1 (ko) | 2012-06-28 |
KR20060125472A (ko) | 2006-12-06 |
TWI408780B (zh) | 2013-09-11 |
EP1740025B1 (en) | 2018-08-29 |
EP1740025A2 (en) | 2007-01-03 |
EP1740025A3 (en) | 2009-04-08 |
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