JP2010287742A - 配線基板の製造方法 - Google Patents
配線基板の製造方法 Download PDFInfo
- Publication number
- JP2010287742A JP2010287742A JP2009140529A JP2009140529A JP2010287742A JP 2010287742 A JP2010287742 A JP 2010287742A JP 2009140529 A JP2009140529 A JP 2009140529A JP 2009140529 A JP2009140529 A JP 2009140529A JP 2010287742 A JP2010287742 A JP 2010287742A
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- Prior art keywords
- plating film
- film
- support plate
- plating
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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- 239000000758 substrate Substances 0.000 title abstract description 79
- 239000000463 material Substances 0.000 claims abstract description 116
- 238000007747 plating Methods 0.000 claims description 523
- 238000000034 method Methods 0.000 claims description 59
- 238000009713 electroplating Methods 0.000 claims description 37
- 229910052737 gold Inorganic materials 0.000 claims description 11
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- 239000010410 layer Substances 0.000 abstract description 401
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- KDLHZDBZIXYQEI-UHFFFAOYSA-N palladium Substances [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 14
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 13
- 239000011888 foil Substances 0.000 description 13
- 229910017604 nitric acid Inorganic materials 0.000 description 13
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- 239000002356 single layer Substances 0.000 description 8
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- 238000007254 oxidation reaction Methods 0.000 description 4
- 239000000654 additive Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
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- 239000011889 copper foil Substances 0.000 description 3
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- 238000001312 dry etching Methods 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000010329 laser etching Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 239000003755 preservative agent Substances 0.000 description 2
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- 229910020816 Sn Pb Inorganic materials 0.000 description 1
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- 238000005260 corrosion Methods 0.000 description 1
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Abstract
【解決手段】層間絶縁層14から露出する電極パッド4a、6aを有する配線基板20Jであって、電極パッド4a、6aはそれぞれ層間絶縁層14の表面と同一面で露出し、電極パッド毎に露出面の材質が異なっている。配線基板20Jには、半導体チップ21およびリッド23が搭載され、半導体チップ21の主面に形成されている外部接続端子22と、電極パッド4aとが電気的に接続され、リッド23に形成されている接続部23bと、電極パッド6aとが電気的に接続され、半導体チップ21の裏面にリッド23が接着して配置される。
【選択図】図11
Description
また、本発明における配線基板は、半導体パッケージ、インターポーザ、実装基板等に適用することができ、特に、半導体パッケージに適用することが好適である。以下の実施形態では、半導体パッケージとして配線基板を用いた場合について説明する。
本実施形態における半導体パッケージの製造方法について図面を参照して説明する。まず、図1に示すように、支持板1上に、支持板1と材質が異なり、導電性を有する給電層7を形成する。支持板1は、例えば、500μm程度の厚さのCu(銅)箔である。給電層7は、例えば、めっき法によって形成した1〜5μm程度の厚さのNi(ニッケル)めっき膜である。なお、支持板1として、Cu箔の他に各種金属箔を使用することができる。
前記実施形態1では、電極パッド毎に露出面の材質を異ならせるために、図10に示したように、領域Aにおいて半導体チップ21と接続される電極パッド4aの表面にCuめっき膜を露出し、領域Bにおいてリッド23と接続される電極パッド6aの表面にAuめっき膜を露出する場合について説明した。本実施形態では、図17に示すように、領域Aにおいて半導体チップ21と接続される電極パッド6aの表面にAuめっき膜を露出し、領域Bにおいてリッド23と接続される電極パッド4aの表面にCuめっき膜を露出する場合について説明する。なお、前記実施形態と重複する説明は省略する場合がある。
なお、前記実施形態1の変形例(図12参照)と同様に、支持板1と電極パッド4a、6aのめっき膜の材質を異ならせることは、本実施形態にも適用することができる。すなわち、導電性の支持板1としてNi箔を用いた場合には、給電層7を形成せずに配線基板20Kを形成することができる。
前記実施形態1では、電極パッド毎に露出面の材質を異ならせた配線基板20Jとして、図10に示したように、領域Aにおいて半導体チップ21と接続される電極パッド4aとしてCuめっき膜を露出し、領域Bにおいてリッド23と接続される電極パッド6aとしてAuめっき膜を露出する場合について説明した。本実施形態では、図27に示すように、配線基板20Aの中央部の領域Aでは、電極パッド4aの露出面が層間絶縁層14に形成された凹部18の底面と同一面とし、配線基板20Aの外周部の領域Bでは、電極パッド6aの露出面が層間絶縁層14の表面と同一面としている場合について説明する。なお、前記実施形態と重複する説明は省略する場合がある。
前記実施形態3では、図27に示したように、配線基板20Aの外周部の領域Bでは、電極パッド6aの露出面が層間絶縁層14の表面と同一面となっている場合を示した。本実施形態では、図34に示すように、配線基板20Bの外周部の領域Bでは、電極パッド6aの露出面が層間絶縁層14に形成された凹部42の底面と同一面となっている場合について説明する。なお、前記実施形態と重複する説明は省略する場合がある。
前記実施形態3では、図27に示したように、配線基板20Aの中央部の領域Aでは、電極パッド4aの露出面が層間絶縁層14に形成された凹部18の底面と同一面となっており、配線基板20Aの外周部の領域Bでは、電極パッド6aの露出面が層間絶縁層14の表面と同一面となっている場合を示した。本実施形態では、図40に示すように、配線基板20Cの外周部の領域Bでは、電極パッド4aの露出面が層間絶縁層14に形成された凹部18の底面と同一面となっており、配線基板20Cの中央部の領域Aでは、電極パッド6aの露出面が層間絶縁層14の表面と同一面となっている場合について説明する。なお、前記実施形態と重複する説明は省略する場合がある。
前記実施形態3では、図27に示したように、配線基板20Aの中央部の領域Aでは、電極パッド4aの露出面が層間絶縁層14に形成された凹部18の底面と同一面となっており、配線基板20Aの外周部の領域Bでは、電極パッド6aの露出面が層間絶縁層14の表面と同一面となっている場合を示した。本実施形態では、図46に示すように、配線基板20Dの外周部の領域Bでは、電極パッド4aの露出面が層間絶縁層14に形成された凹部18の底面と同一面となっており、配線基板20Dの中央部の領域Aでは、電極パッド6aの露出面が層間絶縁層14に形成された凹部42の底面と同一面となっている場合について説明する。なお、前記実施形態と重複する説明は省略する場合がある。
前記実施形態3では、図27に示したように、配線基板20Aの中央部の領域Aでは、電極パッド4aの露出面が層間絶縁層14に形成された凹部18の底面と同一面となっており、配線基板20Aの外周部の領域Bでは、電極パッド6aの露出面が層間絶縁層14の表面と同一面となっている場合を示した。本実施形態では、図52に示すように、配線基板20Eの外周部の領域Bでは、電極パッド6aの露出面が層間絶縁層14に形成された凹部54の底面と同一面となっており、配線基板20Eの中央部の領域Aでは、電極パッド4aの露出面が層間絶縁層14の表面と同一面となっている場合について説明する。なお、前記実施形態と重複する説明は省略する場合がある。
前記実施形態3では、図27に示したように、配線基板20Aの中央部の領域Aでは、電極パッド4aの露出面が層間絶縁層14に形成された凹部18の底面と同一面となっており、配線基板20Aの外周部の領域Bでは、電極パッド6aの露出面が層間絶縁層14の表面と同一面となっている場合を示した。本実施形態では、図58に示すように、配線基板20Fの中央部の領域Aでは、電極パッド6aの露出面が層間絶縁層14に形成された凹部54の底面と同一面となっており、配線基板20Fの外周部の領域Bでは、電極パッド4aの露出面が層間絶縁層14の表面と同一面となっている場合について説明する。なお、前記実施形態と重複する説明は省略する場合がある。
前記実施形態3では、図29に示したように、電極パッド4a、6aが形成されている面側の配線基板20A上に種々の部品(半導体チップ21、リッド23)を搭載した場合について説明した。本実施形態では、図60に示すように、電極4a、6aが形成されている面側の配線基板20G上に種々の部品(チップキャパシタ61、はんだボール62)を搭載し、その反対面の配線基板20G上に半導体チップ64を搭載する場合について説明する。なお、前記実施形態と重複する説明は省略する場合がある。
前記実施形態3では、図29に示したように、電極パッド4a、6aが形成されている面側の配線基板20A上に半導体チップ21、リッド23を搭載した場合について説明した。本実施形態では、別の部品(チップキャパシタ)を搭載する場合について説明する。なお、前記実施形態と重複する説明は省略する場合がある。
図62に示す配線基板20Iは、前記実施形態5で図36〜図40を参照して説明した製造工程を用いて形成することができる。これらの製造工程を経て配線基板20Iの電極パッド4aおよび電極パッド6aは、表面絶縁層14の表面からの深さが互いに異なって露出することになる。この配線基板20Iの電極パッド6aと、半導体チップ21の外部接続端子22とが電気的に接続されて配線基板20I上に半導体チップ21が搭載される。また、配線基板20Iの電極パッド4aと、POP(Package On Package)基板71の外部接続端子80とが電気的に接続されて配線基板20I上にPOP基板71が搭載される。
2 レジスト層
2a 開口部
3 深さ調整膜
4 めっき膜
4a 電極パッド
5 レジスト層
5a 開口部
6 めっき膜
6a 電極パッド
6e Auめっき膜
6f Niめっき膜
6g Cuめっき膜
11、12、13 配線
14、15、16 層間絶縁層
17 ソルダレジスト
18 凹部
20A〜20K 配線基板
21 半導体チップ
22 外部接続端子
23 リッド
23a 蓋部
23b 接続部
24 グリス
25 はんだ
30A〜30K 半導体パッケージ
41 深さ調整膜
42 凹部
51 支持板
52 給電層
53 深さ調整膜
54 凹部
61 チップキャパシタ
62 はんだボール
63 外部接続端子
64 半導体チップ
65 外部接続端子
66 はんだ
71 POP基板
72 コア基板
73、74 配線
75 スルーホール
76、77 ソルダレジスト
78 チップ
79、80 外部接続端子
101 配線基板
102 電極パッド
103 絶縁層
104 凹部
105 配線層
106 ソルダレジスト
107 ビア
Claims (13)
- 以下の工程を含むことを特徴とする配線基板の製造方法:
(a)支持板上に開口部を有する第1レジスト層を形成し、電解めっき法により、前記第1レジスト層の開口部の支持板上に第1めっき膜を形成し、次いで、前記第1レジスト層を除去する工程;
(b)前記支持板上に開口部を有する第2レジスト層を形成し、電解めっき法により、前記第2レジスト層の開口部の支持板上に第2めっき膜を形成し、次いで、前記第2レジスト層を除去する工程;
(c)前記(a)、(b)工程後に、前記第1および第2めっき膜と電気的に接続された配線層と絶縁層とを積層し、配線基板本体を形成する工程;
(d)前記(c)工程後に、前記支持板を除去し、前記配線基板本体の支持板除去面に前記第1および第2めっき膜を露出する工程。 - 請求項1記載の配線基板の製造方法において、
前記第1めっき膜と前記第2めっき膜が、異なる材質からなることを特徴とする配線基板の製造方法。 - 請求項1記載の配線基板の製造方法において、
前記支持板はNiからなり、
前記第1めっき膜はCuからなり、
前記第2めっき膜はAu/Pd/Ni/CuまたはAu/Ni/Cuからなることを特徴とする配線基板の製造方法。 - 請求項1記載の配線基板の製造方法において、
前記支持板上には給電層が形成されており、
前記(a)工程および前記(b)工程の電解めっき法では、前記給電層をめっき給電部として用いることを特徴とする配線基板の製造方法。 - 請求項4記載の配線基板の製造方法において、
前記支持板はCuからなり、
前記給電層はNiからなり、
前記第1めっき膜はCuからなり、
前記第2めっき膜はAu/Pd/Ni/CuまたはAu/Ni/Cuからなることを特徴とする配線基板の製造方法。 - 請求項4記載の配線基板の製造方法において、
前記(a)工程または前記(b)工程では、前記支持板と前記第1または第2めっき膜との間に深さ調整膜を形成し、
前記(d)工程では、前記支持板を除去した後、前記深さ調整膜を除去することを特徴とする配線基板の製造方法。 - 請求項6記載の配線基板の製造方法において、
前記支持板はCuからなり、
前記給電層はNiからなり、
前記第1めっき膜はCuからなり、
前記深さ調整膜はNiからなり、
前記深さ調整膜上の前記第2めっき膜はAu/Pd/Ni/CuまたはAu/Ni/Cuからなることを特徴とする配線基板の製造方法。 - 請求項1記載の配線基板の製造方法において、
前記(a)工程または前記(b)工程では、前記支持板と前記第1または第2めっき膜との間に深さ調整膜を形成し、
前記(d)工程では、前記支持板を除去した後、前記深さ調整膜を除去することを特徴とする配線基板の製造方法。 - 請求項8記載の配線基板の製造方法において、
前記支持板はCuからなり、
前記深さ調整膜はNiからなり、
前記深さ調整膜上の前記第1めっき膜はCuからなり、
前記第2めっき膜はAu/Pd/Ni/CuまたはAu/Ni/Cuからなることを特徴とする配線基板の製造方法。 - 請求項8記載の配線基板の製造方法において、
前記支持板はNiからなり、
前記深さ調整膜はNiからなり、
前記第1めっき膜はCuからなり、
前記深さ調整膜上の前記第2めっき膜はAu/Pd/Ni/CuまたはAu/Ni/Cuからなることを特徴とする配線基板の製造方法。 - 請求項1記載の配線基板の製造方法において、
前記(a)工程では、前記支持板と前記第1めっき膜との間に第1深さ調整膜を形成し、
前記(b)工程では、前記支持板と前記第2めっき膜との間に第2深さ調整膜を形成し、
前記(d)工程では、前記支持板および前記第2深さ調整膜を除去した後、前記第1深さ調整膜を除去することを特徴とする配線基板の製造方法。 - 請求項11記載の配線基板の製造方法において、
前記支持板はCuからなり、
前記第1深さ調整膜はNiからなり、
前記第1深さ調整膜上の前記第1めっき膜はCuからなり、
前記第2深さ調整膜はCuからなり、
前記第2深さ調整膜上の前記第2めっき膜はAu/Pd/Ni/CuまたはAu/Ni/Cuからなることを特徴とする配線基板の製造方法。 - 前記請求項1〜12のいずれか一項に記載の配線基板の製造方法において、
前記(d)工程後に、前記第1および前記第2めっき膜のそれぞれには異なる部品が電気的に接続されることを特徴とする配線基板の製造方法。
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8872326B2 (en) | 2012-08-29 | 2014-10-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Three dimensional (3D) fan-out packaging mechanisms |
JP2019201121A (ja) * | 2018-05-17 | 2019-11-21 | エイブリック株式会社 | プリモールド基板とその製造方法および中空型半導体装置とその製造方法 |
WO2023210815A1 (ja) * | 2022-04-28 | 2023-11-02 | 凸版印刷株式会社 | 配線基板、半導体装置及び配線基板の製造方法 |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8987896B2 (en) * | 2009-12-16 | 2015-03-24 | Intel Corporation | High-density inter-package connections for ultra-thin package-on-package structures, and processes of forming same |
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KR101706470B1 (ko) * | 2015-09-08 | 2017-02-14 | 앰코 테크놀로지 코리아 주식회사 | 표면 마감층을 갖는 반도체 디바이스 및 그 제조 방법 |
US10204889B2 (en) * | 2016-11-28 | 2019-02-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package structure and method of forming thereof |
US10314171B1 (en) * | 2017-12-29 | 2019-06-04 | Intel Corporation | Package assembly with hermetic cavity |
CN111405774B (zh) * | 2020-03-18 | 2021-05-28 | 盐城维信电子有限公司 | 一种线路板及其制造方法 |
US20220069489A1 (en) * | 2020-08-28 | 2022-03-03 | Unimicron Technology Corp. | Circuit board structure and manufacturing method thereof |
KR20220033636A (ko) | 2020-09-09 | 2022-03-17 | 삼성전자주식회사 | 반도체 패키지 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007214534A (ja) * | 2006-02-09 | 2007-08-23 | Phoenix Precision Technology Corp | 導電構造を具備する回路基板の製造方法 |
JP2008270346A (ja) * | 2007-04-17 | 2008-11-06 | Shinko Electric Ind Co Ltd | 配線基板の製造方法及び半導体装置の製造方法及び配線基板 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3635219B2 (ja) * | 1999-03-11 | 2005-04-06 | 新光電気工業株式会社 | 半導体装置用多層基板及びその製造方法 |
JP3546961B2 (ja) | 2000-10-18 | 2004-07-28 | 日本電気株式会社 | 半導体装置搭載用配線基板およびその製造方法、並びに半導体パッケージ |
US7501328B2 (en) * | 2003-05-07 | 2009-03-10 | Microfabrica Inc. | Methods for electrochemically fabricating structures using adhered masks, incorporating dielectric sheets, and/or seed layers that are partially removed via planarization |
JP2005235982A (ja) | 2004-02-19 | 2005-09-02 | Dainippon Printing Co Ltd | 配線基板の製造方法と配線基板、および半導体パッケージ |
JP4108643B2 (ja) | 2004-05-12 | 2008-06-25 | 日本電気株式会社 | 配線基板及びそれを用いた半導体パッケージ |
JP4146864B2 (ja) | 2005-05-31 | 2008-09-10 | 新光電気工業株式会社 | 配線基板及びその製造方法、並びに半導体装置及び半導体装置の製造方法 |
KR100892935B1 (ko) * | 2005-12-14 | 2009-04-09 | 신꼬오덴기 고교 가부시키가이샤 | 칩 내장 기판 및 칩 내장 기판의 제조방법 |
CN101507373A (zh) * | 2006-06-30 | 2009-08-12 | 日本电气株式会社 | 布线板、使用布线板的半导体器件、及其制造方法 |
JP5091469B2 (ja) * | 2006-12-05 | 2012-12-05 | 京セラSlcテクノロジー株式会社 | 配線基板およびその製造方法 |
KR20090022877A (ko) * | 2007-08-31 | 2009-03-04 | 주식회사 탑 엔지니어링 | 박막 금속 전도선의 제조 방법 |
KR100896810B1 (ko) * | 2007-10-16 | 2009-05-11 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조방법 |
US8461036B2 (en) * | 2009-12-22 | 2013-06-11 | Intel Corporation | Multiple surface finishes for microelectronic package substrates |
-
2009
- 2009-06-11 JP JP2009140529A patent/JP5231340B2/ja active Active
-
2010
- 2010-06-10 US US12/797,905 patent/US8790504B2/en active Active
- 2010-06-11 KR KR1020100055592A patent/KR101985020B1/ko active IP Right Grant
- 2010-06-11 TW TW099119062A patent/TWI523591B/zh active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007214534A (ja) * | 2006-02-09 | 2007-08-23 | Phoenix Precision Technology Corp | 導電構造を具備する回路基板の製造方法 |
JP2008270346A (ja) * | 2007-04-17 | 2008-11-06 | Shinko Electric Ind Co Ltd | 配線基板の製造方法及び半導体装置の製造方法及び配線基板 |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8872326B2 (en) | 2012-08-29 | 2014-10-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Three dimensional (3D) fan-out packaging mechanisms |
US9431367B2 (en) | 2012-08-29 | 2016-08-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming a semiconductor package |
KR101752592B1 (ko) * | 2012-08-29 | 2017-06-29 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | 3차원 팬 아웃 패키징 메커니즘 |
US9960125B2 (en) | 2012-08-29 | 2018-05-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming a semiconductor package |
US10276516B2 (en) | 2012-08-29 | 2019-04-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor package |
US10672723B2 (en) | 2012-08-29 | 2020-06-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor package |
US11362046B2 (en) | 2012-08-29 | 2022-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package |
JP2019201121A (ja) * | 2018-05-17 | 2019-11-21 | エイブリック株式会社 | プリモールド基板とその製造方法および中空型半導体装置とその製造方法 |
JP7063718B2 (ja) | 2018-05-17 | 2022-05-09 | エイブリック株式会社 | プリモールド基板とその製造方法および中空型半導体装置とその製造方法 |
WO2023210815A1 (ja) * | 2022-04-28 | 2023-11-02 | 凸版印刷株式会社 | 配線基板、半導体装置及び配線基板の製造方法 |
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US8790504B2 (en) | 2014-07-29 |
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US20100314254A1 (en) | 2010-12-16 |
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KR20100133317A (ko) | 2010-12-21 |
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