JP6504665B2 - 印刷回路基板、その製造方法、及び電子部品モジュール - Google Patents
印刷回路基板、その製造方法、及び電子部品モジュール Download PDFInfo
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- H—ELECTRICITY
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties
- H05K3/4694—Partitioned multilayer circuits having adjacent regions with different properties, e.g. by adding or inserting locally circuit layers having a higher circuit density
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
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- H01L23/5385—Assembly of a plurality of insulating substrates
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16265—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/1701—Structure
- H01L2224/1703—Bump connectors having different sizes, e.g. different diameters, heights or widths
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/04—Assemblies of printed circuits
- H05K2201/048—Second PCB mounted on first PCB by inserting in window or holes of the first PCB
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10431—Details of mounted components
- H05K2201/10507—Involving several components
- H05K2201/10522—Adjacent components
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
Description
図1は、本発明の一実施例による印刷回路基板を例示する断面図である。
図6は本発明の一実施例による電子部品モジュールを例示する断面図であり、重複する構成に関する説明は省略する。
図8は、本発明の一実施例による電子部品モジュールの製造方法を示すフローチャートであり、図9〜図22は、本発明の一実施例による電子部品モジュールの製造方法を工程順に示す工程断面図である。
101 貫通部
115、125 第1のパッド
130 ビルドアップ絶縁層
139 ビルドアップ回路層
140、150、240 ソルダレジスト層
160 充填樹脂
170 ハンダボール
501、502、503 電子部品
10 連結基板
10A 微細回路構造体
11 コア絶縁層
12 金属層
15 ビア
42、52 第2のパッド
Claims (19)
- コア基板、前記コア基板上に形成される第1の回路パターン、及び前記コア基板及び前記第1の回路パターンを貫通する貫通部を有する回路基板と、
コア絶縁層及び前記コア絶縁層上に形成される第2の回路パターンを含む微細回路構造体を有し、前記回路基板の前記貫通部に収容される連結基板と、を含み、
前記コア絶縁層の厚さは、前記コア基板の厚さよりも厚い、印刷回路基板。 - 前記第1の回路パターンは、複数の回路層と前記複数の回路層の間に介在された絶縁層を含む、請求項1に記載の印刷回路基板。
- 前記第1の回路パターンは、電子部品を実装するための第1のパッドを含む、請求項1または2に記載の印刷回路基板。
- 前記微細回路構造体は、前記連結基板の一面又は両面に形成される、請求項1から3のいずれか一項に記載の印刷回路基板。
- 前記微細回路構造体は前記連結基板の両面に形成され、前記両面の微細回路構造体はビアを介して電気的に連結される、請求項1から4のいずれか一項に記載の印刷回路基板。
- 前記微細回路構造体は、複数の回路層と前記複数の回路層の間に介在された絶縁層を含む、請求項1から5のいずれか一項に記載の印刷回路基板。
- 前記絶縁層は感光性絶縁層である、請求項6に記載の印刷回路基板。
- 前記第2の回路パターンは、電子部品を連結するための信号線を含む、請求項1から7のいずれか一項に記載の印刷回路基板。
- 前記第2の回路パターンは、電子部品を実装するための第2のパッドを含む、請求項1から8のいずれか一項に記載の印刷回路基板。
- 前記第2の回路パターンは、前記第1の回路パターンより小さいピッチの微細パターンを含む、請求項1から9のいずれか一項に記載の印刷回路基板。
- 前記回路基板及び前記連結基板上に形成されたビルドアップ絶縁層とビルドアップ回路層を含むビルドアップ層をさらに含む、請求項1から10のいずれか一項に記載の印刷回路基板。
- 前記回路基板上に形成されたソルダレジスト層をさらに含む、請求項1から11のいずれか一項に記載の印刷回路基板。
- 前記連結基板と前記貫通部の間に形成される充填樹脂をさらに含む、請求項1から12のいずれか一項に記載の印刷回路基板。
- 前記充填樹脂はソルダレジストである、請求項13に記載の印刷回路基板。
- コア基板、前記コア基板上に形成される第1の回路パターン、及び前記コア基板及び前記第1の回路パターンを貫通する貫通部を有する回路基板と、コア絶縁層及び前記コア絶縁層上に形成される第2の回路パターンを含む微細回路構造体を有し、前記回路基板の前記貫通部に収容される連結基板と、を含む印刷回路基板と、
前記印刷回路基板の一面又は両面に搭載される電子部品と、を含み、
前記コア絶縁層の厚さは、前記コア基板の厚さよりも厚い、電子部品モジュール。 - 前記第2の回路パターンは、前記第1の回路パターンより小さいピッチの微細パターンを含む、請求項15に記載の電子部品モジュール。
- コア基板、前記コア基板上に形成される第1の回路パターン、及び前記コア基板及び前記第1の回路パターンを貫通する貫通部を有する回路基板を準備する段階と、
前記貫通部にコア絶縁層及び前記コア絶縁層上に形成される第2の回路パターンを含む微細回路構造体を有する連結基板を収容する段階と、を含み、
前記コア絶縁層の厚さは、前記コア基板の厚さよりも厚い、印刷回路基板の製造方法。 - 前記連結基板を前記貫通部に収容する段階の前に、
前記連結基板を準備する段階をさらに含み、
前記連結基板は、前記コア絶縁層の第1の側及び前記第1の側と対向する第2の側上に配置された回路パターン及び絶縁層、及び前記コア絶縁層の第1の側と第2の側を電気的に連結するビアを含む、請求項17に記載の印刷回路基板の製造方法。 - 前記印刷回路基板の一面又は両面に一つ以上の電子部品を実装する段階をさらに含む、請求項18に記載の印刷回路基板の製造方法。
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Application Number | Priority Date | Filing Date | Title |
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KR1020150048937A KR102163039B1 (ko) | 2015-04-07 | 2015-04-07 | 인쇄회로기판, 그 제조방법, 및 전자부품 모듈 |
KR10-2015-0048937 | 2015-04-07 |
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JP2016201529A JP2016201529A (ja) | 2016-12-01 |
JP6504665B2 true JP6504665B2 (ja) | 2019-04-24 |
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US (1) | US20160302308A1 (ja) |
JP (1) | JP6504665B2 (ja) |
KR (1) | KR102163039B1 (ja) |
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KR102381986B1 (ko) * | 2016-10-28 | 2022-03-31 | 삼성전기주식회사 | 감광성 절연필름 및 이를 포함하는 부품 |
KR20180070786A (ko) * | 2016-12-16 | 2018-06-27 | 삼성전자주식회사 | 반도체 패키지 |
KR101942742B1 (ko) * | 2017-10-26 | 2019-01-28 | 삼성전기 주식회사 | 팬-아웃 반도체 패키지 |
CN107864562A (zh) * | 2017-12-20 | 2018-03-30 | 惠州市串联电子科技有限公司 | 一种led线路板及其制作方法 |
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US11798865B2 (en) | 2019-03-04 | 2023-10-24 | Intel Corporation | Nested architectures for enhanced heterogeneous integration |
US11164818B2 (en) * | 2019-03-25 | 2021-11-02 | Intel Corporation | Inorganic-based embedded-die layers for modular semiconductive devices |
US11011496B2 (en) | 2019-09-06 | 2021-05-18 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages and methods of manufacturing the same |
US20220149005A1 (en) * | 2020-11-10 | 2022-05-12 | Qualcomm Incorporated | Package comprising a substrate and a high-density interconnect integrated device |
KR20230075176A (ko) * | 2021-11-22 | 2023-05-31 | 삼성전기주식회사 | 인쇄회로기판 |
CN116564923A (zh) * | 2022-01-28 | 2023-08-08 | 奥特斯奥地利科技与系统技术有限公司 | 包括基于半导体的部件的模块及其制造方法 |
CN117177433A (zh) * | 2022-05-26 | 2023-12-05 | 奥特斯奥地利科技与系统技术有限公司 | 封装件和制造封装件的方法 |
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DE3913966B4 (de) | 1988-04-28 | 2005-06-02 | Ibiden Co., Ltd., Ogaki | Klebstoffdispersion zum stromlosen Plattieren, sowie Verwendung zur Herstellung einer gedruckten Schaltung |
JP2003298232A (ja) * | 2002-04-02 | 2003-10-17 | Sony Corp | 多層配線基板の製造方法および多層配線基板 |
JP2004327645A (ja) | 2003-04-24 | 2004-11-18 | Fuji Electric Device Technology Co Ltd | プリント基板 |
JP2005039217A (ja) * | 2003-06-24 | 2005-02-10 | Ngk Spark Plug Co Ltd | 中間基板 |
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US7932471B2 (en) * | 2005-08-05 | 2011-04-26 | Ngk Spark Plug Co., Ltd. | Capacitor for incorporation in wiring board, wiring board, method of manufacturing wiring board, and ceramic chip for embedment |
KR20090053628A (ko) * | 2007-11-23 | 2009-05-27 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조방법 |
JPWO2009141928A1 (ja) * | 2008-05-19 | 2011-09-29 | イビデン株式会社 | プリント配線板及びその製造方法 |
JP5010737B2 (ja) * | 2008-05-23 | 2012-08-29 | イビデン株式会社 | プリント配線板 |
DE102008062516A1 (de) | 2008-12-16 | 2010-07-01 | Continental Automotive Gmbh | Leiterplatte mit aufgewachsener Metallschicht in einer biegbaren Zone |
US20110103030A1 (en) | 2009-11-02 | 2011-05-05 | International Business Machines Corporation | Packages and Methods for Mitigating Plating Stub Effects |
JP2011159855A (ja) * | 2010-02-02 | 2011-08-18 | Panasonic Corp | 局所多層回路基板、および局所多層回路基板の製造方法 |
CN102771200A (zh) * | 2010-02-22 | 2012-11-07 | 三洋电机株式会社 | 多层印刷电路板及其制造方法 |
US8654538B2 (en) * | 2010-03-30 | 2014-02-18 | Ibiden Co., Ltd. | Wiring board and method for manufacturing the same |
JP5566921B2 (ja) | 2011-01-17 | 2014-08-06 | 名東電産株式会社 | アルミニウムを導電パターンとしたプリント配線基板の製造方法 |
CN102504332A (zh) | 2011-11-02 | 2012-06-20 | 台光电子材料(昆山)有限公司 | 无机填充物及含该无机填充物的电学材料 |
KR101316105B1 (ko) * | 2012-02-07 | 2013-10-11 | 삼성전기주식회사 | 난연성 절연층을 포함하는 인쇄회로기판의 제조방법 |
JP2014049578A (ja) * | 2012-08-30 | 2014-03-17 | Ibiden Co Ltd | 配線板、及び、配線板の製造方法 |
KR20140081193A (ko) * | 2012-12-21 | 2014-07-01 | 삼성전기주식회사 | 고밀도 및 저밀도 기판 영역을 구비한 하이브리드 기판 및 그 제조방법 |
TWI461127B (zh) * | 2012-12-25 | 2014-11-11 | Univ Nat Taipei Technology | 電子裝置及其製法 |
US9351410B2 (en) * | 2014-03-07 | 2016-05-24 | Fujikura Ltd. | Electronic component built-in multi-layer wiring board and method of manufacturing the same |
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2015
- 2015-04-07 KR KR1020150048937A patent/KR102163039B1/ko active IP Right Grant
- 2015-09-30 US US14/871,065 patent/US20160302308A1/en not_active Abandoned
- 2015-11-26 JP JP2015230980A patent/JP6504665B2/ja active Active
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KR102163039B1 (ko) | 2020-10-08 |
US20160302308A1 (en) | 2016-10-13 |
KR20160120011A (ko) | 2016-10-17 |
JP2016201529A (ja) | 2016-12-01 |
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