JP2011142286A - 電子部品内蔵型プリント基板およびその製造方法 - Google Patents
電子部品内蔵型プリント基板およびその製造方法 Download PDFInfo
- Publication number
- JP2011142286A JP2011142286A JP2010107474A JP2010107474A JP2011142286A JP 2011142286 A JP2011142286 A JP 2011142286A JP 2010107474 A JP2010107474 A JP 2010107474A JP 2010107474 A JP2010107474 A JP 2010107474A JP 2011142286 A JP2011142286 A JP 2011142286A
- Authority
- JP
- Japan
- Prior art keywords
- electronic component
- metal substrate
- circuit board
- printed circuit
- built
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 121
- 229910052751 metal Inorganic materials 0.000 claims abstract description 112
- 239000002184 metal Substances 0.000 claims abstract description 112
- 239000010407 anodic oxide Substances 0.000 claims abstract description 18
- 239000010410 layer Substances 0.000 claims description 90
- 238000000034 method Methods 0.000 claims description 50
- 230000008569 process Effects 0.000 claims description 42
- 239000012790 adhesive layer Substances 0.000 claims description 25
- 229910052782 aluminium Inorganic materials 0.000 claims description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 11
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 9
- 230000003647 oxidation Effects 0.000 claims description 9
- 238000007254 oxidation reaction Methods 0.000 claims description 9
- 238000010030 laminating Methods 0.000 claims description 8
- 230000000149 penetrating effect Effects 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 4
- 238000009413 insulation Methods 0.000 abstract description 3
- 230000005855 radiation Effects 0.000 abstract 1
- 229910000679 solder Inorganic materials 0.000 description 11
- 239000011810 insulating material Substances 0.000 description 10
- 230000008901 benefit Effects 0.000 description 5
- 239000000654 additive Substances 0.000 description 4
- 239000011777 magnesium Substances 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 3
- 238000002048 anodisation reaction Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 239000000945 filler Substances 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 229910052749 magnesium Inorganic materials 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 230000002457 bidirectional effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 150000003071 polychlorinated biphenyls Chemical class 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/44—Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits
- H05K3/445—Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits having insulated holes or insulated via connections through the metal core
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01012—Magnesium [Mg]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09745—Recess in conductor, e.g. in pad or in metallic substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09772—Conductors directly under a component but not electrically connected to the component
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/01—Tools for processing; Objects used during processing
- H05K2203/0191—Using tape or non-metallic foil in a process, e.g. during filling of a hole with conductive paste
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0315—Oxidising metal
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4641—Manufacturing multilayer circuits by laminating two or more circuit boards having integrally laminated metal sheets or special power cores
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
【解決手段】本発明の電子部品内蔵型プリント基板100は、全面に陽極酸化膜120が形成された金属基板110、金属基板110に形成されたキャビティ130の内部に2段に配置された2つの電子部品140、金属基板110の両面に積層され、キャビティ130の内部に配置された電子部品140を埋め込ませる絶縁層150と、電子部品140の接続端子145に接続されるビア165を含み、絶縁層150の露出面に形成された回路層160とを含んでなる。
【選択図】図2
Description
110 金属基板
120 陽極酸化膜
130 キャビティ
140 電子部品
145 接続端子
150 絶縁層
160 回路層
165 ビア
170 支持板
175 開口部
180 接着層
190 スルーホール
191 支持テープ
193 半田レジスト層
195 ホール
Claims (17)
- 全面に陽極酸化膜が形成された金属基板と、
前記金属基板に形成されたキャビティの内部に2段に配置された2つの電子部品と、
前記金属基板の両面に積層され、前記キャビティの内部に配置された前記電子部品を埋め込ませる絶縁層と、
前記電子部品の接続端子に接続されるビアを含み、前記絶縁層の露出面に形成された回路層とを含んでなることを特徴とする電子部品内蔵型プリント基板。 - 前記キャビティの厚さ方向を分割するように前記キャビティの内部に形成され、両面が前記2つの電子部品をそれぞれ支持する支持板をさらに含むことを特徴とする請求項1に記載の電子部品内蔵型プリント基板。
- 前記支持板の両面に塗布され、前記2つの電子部品を固定する接着層をさらに含むことを特徴とする請求項2に記載の電子部品内蔵型プリント基板。
- 前記支持板を貫通する少なくとも一つの開口部をさらに含むことを特徴とする請求項2に記載の電子部品内蔵型プリント基板。
- 前記支持板が、前記金属基板から延長されて一体に形成されたことを特徴とする請求項2に記載の電子部品内蔵型プリント基板。
- 前記金属基板が、2つ備えられて2段に配置され、
前記2つの金属基板を互いに接着させる接着層をさらに含むことを特徴とする請求項1に記載の電子部品内蔵型プリント基板。 - 前記絶縁層および前記金属基板を貫通して前記回路層と導通しているスルーホールをさらに含むことを特徴とする請求項1に記載の電子部品内蔵型プリント基板。
- 前記金属基板が、アルミニウムで形成され、前記陽極酸化膜が、アルミナで形成されたことを特徴とする請求項1に記載の電子部品内蔵型プリント基板。
- (A)金属基板にキャビティを形成した後、陽極酸化工程によって前記金属基板の全面に陽極酸化膜を形成する段階と、
(B)前記キャビティの内部に2つの電子部品を2段に配置する段階と、
(C)前記金属基板の両面に絶縁層を積層することにより、前記キャビティの内部に配置した前記電子部品を埋め込ませる段階と、
(D)前記絶縁層の露出面に、前記電子部品の接続端子に接続されたビアを含む回路層を形成する段階とを含んでなることを特徴とする電子部品内蔵型プリント基板の製造方法。 - 前記(A)段階で、前記金属基板の両面からエッチング工程によって前記金属基板を除去して前記キャビティを形成するとき、前記金属基板の中心を所定の厚さ残存させて前記キャビティの厚さ方向を分割する支持板を形成することを特徴とする請求項9に記載の電子部品内蔵型プリント基板の製造方法。
- 前記(B)段階で、前記支持板の両面に接着層を塗布して前記2つの電子部品を固定することを特徴とする請求項10に記載の電子部品内蔵型プリント基板の製造方法。
- 前記(A)段階で、前記支持板を形成するとき、前記支持板を貫通する少なくとも一つの開口部を形成することを特徴とする請求項10に記載の電子部品内蔵型プリント基板の製造方法。
- 前記(D)段階が、前記絶縁層および前記金属基板を貫通して前記回路層と導通するスルーホールを形成する段階をさらに含むことを特徴とする請求項9に記載の電子部品内蔵型プリント基板の製造方法。
- 前記(A)段階で、前記金属基板が、アルミニウムで形成され、前記陽極酸化膜が、アルミナで形成されたことを特徴とする請求項9に記載の電子部品内蔵型プリント基板の製造方法。
- (A)2つの金属基板にキャビティを形成した後、陽極酸化工程によって前記2つの金属基板の全面に陽極酸化膜を形成する段階と、
(B)前記キャビティの内部に電子部品を配置する段階と、
(C)前記2つの金属基板の一面に絶縁層を積層することにより、前記キャビティの内部に配置した前記電子部品を埋め込ませる段階と、
(D)前記絶縁層を積層した前記2つの金属基板を接着層を用いて互いに接着させる段階と、
(E)前記絶縁層の露出面に、前記電子部品の接続端子に接続されたビアを含む回路層を形成する段階とを含んでなることを特徴とする電子部品内蔵型プリント基板の製造方法。 - 前記(E)段階が、前記絶縁層および前記金属基板を貫通して前記回路層と導通するスルーホールを形成する段階をさらに含むことを特徴とする請求項15に記載の電子部品内蔵型プリント基板の製造方法。
- 前記(A)段階で、前記金属基板が、アルミニウムで形成され、前記陽極酸化膜が、アルミナで形成されたことを特徴とする請求項15に記載の電子部品内蔵型プリント基板の製造方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2010-0000910 | 2010-01-06 | ||
KR1020100000910A KR101119303B1 (ko) | 2010-01-06 | 2010-01-06 | 전자부품 내장형 인쇄회로기판 및 그 제조방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2011142286A true JP2011142286A (ja) | 2011-07-21 |
JP5140112B2 JP5140112B2 (ja) | 2013-02-06 |
Family
ID=44224592
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010107474A Expired - Fee Related JP5140112B2 (ja) | 2010-01-06 | 2010-05-07 | 電子部品内蔵型プリント基板およびその製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20110164391A1 (ja) |
JP (1) | JP5140112B2 (ja) |
KR (1) | KR101119303B1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2018006450A (ja) * | 2016-06-29 | 2018-01-11 | 新光電気工業株式会社 | 電子部品内蔵基板及びその製造方法と電子部品装置 |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101018109B1 (ko) * | 2009-08-24 | 2011-02-25 | 삼성전기주식회사 | 다층 배선 기판 및 그의 제조방법 |
TW201110285A (en) * | 2009-09-08 | 2011-03-16 | Unimicron Technology Corp | Package structure having embedded semiconductor element and method of forming the same |
KR101560430B1 (ko) | 2011-08-12 | 2015-10-14 | 엘지디스플레이 주식회사 | 표시장치 |
US20130258623A1 (en) * | 2012-03-29 | 2013-10-03 | Unimicron Technology Corporation | Package structure having embedded electronic element and fabrication method thereof |
KR101976602B1 (ko) * | 2012-12-26 | 2019-05-10 | 엘지이노텍 주식회사 | 인쇄회로 기판 및 그 제조 방법 |
KR102237778B1 (ko) * | 2014-01-22 | 2021-04-09 | 엘지이노텍 주식회사 | 임베디드 인쇄회로기판 |
US9613933B2 (en) | 2014-03-05 | 2017-04-04 | Intel Corporation | Package structure to enhance yield of TMI interconnections |
JP2015228455A (ja) * | 2014-06-02 | 2015-12-17 | 株式会社東芝 | 半導体装置及びその製造方法 |
CN104157580B (zh) * | 2014-08-12 | 2017-06-06 | 上海航天电子通讯设备研究所 | 基于铝阳极氧化技术的埋置芯片互连封装方法及结构 |
KR102276513B1 (ko) * | 2014-11-10 | 2021-07-14 | 삼성전기주식회사 | 열전 모듈을 갖는 기판, 반도체 패키지 및 이들의 제조방법 |
US9875997B2 (en) * | 2014-12-16 | 2018-01-23 | Qualcomm Incorporated | Low profile reinforced package-on-package semiconductor device |
GB2535763B (en) * | 2015-02-26 | 2018-08-01 | Murata Manufacturing Co | An embedded magnetic component device |
US10231338B2 (en) | 2015-06-24 | 2019-03-12 | Intel Corporation | Methods of forming trenches in packages structures and structures formed thereby |
KR101922874B1 (ko) * | 2015-12-21 | 2018-11-28 | 삼성전기 주식회사 | 전자 부품 패키지 |
CN109413836B (zh) * | 2017-08-15 | 2021-04-20 | 鹏鼎控股(深圳)股份有限公司 | 电路板及其制备方法 |
KR102079153B1 (ko) * | 2018-04-13 | 2020-04-07 | 주식회사 피앤엠테크 | 임베디드 기판 및 그 제조방법 |
CN111199922A (zh) | 2018-11-20 | 2020-05-26 | 奥特斯科技(重庆)有限公司 | 部件承载件及其制造方法 |
KR20210137275A (ko) * | 2020-05-07 | 2021-11-17 | 삼성전자주식회사 | 반도체 패키지 및 그의 제조 방법 |
CN112989745A (zh) * | 2021-02-20 | 2021-06-18 | 南京工程学院 | 一种pcb电子元器件优化布置的热设计方法 |
KR20230090619A (ko) * | 2021-12-15 | 2023-06-22 | 삼성전기주식회사 | 인쇄회로기판 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05129482A (ja) * | 1991-08-27 | 1993-05-25 | Kyocera Corp | 電子部品収納用パツケージ |
JPH07326708A (ja) * | 1994-06-01 | 1995-12-12 | Toppan Printing Co Ltd | マルチチップモジュール半導体装置 |
JP2001274034A (ja) * | 2000-01-20 | 2001-10-05 | Shinko Electric Ind Co Ltd | 電子部品パッケージ |
JP2005317903A (ja) * | 2004-03-31 | 2005-11-10 | Alps Electric Co Ltd | 回路部品モジュール、回路部品モジュールスタック、記録媒体およびこれらの製造方法 |
JP2009081193A (ja) * | 2007-09-25 | 2009-04-16 | Sanyo Electric Co Ltd | 発光モジュールおよびその製造方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5578869A (en) * | 1994-03-29 | 1996-11-26 | Olin Corporation | Components for housing an integrated circuit device |
US20020020898A1 (en) * | 2000-08-16 | 2002-02-21 | Vu Quat T. | Microelectronic substrates with integrated devices |
JP2005286273A (ja) * | 2004-03-31 | 2005-10-13 | Sohki:Kk | 回路基板、回路基板の製造方法、電子デバイス、電子デバイスの製造方法 |
KR100733251B1 (ko) * | 2005-09-29 | 2007-06-27 | 삼성전기주식회사 | 이중 전자부품이 내장된 인쇄회로기판 및 그 제조방법 |
KR100726240B1 (ko) * | 2005-10-04 | 2007-06-11 | 삼성전기주식회사 | 전자소자 내장 인쇄회로기판 및 그 제조방법 |
KR100656751B1 (ko) * | 2005-12-13 | 2006-12-13 | 삼성전기주식회사 | 전자소자 내장 인쇄회로기판 및 그 제조방법 |
KR100945285B1 (ko) * | 2007-09-18 | 2010-03-03 | 삼성전기주식회사 | 전자소자 내장 인쇄회로기판 및 그 제조 방법 |
US20100289130A1 (en) * | 2009-05-12 | 2010-11-18 | Interconnect Portfolio Llc | Method and Apparatus for Vertical Stacking of Integrated Circuit Chips |
-
2010
- 2010-01-06 KR KR1020100000910A patent/KR101119303B1/ko active IP Right Grant
- 2010-05-06 US US12/775,341 patent/US20110164391A1/en not_active Abandoned
- 2010-05-07 JP JP2010107474A patent/JP5140112B2/ja not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05129482A (ja) * | 1991-08-27 | 1993-05-25 | Kyocera Corp | 電子部品収納用パツケージ |
JPH07326708A (ja) * | 1994-06-01 | 1995-12-12 | Toppan Printing Co Ltd | マルチチップモジュール半導体装置 |
JP2001274034A (ja) * | 2000-01-20 | 2001-10-05 | Shinko Electric Ind Co Ltd | 電子部品パッケージ |
JP2005317903A (ja) * | 2004-03-31 | 2005-11-10 | Alps Electric Co Ltd | 回路部品モジュール、回路部品モジュールスタック、記録媒体およびこれらの製造方法 |
JP2009081193A (ja) * | 2007-09-25 | 2009-04-16 | Sanyo Electric Co Ltd | 発光モジュールおよびその製造方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2018006450A (ja) * | 2016-06-29 | 2018-01-11 | 新光電気工業株式会社 | 電子部品内蔵基板及びその製造方法と電子部品装置 |
US10264681B2 (en) | 2016-06-29 | 2019-04-16 | Shinko Electric Industries Co., Ltd. | Electronic component built-in substrate and electronic component device |
Also Published As
Publication number | Publication date |
---|---|
KR101119303B1 (ko) | 2012-03-20 |
US20110164391A1 (en) | 2011-07-07 |
KR20110080599A (ko) | 2011-07-13 |
JP5140112B2 (ja) | 2013-02-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5140112B2 (ja) | 電子部品内蔵型プリント基板およびその製造方法 | |
KR101077410B1 (ko) | 방열부재를 구비한 전자부품 내장형 인쇄회로기판 및 그 제조방법 | |
JP6504665B2 (ja) | 印刷回路基板、その製造方法、及び電子部品モジュール | |
JP2012134536A (ja) | 電子部品内装型プリント基板の製造方法 | |
US20110010932A1 (en) | Wiring board, semiconductor device having wiring board, and method of manufacturing wiring board | |
WO2010052942A1 (ja) | 電子部品内蔵配線板及びその製造方法 | |
JP2016207958A (ja) | 配線基板及び配線基板の製造方法 | |
JP2008016819A (ja) | パッケージオンパッケージのボトム基板及びその製造方法 | |
JPH11233678A (ja) | Icパッケージの製造方法 | |
JP2016207957A (ja) | 配線基板及び配線基板の製造方法 | |
KR100789530B1 (ko) | 칩 내장형 인쇄회로기판 및 그 제조방법 | |
JP2003318327A (ja) | プリント配線板および積層パッケージ | |
JP2012134437A (ja) | 電子部品内蔵型プリント基板およびその製造方法 | |
KR20160086181A (ko) | 인쇄회로기판, 패키지 및 그 제조방법 | |
JP2011187913A (ja) | 電子素子内蔵型印刷回路基板及びその製造方法 | |
JP2010226075A (ja) | 配線板及びその製造方法 | |
US11570905B2 (en) | Method of manufacturing component carrier and component carrier | |
KR101084910B1 (ko) | 전자부품 내장형 인쇄회로기판 및 그 제조방법 | |
JP2011187912A (ja) | 電子素子内蔵型印刷回路基板及びその製造方法 | |
JP5660462B2 (ja) | プリント配線板 | |
KR101092945B1 (ko) | 패키지 기판, 이를 구비한 전자소자 패키지, 및 패키지 기판 제조 방법 | |
KR101214671B1 (ko) | 전자 부품 내장형 인쇄회로기판 및 그 제조 방법 | |
JP2011082471A (ja) | 電子部品内装型プリント基板及びその製造方法 | |
JP4779619B2 (ja) | 支持板、多層回路配線基板及びそれを用いた半導体パッケージ | |
KR100858032B1 (ko) | 능동 소자 내장형 인쇄회로기판 및 제조 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120321 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120621 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20121030 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20121116 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5140112 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20151122 Year of fee payment: 3 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |