JP2008270346A - 配線基板の製造方法及び半導体装置の製造方法及び配線基板 - Google Patents
配線基板の製造方法及び半導体装置の製造方法及び配線基板 Download PDFInfo
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- JP2008270346A JP2008270346A JP2007108152A JP2007108152A JP2008270346A JP 2008270346 A JP2008270346 A JP 2008270346A JP 2007108152 A JP2007108152 A JP 2007108152A JP 2007108152 A JP2007108152 A JP 2007108152A JP 2008270346 A JP2008270346 A JP 2008270346A
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- electrode pad
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- wiring board
- manufacturing
- insulating layer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 112
- 238000004519 manufacturing process Methods 0.000 title claims description 87
- 238000000034 method Methods 0.000 title claims description 55
- 229910000679 solder Inorganic materials 0.000 claims abstract description 89
- 239000000758 substrate Substances 0.000 claims description 146
- 239000002184 metal Substances 0.000 claims description 49
- 229910052751 metal Inorganic materials 0.000 claims description 49
- 230000002093 peripheral effect Effects 0.000 claims description 12
- 238000007788 roughening Methods 0.000 claims description 8
- 230000008646 thermal stress Effects 0.000 abstract description 13
- 230000032798 delamination Effects 0.000 abstract description 8
- 238000010030 laminating Methods 0.000 abstract description 5
- 239000010949 copper Substances 0.000 description 58
- 239000010408 film Substances 0.000 description 34
- 238000007747 plating Methods 0.000 description 23
- 229920005989 resin Polymers 0.000 description 23
- 239000011347 resin Substances 0.000 description 23
- 238000012986 modification Methods 0.000 description 20
- 230000004048 modification Effects 0.000 description 20
- 229910052759 nickel Inorganic materials 0.000 description 18
- 150000002739 metals Chemical class 0.000 description 17
- 239000003822 epoxy resin Substances 0.000 description 10
- 229920000647 polyepoxide Polymers 0.000 description 10
- 229910001316 Ag alloy Inorganic materials 0.000 description 9
- 229910020836 Sn-Ag Inorganic materials 0.000 description 9
- 229910020988 Sn—Ag Inorganic materials 0.000 description 9
- 229910052718 tin Inorganic materials 0.000 description 9
- 229910001128 Sn alloy Inorganic materials 0.000 description 8
- 238000010586 diagram Methods 0.000 description 8
- 239000004332 silver Substances 0.000 description 8
- 238000001039 wet etching Methods 0.000 description 8
- 238000010438 heat treatment Methods 0.000 description 7
- 230000018109 developmental process Effects 0.000 description 6
- 238000009713 electroplating Methods 0.000 description 6
- 238000003475 lamination Methods 0.000 description 6
- 238000000059 patterning Methods 0.000 description 6
- 238000005476 soldering Methods 0.000 description 6
- 239000007788 liquid Substances 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 238000007772 electroless plating Methods 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 239000009719 polyimide resin Substances 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229920001187 thermosetting polymer Polymers 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- 230000007261 regionalization Effects 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 230000003746 surface roughness Effects 0.000 description 2
- 239000004925 Acrylic resin Substances 0.000 description 1
- 229920000178 Acrylic resin Polymers 0.000 description 1
- QCEUXSAXTBNJGO-UHFFFAOYSA-N [Ag].[Sn] Chemical compound [Ag].[Sn] QCEUXSAXTBNJGO-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
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- H—ELECTRICITY
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- H05K3/46—Manufacturing multilayer circuits
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- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
- H05K1/113—Via provided in pad; Pad over filled via
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- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
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Abstract
【解決手段】半導体装置100は、半導体チップ110が配線基板120にフリップチップ実装してなる構成である。配線基板120は、複数の配線層と複数の絶縁層が積層された多層構造であり、チップ実装側に第1電極パッド130が形成されている。第1電極パッド130のテーパ面132は、はんだ接続側又はチップ実装側となる上方向に対して絞られる向きの勾配を有する。そのため、はんだ接続側又はチップ実装側への力に対する保持力が強化されると共に、テーパ面132が第1層の絶縁層のテーパ状内壁に密着して絶縁層との接合強度が高められている。これにより、絶縁層でデラミネーショ及びクラックが発生することを防止できる。
【選択図】図2
Description
また、電極パッド10にはんだバンプを介して半導体チップを実装した後に、上記のようなデラミネーションやクラックが発生している状態で、半導体チップを配線基板から引き離そうとする力が加えられると、電極パッド10が第1絶縁層12から分離するおそれがあった。
本発明は、支持基板上に絶縁層を形成する第1工程と、前記絶縁層に前記支持基板側が小径で開口側が大径となるテーパ状開口を形成する第2工程と、前記テーパ状開口の内部に開口側が大径となる電極パッドを形成する第3工程と、前記絶縁層の表面に前記電極パッドと電気的に接続される配線層を形成する第4工程と、前記支持基板を除去して前記電極パッドの小径側端面を露出する第5工程と、を有することにより、上記課題を解決するものである。
本発明は、前記電極パッドが、テーパ状外周面の水平面に対する傾き角θが50度〜80度に設定されることにより、上記課題を解決するものである。
本発明は、請求項1に記載の配線基板の製造方法であって、前記第4工程は、前記絶縁層を形成する前に前記電極パッドのテーパ状外周面を含む表面を粗面化する工程を含むことにより、上記課題を解決するものである。
本発明は、請求項2に記載の配線基板の製造方法であって、前記第3工程は、前記電極パッドを形成する前に前記テーパ状開口の内部を粗面化する工程を含むことにより、上記課題を解決するものである。
本発明は、請求項1に記載の配線基板の製造方法であって、前記支持基板は金属からなり、前記第3工程は、前記支持基板と前記電極パッドとの間に前記支持基板と同種の金属層を形成する工程を含み、前記第7工程は、前記支持基板を除去すると共に、前記金属層を除去して電極パッドの露出面がテーパ状開口を形成する工程を含むことにより、上記課題を解決するものである。
本発明は、請求項2に記載の配線基板の製造方法であって、前記支持基板は金属からなり、前記第3工程は、前記支持基板と前記電極パッドとの間に前記支持基板と同種の金属層を形成する工程を含み、前記第5工程は、前記支持基板を除去すると共に、前記金属層を除去して電極パッドの露出面がテーパ状開口を形成する工程を含むことにより、上記課題を解決するものである。
本発明は、前記請求項1乃至7の何れかに1項に記載された配線基板の製造方法を用いた半導体装置の製造方法であって、前記電極パッドにはんだバンプを介して半導体チップを実装する工程を有することにより、上記課題を解決するものである。
本発明は、前記請求項1乃至7の何れかに1項に記載された配線基板の製造方法を用いた半導体装置の製造方法であって、前記配線基板の前記電極パッドが形成される電極パッド形成面と反対側の面に半導体チップを実装する工程を有することにより、上記課題を解決するものである。
本発明は、電極パッドと、前記電極パッドに接して形成される絶縁層と、を有する配線基板において、前記電極パッドは、前記絶縁層が形成される絶縁層側が大径で、前記電極パッドの露出面側が小径となるテーパ状に形成されることにより、上記課題を解決するものである。
半導体チップ110の端子は、はんだバンプ180を介してAu層170にはんだ付けされることで、第1電極パッド130に導通される。はんだバンプ180は、はんだボールを第1電極パッド130に搭載し、リフロー(加熱処理)して形成される。本実施例においては、例えば、第1電極パッド130の直径が70μm〜100μm程度、厚さが15μm(±10μm)程度となるように形成される。
また、この変形例の場合、前述した図3Nの工程で、半導体チップ110を配線基板120に搭載し、その後、支持基板200除去することにより、半導体装置を完成するようにしても良い。
ここで、半導体装置400に用いられる配線基板420の製造方法について図6A〜図6Oを参照して説明する。図6A〜図6Oは実施例2の配線基板420の製造方法(その1〜その15)を説明するための図である。
また、この変形例の場合、前述した図6Nの工程で、半導体チップ110を配線基板420に搭載し、その後、支持基板200を除去することにより、半導体装置を完成するようにしても良い。
第1電極パッド130は、前述した実施例1、2と同様に、上面側(はんだ接続側及びチップ実装側)の外径が小径で、下面側(基板の積層側)が大径となるように形成されるため、外周面がテーパ面132になっている。本実施例では、第1電極パッド130のテーパ面132の勾配角(水平面に対する傾き角)θがθ=50度〜80度となるように勾配が設定されている。尚、この勾配角θの角度は、これに限るものではなく、50度未満あるいは80度以上の任意の角度に設定することも可能である。
ここで、半導体装置500に用いられる配線基板520の製造方法について図9A〜図9Sを参照して説明する。図9A〜図9Sは実施例3の配線基板520の製造方法(その1〜その20)を説明するための図である。尚、図9A〜図9Sにおいては、第1電極パッド130が配線基板120の下面側となるフェイスダウンの向き(前述した図8に示す積層構造と上下方向に逆の向き)で各層を積層する。
また、この変形例の場合、前述した図9Rの工程で、半導体チップ110を配線基板120に搭載し、その後、支持基板200除去することにより、半導体装置を完成するようにしても良い。
また、本実施例ではんだバンプ180をリフローする際の熱応力が発生した場合には、第1電極パッド130の外周に基板の積層側よりもチップ実装側が小径となるテーパ面132が形成されているので、テーパ面132と第1絶縁層121との密着性が強化されており、これにより、クラック発生が防止される。
また、この変形例の場合、半導体チップ110を配線基板620に搭載し、その後、支持基板200を除去することにより、半導体装置を完成するようにしても良い。
また、本発明は、上記はんだバンプ180を形成する構成の半導体装置に限らず、基板に電子部品が搭載された構成、あるいは基板に配線パターンが形成された構成でも良いので、例えば、はんだバンプを介して基板上に接合されるフリップチップ、あるいははんだバンプを介して回路基板を接合させる多層基板やインターポーザにも適用することができるのは勿論である。
110 半導体チップ
120,420,520,620 配線基板
121 第1絶縁層
122 第1層
123 第2絶縁層
124 第2層
126 第3層
128 第4層
130 第1電極パッド
132 テーパ面
134,142,152 ビア
136 第3電極パッド
140,150 配線パターン層
160 第2電極パッド
180 はんだバンプ
200 支持基板
220 第1電極形成用テーパ状開口
430 テーパ状開口
430 電極開口
440 Cu層
Claims (10)
- 支持基板上にレジスト層を形成する第1工程と、
前記レジスト層に前記支持基板側が小径で開口側が大径となるテーパ状開口を形成する第2工程と、
前記テーパ状開口の内部に開口側が大径となる電極パッドを形成する第3工程と、
前記レジスト層を除去し、前記電極パッドの周囲及び前記支持基板上に絶縁層を形成する第4工程と、
前記絶縁層に前記電極パッドを露出させるビアを形成する第5工程と、
前記ビア及び前記絶縁層の表面に前記電極パッドと電気的に接続される配線層を形成する第6工程と、
前記支持基板を除去して前記電極パッドの小径側端面を露出する第7工程と、
を有することを特徴とする配線基板の製造方法。 - 支持基板上に絶縁層を形成する第1工程と、
前記絶縁層に前記支持基板側が小径で開口側が大径となるテーパ状開口を形成する第2工程と、
前記テーパ状開口の内部に開口側が大径となる電極パッドを形成する第3工程と、
前記絶縁層の表面に前記電極パッドと電気的に接続される配線層を形成する第4工程と、
前記支持基板を除去して前記電極パッドの小径側端面を露出する第5工程と、
を有することを特徴とする配線基板の製造方法。 - 前記電極パッドは、テーパ状外周面の水平面に対する傾き角θが50度〜80度に設定されることを特徴とする請求項1または2に記載の配線基板の製造方法。
- 請求項1に記載の配線基板の製造方法であって、
前記第4工程は、前記絶縁層を形成する前に前記電極パッドのテーパ状外周面を含む表面を粗面化する工程を含むことを特徴とする配線基板の製造方法。 - 請求項2に記載の配線基板の製造方法であって、
前記第3工程は、前記電極パッドを形成する前に前記テーパ状開口の内部を粗面化する工程を含むことを特徴とする配線基板の製造方法。 - 請求項1に記載の配線基板の製造方法であって、
前記支持基板は金属からなり、
前記第3工程は、前記支持基板と前記電極パッドとの間に前記支持基板と同種の金属層を形成する工程を含み、
前記第7工程は、前記支持基板を除去すると共に、前記金属層を除去して電極パッドの露出面がテーパ状開口を形成する工程を含むことを特徴とする配線基板の製造方法。 - 請求項2に記載の配線基板の製造方法であって、
前記支持基板は金属からなり、
前記第3工程は、前記支持基板と前記電極パッドとの間に前記支持基板と同種の金属層を形成する工程を含み、
前記第5工程は、前記支持基板を除去すると共に、前記金属層を除去して電極パッドの露出面がテーパ状開口を形成する工程を含むことを特徴とする配線基板の製造方法。 - 前記請求項1乃至7の何れかに1項に記載された配線基板の製造方法を用いた半導体装置の製造方法であって、
前記電極パッドにはんだバンプを介して半導体チップを実装する工程を有することを特徴とする半導体装置の製造方法。 - 前記請求項1乃至7の何れかに1項に記載された配線基板の製造方法を用いた半導体装置の製造方法であって、
前記配線基板の前記電極パッドが形成される電極パッド形成面と反対側の面に半導体チップを実装する工程を有することを特徴とする半導体装置の製造方法。 - 電極パッドと、
前記電極パッドに接して形成される絶縁層と、
を有する配線基板において、
前記電極パッドは、前記絶縁層が形成される絶縁層側が大径で、前記電極パッドの露出面側が小径となるテーパ状に形成されることを特徴とする配線基板。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
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JP2007108152A JP5032187B2 (ja) | 2007-04-17 | 2007-04-17 | 配線基板の製造方法及び半導体装置の製造方法及び配線基板 |
TW097112962A TW200849530A (en) | 2007-04-17 | 2008-04-10 | Wiring board manufacturing method, semiconductor device manufacturing method and wiring board |
US12/102,303 US8225502B2 (en) | 2007-04-17 | 2008-04-14 | Wiring board manufacturing method |
CNA2008100902857A CN101290889A (zh) | 2007-04-17 | 2008-04-17 | 布线板制造方法、半导体器件制造方法和布线板 |
KR1020080035535A KR101458989B1 (ko) | 2007-04-17 | 2008-04-17 | 배선 기판의 제조 방법, 반도체 장치의 제조 방법 및 배선기판 |
US13/525,779 US20120256320A1 (en) | 2007-04-17 | 2012-06-18 | Wiring board manufacturing method, semiconductor device manufacturing method and wiring board |
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JP2007108152A JP5032187B2 (ja) | 2007-04-17 | 2007-04-17 | 配線基板の製造方法及び半導体装置の製造方法及び配線基板 |
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JP (1) | JP5032187B2 (ja) |
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Also Published As
Publication number | Publication date |
---|---|
US20120256320A1 (en) | 2012-10-11 |
TW200849530A (en) | 2008-12-16 |
US8225502B2 (en) | 2012-07-24 |
KR20080093910A (ko) | 2008-10-22 |
US20080257596A1 (en) | 2008-10-23 |
CN101290889A (zh) | 2008-10-22 |
KR101458989B1 (ko) | 2014-11-07 |
JP5032187B2 (ja) | 2012-09-26 |
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