JPWO2014188760A1 - モジュール - Google Patents
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- JPWO2014188760A1 JPWO2014188760A1 JP2015518125A JP2015518125A JPWO2014188760A1 JP WO2014188760 A1 JPWO2014188760 A1 JP WO2014188760A1 JP 2015518125 A JP2015518125 A JP 2015518125A JP 2015518125 A JP2015518125 A JP 2015518125A JP WO2014188760 A1 JPWO2014188760 A1 JP WO2014188760A1
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- columnar conductor
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- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
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- H05K3/28—Applying non-metallic protective coatings
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H05K1/115—Via connections; Lands around holes or via connections
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- H05K1/18—Printed circuits structurally associated with non-printed electric components
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- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
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- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
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- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
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- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81399—Material
- H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H01L2924/151—Die mounting substrate
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- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0364—Conductor shape
- H05K2201/0367—Metallic bump or raised conductor not used as solder bump
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- H05K2201/06—Thermal details
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- H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
- H05K2203/025—Abrading, e.g. grinding or sand blasting
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- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0562—Details of resist
- H05K2203/0588—Second resist used as pattern over first resist
Abstract
Description
本発明の第1実施形態にかかるモジュール1について、図1〜図3を参照して説明する。なお、図1は第1実施形態にかかるモジュール1の断面図、図2は図1のA領域の拡大図、図3(a)は、モジュール1の配線基板の平面図、(b)は(a)のB領域の拡大図である。
次に、モジュール1の製造方法について、図4および図5を参照して説明する。なお、図4および図5はモジュール1の製造方法を説明するための図であり、図2に対応するモジュール1の部分断面図である。また、図4(a)〜(f)はその製造方法の各工程を示し、図5(a)〜(c)は図4(f)に続く各工程を示す。
本発明の第2実施形態にかかるモジュール1aについて、図6および図7を参照して説明する。なお、図6はモジュール1aの断面図、図7は図6のC領域の拡大図である。
次に、モジュール1aの製造方法について、図8および図9を参照して説明する。なお、図8および図9はモジュール1aの製造方法を説明するための図であり、図7に対応するモジュール1aの部分断面図である。また、図8(a)〜(f)はその製造方法の各工程を示し、図9(a)〜(e)は図8(f)に続く各工程を示す。
次に、柱状導体の変形例について、図10を参照して説明する。なお、図10(a)〜(c)は、本例にかかる柱状導体5c〜5eの断面図である。
2 配線基板
3a,3b 部品
4a 基板電極
5a〜5e 柱状導体
6 中間被膜
7a 第1封止樹脂層(封止樹脂層)
Claims (9)
- 部品が実装される配線基板と、
前記配線基板の一方主面に形成された基板電極と、
その一端が前記基板電極に接続された柱状導体と、
前記柱状導体の外周面を被覆して形成された中間被膜と、
前記配線基板の一方主面および前記中間被膜を被覆して設けられた封止樹脂層とを備え、
前記中間被膜が、前記柱状導体の線膨張係数と前記封止樹脂層の線膨張係数の間の線膨張係数を有する
ことを特徴とするモジュール。 - 前記柱状導体は、前記基板電極との接続面の中心点が、前記基板電極の前記柱状導体との接続面の中心点に対して、所定の方向にずれて配置されていることを特徴とする請求項1に記載のモジュール。
- 前記柱状導体の他端が接続されるマザー基板の線膨張係数が前記封止樹脂層の線膨張係数よりも大きい場合に、
前記所定の方向は、前記配線基板の一方主面の中央方向であることを特徴とする請求項2に記載のモジュール。 - 前記柱状導体の他端が接続されるマザー基板の線膨張係数が前記封止樹脂層の線膨張係数よりも小さい場合に、
前記所定の方向は、前記配線基板の一方主面の端縁方向であることを特徴とする請求項2に記載のモジュール。 - 前記中間被膜が金属からなることを特徴とする請求項1ないし4のいずれかに記載のモジュール。
- 前記中間被膜が、前記基板電極の前記柱状導体に対向して接続される接続面のうち、前記柱状導体と接触していない部分も被覆して設けられていることを特徴とする請求項1ないし5のいずれかに記載のモジュール。
- 前記基板電極の前記接続面の面積が、前記柱状導体の前記基板電極に対向して接続される接続面の面積と略同一であることを特徴とする請求項1ないし6のいずれかに記載のモジュール。
- 前記柱状導体は、その長さ方向に段差を有することを特徴とする請求項1ないし7のいずれかに記載のモジュール。
- 前記柱状導体は、前記基板電極に接続される一端側の横断面積が、他端側の横断面積よりも大きく形成されていることを特徴とする請求項1ないし8のいずれかに記載のモジュール。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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JP2013107346 | 2013-05-21 | ||
JP2013107346 | 2013-05-21 | ||
PCT/JP2014/056192 WO2014188760A1 (ja) | 2013-05-21 | 2014-03-10 | モジュール |
Publications (2)
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JPWO2014188760A1 true JPWO2014188760A1 (ja) | 2017-02-23 |
JP6137309B2 JP6137309B2 (ja) | 2017-05-31 |
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US (1) | US9832871B2 (ja) |
JP (1) | JP6137309B2 (ja) |
CN (1) | CN105230135B (ja) |
WO (1) | WO2014188760A1 (ja) |
Families Citing this family (10)
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JP6520801B2 (ja) * | 2016-04-19 | 2019-05-29 | 株式会社村田製作所 | 電子部品 |
JP6512161B2 (ja) * | 2016-04-21 | 2019-05-15 | 株式会社村田製作所 | 電子部品 |
US10049893B2 (en) * | 2016-05-11 | 2018-08-14 | Advanced Semiconductor Engineering, Inc. | Semiconductor device with a conductive post |
WO2018003391A1 (ja) | 2016-06-29 | 2018-01-04 | 株式会社村田製作所 | 部品内蔵基板及びその製造方法、並びに高周波モジュール |
JP6791352B2 (ja) * | 2017-03-14 | 2020-11-25 | 株式会社村田製作所 | 回路モジュールおよびその製造方法 |
CN211858622U (zh) * | 2017-06-16 | 2020-11-03 | 株式会社村田制作所 | 电路基板及电路模块 |
CN111096090B (zh) * | 2017-09-20 | 2023-04-21 | 株式会社村田制作所 | 陶瓷基板的制造方法、陶瓷基板以及模块 |
CN112789723A (zh) * | 2018-09-28 | 2021-05-11 | 株式会社村田制作所 | 电路模块和通信装置 |
WO2023074262A1 (ja) * | 2021-11-01 | 2023-05-04 | 株式会社村田製作所 | 回路モジュール |
EP4333565A1 (en) * | 2022-09-01 | 2024-03-06 | Murata Manufacturing Co., Ltd. | Electronic component with reduced stress |
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US9832871B2 (en) | 2017-11-28 |
CN105230135A (zh) | 2016-01-06 |
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US20160073499A1 (en) | 2016-03-10 |
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