CN1835654B - 配线基板及其制造方法 - Google Patents

配线基板及其制造方法 Download PDF

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Publication number
CN1835654B
CN1835654B CN2006100598487A CN200610059848A CN1835654B CN 1835654 B CN1835654 B CN 1835654B CN 2006100598487 A CN2006100598487 A CN 2006100598487A CN 200610059848 A CN200610059848 A CN 200610059848A CN 1835654 B CN1835654 B CN 1835654B
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Prior art keywords
wiring substrate
semiconductor chip
insulating barrier
stiffener
distribution structure
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CN2006100598487A
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CN1835654A (zh
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山野孝治
春原昌宏
饭塚肇
小山铁也
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Shinko Electric Industries Co Ltd
Shinko Electric Co Ltd
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Shinko Electric Co Ltd
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Abstract

一种配线基板，包括在其中嵌入半导体芯片的绝缘层，以及与半导体芯片连接的配线结构。加强绝缘层的加强构件嵌入在绝缘层中。这可以实现配线基板的薄型化，并且可以抑制配线基板的翘曲。

Description

配线基板及其制造方法
技术领域
本发明涉及一种制造配线基板的方法，更具体地说，本发明涉及制造结合了半导体芯片的配线基板的方法。
背景技术
当前，使用半导体器件，如半导体芯片，的电子装置的高性能化已取得进展。这样便存在如下需求：在基板上安装半导体芯片的高密度化、使其上安装有半导体芯片的基板的小型化以及基板内的节省空间化。
因此，已提出半导体芯片嵌入其中的基板，即内置芯片型配线基板。并且已提出了多种用于将半导体芯片结合在基板内的结构(例如，参考JP-A-2001-196525)。这种内置芯片型配线基板具有与半导体芯片连接的配线结构。而且，在配线基板上形成有端子连接部，这样使得配线基板可以与其他装置、母板或类似装置连接。
然而，在实现了内置芯片型配线基板的薄型化(变薄)和高密度化的情况下，可能出现配线基板翘曲的问题。为了解决配线基板的这种翘曲，有必要将具有预定厚度的基板，如芯板，与半导体芯片嵌入在其中的层进行层叠，以使配线基板具有抑制翘曲的结构。因此，在具有这种层叠结构的内置芯片型配线基板中，难以减小配线基板的厚度和提高配线基板中的密度。
而且，在抑制配线基板翘曲的同时，难以实现配线基板的薄型化。
发明内容
本发明的目的是提供一种新型且实用的配线基板，以及一种制造该配线基板的方法，从而解决上述问题。
在本发明中，可以实现结合半导体芯片的配线基板的薄型化，并且可以抑制这种配线基板的翘曲。
在一些实施例中，本发明的配线基板包括：至少一个半导体芯片；绝缘层，其中嵌入至少一个半导体芯片；配线结构，其与半导体芯片连接；以及至少一个用于加强绝缘层的加强构件，所述加强构件嵌入在绝缘层中。
所述配线基板具有这样的结构：即，该结构能够抑制配线基板的翘曲，并可以实现配线基板的薄型化。
在本发明的配线基板中，加强构件与半导体芯片安装在基本相同的平面上。这样，可以减小配线基板的厚度。
在本发明的配线基板中，加强构件形成为包围半导体芯片。这样，可以有利地增强抑制配线基板翘曲的效果。
在本发明的配线基板中，配线结构具有多层配线结构。这样，可以实现配线结构的高密度化。因此，本实施例是有显著效果的。
在本发明的配线基板中，配线结构包括：第一配线子结构，其在半导体芯片的第一侧形成；以及第二配线子结构，其在半导体芯片的第二侧形成。这样，可以实现配线结构的高密度化。因此，本实施例是有显著效果的。
在本发明的配线基板中，第一配线子结构和第二配线子结构通过在绝缘层中形成的导通塞连接。这样，可以实现配线结构的高密度化。因此，本实施例是有显著效果的。
本发明的配线基板还包括：第一端子连接部，其在配线基板的第一表面上形成，并通过配线结构与半导体芯片连接；以及第二端子连接部，其在配线基板的第二表面上形成，并通过配线结构与半导体芯片连接。这样，端子连接部可以分别连接到半导体芯片的与第一表面和第二表面对应的两个侧面中的每个侧面上。
在本发明的配线基板中，加强构件由有机芯材料或金属材料制成。
在一些实施例中，本发明的制造配线基板的方法包括：形成下层配线结构；将至少一个半导体芯片安装在下层配线结构上，并且将半导体芯片与下层配线结构连接；形成至少一个加强构件；以及形成绝缘层，以便将半导体芯片和加强构件嵌入在绝缘层中，加强构件用于加强绝缘层。
该制造配线基板的方法能够抑制配线基板的翘曲，并且可以实现配线基板的薄型化。
在本发明的制造配线基板的方法中，加强构件与半导体芯片安装在基本相同的平面上。这样，可以减小配线基板的厚度。
本发明的制造配线基板的方法还包括：在绝缘层中形成导通塞，并且将导通塞与下层配线结构连接；以及形成上层配线结构，使得半导体芯片安装在下层配线结构与上层配线结构之间，并且将上层配线结构与导通塞连接。这样，可以实现配线结构的高密度化。因此，本实施例是有显著效果的。
在本发明的制造配线基板的方法中，下层配线结构形成在芯板上，并且方法还包括：去除芯板。这样，可以减小配线基板的厚度。而且，可以稳定地形成配线基板。因此，本实施例是有显著效果的。
在本发明的制造配线基板的方法中，芯板由导电材料制成，并且形成下层配线结构的步骤包括：通过使用芯板作为电极的电镀形成下层配线结构。在进行电镀时，这有助于供给电能。因此，本实施例是有显著效果的。
在本发明的制造配线基板的方法中，半导体芯片通过在半导体芯片上形成的柱形凸点电连接到下层配线结构上凸点是。这样，可以提高半导体芯片与配线结构之间连接的可靠性。
本发明的制造配线基板的方法还包括：在柱形凸点与下层配线结构之间形成由焊料制成的连接部。这样，可以提高半导体芯片与配线结构之间连接的可靠性。
根据本发明，减小了结合了半导体芯片的配线基板的厚度，并且可以抑制这种配线基板的翘曲。
附图说明
图1为根据本发明第一实施例的配线基板的示意性剖视图。
图2A为根据第一实施例的加强构件的设置方法的第一视图。
图2B为根据第一实施例的加强构件的设置方法的第二视图。
图2C为根据第一实施例的加强构件的设置方法的第三视图。
图3A为根据第一实施例的配线基板的制造方法的第一视图。
图3B为根据第一实施例的配线基板的制造方法的第二视图。
图3C为根据第一实施例的配线基板的制造方法的第三视图。
图3D为根据第一实施例的配线基板的制造方法的第四视图。
图3E为根据第一实施例的配线基板的制造方法的第五视图。
图3F为根据第一实施例的配线基板的制造方法的第六视图。
图3G为根据第一实施例的配线基板的制造方法的第七视图。
图3H为根据第一实施例的配线基板的制造方法的第八视图。
图3I为根据第一实施例的配线基板的制造方法的第九视图。
图3J为根据第一实施例的配线基板的制造方法的第十视图。
图3K为根据第一实施例的配线基板的制造方法的第十一视图。
图3L为根据第一实施例的配线基板的制造方法的第十二视图。
图3M为根据第一实施例的配线基板的制造方法的第十三视图。
图3N为根据第一实施例的配线基板的制造方法的第十四视图。
图3O为根据第一实施例的配线基板的制造方法的第十五视图。
图4为图1所示的配线基板的第一变型的视图。
图5为图1所示的配线基板的第二变型的视图。
具体实施方式
下面，参照附图对发明的实施例进行描述。
第一实施例
图1示意性地示出根据本发明第一实施例的配线基板100的剖视图。
参照图1，根据本实施例的配线基板100包括嵌入在绝缘层103中的半导体芯片109，以及与半导体芯片109连接的配线结构。该配线结构具有图案配线106、117，以及导通塞(via plug)105、116。
此外，配线基板100具有：端子连接部102，其形成在配线基板100的第一侧；端子连接部119，其形成在与配线基板100的第一侧相对的第二侧。端子连接部102、119通过配线结构与半导体芯片109连接。
迄今为止，在减小这种内置半导体芯片型配线基板厚度的情况下，有时将配线基板与用于支撑该配线基板且抑制配线基板翘曲的结构体，如芯板，进行层叠。因此，难以同时实现配线基板的薄型化和抑制配线基板的翘曲。
因此，根据本实施例的配线基板100构造成：将通过加强绝缘层103以防止配线基板翘曲的加强构件112嵌入在绝缘层103中，在该绝缘层103中嵌入有半导体芯片109。使用加强构件112可以抑制配线基板100的翘曲。在上述结构的情况下，可以有效地抑制配线基板100的翘曲，而几乎没有增加配线基板100的厚度。
在图1中，在配线基板100中设置单个半导体芯片109，以便简化附图和描述。然而，与其中安装单个半导体芯片109的结构类似，也可以在配线基板100中安装多个半导体芯片109。而且，在这种情况下，通过将加强构件112嵌入绝缘层103中，也可以类似地抑制配线基板100的翘曲。
这样，与具有其中绝缘层103和用于支撑该绝缘层103的芯板层叠在一起的结构的配线基板相比，本实施例的结构可以减小配线基板的厚度。
接下来，描述配线基板100的构造细节。例如，与半导体芯片109连接的配线结构包括例如由Cu制成的图案配线106、117，以及导通塞105、116。这些配线结构与半导体芯片109连接。
在半导体芯片109的电极片(未图示)上形成例如由Au制成的柱形凸点108(stud bump)，该柱形凸点108通过例如由焊料制成的连接部107电连接到图案配线106上。通过使用柱形凸点108，提高了半导体芯片109与图案配线106之间电连接的可靠性。而且，通过在柱形凸点108与图案配线106之间形成连接部107，也进一步提高了柱形凸点108与图案配线106之间电连接的可靠性。
图案配线106与导通塞105一体地形成。在导通塞105连接到图案配线106那侧的相对侧上，形成包括例如Au/Ni电镀层的端子连接部102。该端子连接部102是以其一个表面从绝缘层103露出的方式形成的。阻焊层120覆盖绝缘层103且包围端子连接部102。此外，也可以根据需要在端子连接部102上形成焊料凸点121。
此外，在配线基板中形成图案配线106侧的相对侧面上，在例如绝缘层103上形成图案配线117。导通塞116连接图案配线117和106。例如，导通塞116与图案配线117一体地形成。
包括例如Ni/Au电镀层的端子连接部119形成在图案配线117上。在绝缘层103和图案配线117上形成阻焊层118以包围端子连接部119。
例如，在所谓的积层基板中使用的积层树脂(build-up resin)可以用于形成绝缘层103。例如，可以使用热硬化树脂材料，如环氧树脂和聚酰亚胺树脂。
优选地，在半导体芯片109与图案配线106之间，或者在半导体芯片109与绝缘层103之间，形成由树脂材料构成的底部填充层(underfill layer)110。
配线基板100可以构造成例如省去阻焊层118、120以及焊料凸点121。
在根据本实施例的配线基板100中，可以连接到半导体芯片109上的端子连接部分别设置在配线基板的两侧面上。因此，配线基板100构造成：诸如其他的装置、其他的半导体芯片和母板等的连接对象可以容易地连接到配线基板100的两侧面上。
加强构件112可以使用各种材料。例如，可以使用比绝缘层103硬度高的树脂材料，这些材料例如是：在芯板中或类似物中使用的有机芯材料(有时称为预浸渍材料)，金属材料如Cu、Ni、Fe、这些金属材料的合金材料，或复合材料。
优选地，加强构件112在与其上形成有半导体芯片109的平面基本相同的平面上形成。这样，加强构件112嵌入在绝缘层103中，而不会增加绝缘层103的厚度。
根据本实施例的配线基板100可以按照半导体芯片的规格和连接的规格而形成为各种形状和厚度。配线基板的实际厚度的例子在下面进行描述。
例如，在半导体芯片109的厚度D2被设定为80μm的情况下，从半导体芯片109的上端面到阻焊层118的距离D1是20μm。从半导体芯片109的下端面到图案配线106上端的距离D3是45μm。
阻焊层118的厚度d1和阻焊层120的厚度d5的厚度都是30μm。从阻焊层120的上端面到图案配线106的下端面的距离d4是25μm。图案配线106的厚度d3是10μm。从图案配线106的上端面到阻焊层118的下端面的距离d2是145μm。
在这种情况下，配线基板(除焊料凸点121之外)的厚度等于240μm。
图2A示意性地示出了图1中所示的配线基板100的平面图。顺便指出，在图2A中，未示出除半导体芯片109和加强构件112之外的部件。如图2A所示，例如，加强构件112在半导体芯片109的周围形成，以便包围半导体芯片109。因此，更有利于防止基板的翘曲。顺便指出，可以在配线基板上安装单个或多个半导体芯片。
加强构件并不限于上述的例子。例如，加强构件的形状可以以下述各种方式进行改变。
图2B和2C示出了图2A所示的加强构件的变型。顺便指出，在图2B和2C中，用与图2A中使用的附图标记相同的附图标记来表示图2A所示的上述部件。因此，省略对这些部件的描述。加强构件可以变型为如图2B所示的加强构件112A一样，分别放置在配线基板的两侧(端部)且彼此相对。作为另外一种选择，加强构件可以变型为如图2C所示的加强构件112B一样，该加强构件112B分别放置在配线基板的角部附近且彼此相对。在图2C中，加强构件112以部分地包围多个半导体芯片的方式形成。如上所述，根据半导体芯片的大小、配线结构或配线基板的规格，可以对加强构件作出各种变型和改变。
接下来，参照图3A～3O，按步骤依次对根据本发明该实施例的图1所示的配线基板100的制造方法的示例进行说明。
首先，如图3A所示，制备厚度例如为200μm的由Cu制成的芯板101。
随后，在如图3B所示的步骤中，在芯板101上，使用通过光刻法制作的抗蚀图形作为掩膜，并且使用芯板101作为电极，通过电镀形成由例如Au/Ni制成的端子连接部102。这样，在芯板101由导电材料制成的情况下，芯板101可以用作电镀时的电极。当在随后的步骤中执行电镀时，根据需要将芯板用作电极(或用作电镀时的通电线路)。在形成端子连接部102之后，将该抗蚀图形剥离。
接着，在图3C所示的步骤中，通过例如层压或涂敷形成由树脂材料，如环氧树脂，制成的绝缘层103，例如以便覆盖端子连接部102。而且，通过使用例如激光束加工出导通孔103A，以使端子连接部露出。而且，优选地，在形成导通孔103A之后，根据需要执行去污处理，以去除导通孔103A内的残渣，并且使得绝缘层103的表面粗糙化。
接下来，在图3D所示的步骤中，通过例如无电解镀铜在绝缘层103的表面和端子连接部102的表面上形成种晶层104。
接下来，在图3E所示的步骤中，使用通过光刻法制作的抗蚀图形作为掩膜，通过例如电镀铜以形成导通塞105，以便掩盖导通孔103A。并且，要连接到导通塞105上的图案配线106与导通塞105一体地形成。在电镀电解完成之后，将抗蚀图形剥离。
接下来，在图3F所示的步骤中，通过蚀刻去除在绝缘层103上形成的种晶层104的多余部分。然后，使用在绝缘层103和图案配线106上形成的抗蚀图形作为掩膜，其中通过光刻法制作所述抗蚀图形，并通过电镀在图案配线106上形成由例如焊料制成的连接部107。
在这种情况下，优选地，在连接部107与图案配线106之间形成作为阻挡层的Ni层。在电镀完成之后，将抗蚀图形剥离。而且，在这种情况下，用于形成连接部107的方法并不限于电镀。例如，也可以使用这样的方法：将粘合材料涂敷在图案配线106上，并且涂细焊锡粉，以使焊锡粉粘在粘合材料上。
接下来，在如图3G所示的步骤中，将半导体芯片109设置(安装)在图案配线106上。在这种情况下，在半导体芯片109的电极片(未图示)上设置由例如Au制成的柱形凸点108。半导体芯片109安装在图案配线106上，使得柱形凸点108与连接部107接触。此时，对基板进行加热以进行回流焊接。这样，提高了柱形凸点108与连接部107之间连接的可靠性。
优选地，例如，在半导体芯片109与图案配线106之间的空间，或者在半导体芯片109与绝缘层103之间的空间，填充树脂材料，从而形成底部填充层110。
接着，在图3H所示的步骤中，通过例如层压形成由例如可热硬化环氧树脂或可热硬化聚酰亚胺树脂制成的绝缘层111，以便覆盖绝缘层103、图案配线106和半导体芯片109。
绝缘层111用于防止加强构件与图案配线106的接触引起在随后步骤中设置的加强构件或图案配线106受到损坏。在这种情况下，绝缘层111例如形成为具有大约25μm的厚度。
特别是，在绝缘层111是由与绝缘层103相同的材料制成的情况下，绝缘层103与111完全彼此一体地形成。因此，在该图和随后的图中，假定绝缘层103与111形成为一个绝缘层，并将包括绝缘层111的绝缘层103表示为绝缘层103。
接着，在图3I所示的步骤中，通过绝缘层103在图案配线106上设置(安装)例如厚度为100μm且由有机芯材料(预浸渍处理材料)制成的加强构件112。在这种情况下，金属材料如Cu和Ni可以用于加强构件112。作为另外一种选择，加强构件112可以由例如电镀法形成。
接下来，在图3J所示的步骤中，通过层压形成由例如可热硬化环氧树脂或可热硬化聚酰亚胺树脂制成的绝缘层113，以便覆盖加强构件112和半导体芯片109。
特别是，在绝缘层113是由与绝缘层103相同的材料制成的情况下，绝缘层103与113完全彼此一体地形成。因此，在该图和随后的图中，假定绝缘层103与113形成为一个绝缘层，并将包括绝缘层113的绝缘层103表示为绝缘层103。
接下来，在图3K所示的步骤中，通过加热绝缘层103而执行热硬化步骤(硬化步骤)。在这种情况下，加强构件112嵌入在绝缘层103中。所以，可以抑制由于温度变化而引起绝缘层103的翘曲程度，这样绝缘层103可以保持良好的平面度。
接下来，在图3L所示的步骤中，通过使用例如激光束在绝缘层103中形成延伸到图案配线106的导通孔114。而且，根据需要可以进行去污处理。然后，在包括导通孔114的内壁表面的绝缘层103以及露出的图案配线106上，通过例如无电镀铜形成种晶层115。
接下来，在图3M所示的步骤中，使用通过光刻法制作的抗蚀图形作为掩膜，通过电解镀铜形成导通塞116，以便掩盖导通孔114。并且，要连接到导通塞116的图案配线117与导通塞116一体地形成。在电镀完成之后，将抗蚀图形剥离。而且，通过蚀刻去除在绝缘层103上形成的种晶层115的多余部分。
接下来，在图3N所示的步骤中，在图案配线117和绝缘层103上形成阻焊层118，以使图案配线117的一部分露出。然后，在图案配线117露出的部分上，通过无电镀法形成由例如Ni/Au制成的端子连接部119。
接下来，在图3O所示的步骤中，通过例如蚀刻去除由例如Cu制成的芯板101。然后，如图1所示，形成阻焊层120。接着，根据需要形成焊料凸点121。从而，形成配线基板100。
在本实施例中，通过蚀刻去除由例如Cu制成的芯板101。然而，作为另外一种选择，例如通过制备在其上贴有粘性剥离带的芯板101，可以芯板101在其与绝缘层103接触的那侧设置剥离层。优选地，通过加热以降低该剥离层的粘结强度。在这种情况下，在如图3O所示的从绝缘层103去除芯板101的步骤中，通过用例如烘箱对整个配线基板进行加热，以从剥离层剥离绝缘层103。
根据本实施例的制造方法，在图3I所示的步骤中设置加强构件112。然后，在图3K所示的步骤中，在其中嵌入加强构件112的绝缘层103上进行硬化处理。这样，在随后的步骤中，获得了抑制绝缘层103或整个配线基板的翘曲程度的优点。特别是，与现有技术的方法相比，可以更有效地抑制由于温度的升高/下降使应力变化而引起的翘曲程度，以及可以更有效地抑制由于电镀、去污处理、层压处理等使应力变化而引起的翘曲程度。因此，可以形成平面度高且具有高可靠性的配线基板。
另外，在本实施例中，例如，在预定的制造过程中，在由例如Cu制成的芯板101上形成配线基板100。因此，抑制了制造过程中的翘曲程度。而且，在预定制造过程完成之后去除芯板101。从而，可以减小配线基板的厚度。
第二实施例
根据本发明的配线基板并不限于上述实施例。例如，可以对配线结构或加强构件进行各种方式的变型或改变。
例如，图4示意性地示出了作为配线基板100的变型的配线基板200。
参照图4，在图中所示的配线基板200中，绝缘层203、端子连接部202和219、半导体芯片209、柱形凸点208、连接部207、底部填充层210、阻焊层218和220以及加强构件212分别相当于图1所示的绝缘层103、端子连接部102和119、半导体芯片109、柱形凸点108、连接部107、底部填充层110、阻焊层118和120以及加强构件112。，配线基板200具有类似于配线基板100的结构。
在配线基板200的情况下，与配线基板100相比，增加了多个与半导体芯片209连接的配线结构的层。例如，配线基板100总共具有两层配线，其中一层设置在半导体芯片的下侧，而另一层设置在半导体芯片的上侧。配线基板200总共具有四层配线，其中两层设置在半导体芯片的下侧，而其余两层设置在半导体芯片的上侧。
在配线基板200的情况下，导通塞205和216与图案配线206连接，半导体芯片连接到该图案配线206上。此外，导通塞205与图案配线223连接，并且图案配线223与在其上形成端子连接部202的导通塞222连接。另一方面，图案配线217与导通塞216连接。图案配线217经由导通塞224与在其上形成端子连接部219的图案配线225连接。
这样，可以根据需要改变配线的层数。
根据半导体芯片的规格和连接的规格，配线基板200可以以各种形状、厚度形成。配线基板的实际厚度的例子在下面进行描述。
例如，在半导体芯片209的厚度D5被设定为80μm的情况下，从半导体芯片209的上端面到图案配线217的距离D4是20μm。从半导体芯片209的下端面到图案配线206的上端面的距离D6是45μm。
阻焊层218的厚度d6和阻焊层220的厚度d12的厚度都是30μm。从阻焊层220的上端面到图案配线223的下端面的距离d11是25μm。从图案配线223的下端面到图案配线206的下端面的距离d10是25μm。图案配线206的厚度d9是10μm。从图案配线206的上端面到图案配线217的下端面的距离d8是145μm。从图案配线217的下端面到阻焊层218的下端面的距离d7是25μm。
在这种情况下，配线基板200的厚度(除焊料凸点221之外)等于290μm。
图5示意性地示出作为配线基板100的另一个变型的配线基板200A。顺便说明，在该图中，用相同的附图标记表示上述部件。因而省略了对这些部件的描述。
参照图5，在图中所示的配线基板200A中，相当于加强构件212的加强构件212A同样也在半导体芯片209的附近形成。加强构件212A的总面积大于加强构件212的总面积。
在这种情况下，在加强构件212A中形成用于形成导通塞216的孔部。
这样，根据需要可以对加强构件和配线结构作出各种变型和改变。
在上述实施例中，加强构件安装在正面朝下型(倒装芯片型)配线基板中以抑制配线基板的翘曲。然而，作为另外一种选择，加强构件也可以安装在正面朝上型配线基板中。而且，通过将加强构件安装在其中嵌入半导体芯片的绝缘层内，可以有效地抑制正面朝上型配线基板的翘曲，而几乎不增加正面朝上型配线基板的厚度。
虽然已参照具体实施例对本发明进行了描述，但只要不脱离所附权利要求书中描述的本发明的精神和范围的情况下，本领域的技术人员可以对本发明作出各种变型和改变。
根据本发明，能够减小结合了半导体芯片的配线基板的厚度，并且也可以抑制这种配线基板的翘曲。
本申请基于2005年3月15日提交的日本专利申请No.2005-073946，并要求该申请的外国优先权，所述日本专利申请的全部内容以引用的方式并入本文。

Claims (17)

1.一种配线基板，包括：
至少一个半导体芯片；
绝缘层，其中嵌入所述至少一个半导体芯片；
配线结构，其与所述至少一个半导体芯片连接；以及
至少一个加强构件，其用于加强所述绝缘层，并且所述加强构件嵌入在所述绝缘层中，
其中，所述配线结构包括：
第一配线子结构，其在所述半导体芯片的第一侧形成；以及
第二配线子结构，其在所述半导体芯片的第二侧形成，
所述第一配线子结构和所述第二配线子结构通过在所述绝缘层中形成的导通塞连接。
2.根据权利要求1所述的配线基板，其中，
所述加强构件与所述半导体芯片安装在相同的平面上。
3.根据权利要求1所述的配线基板，其中，
所述加强构件形成为包围所述半导体芯片。
4.根据权利要求1所述的配线基板，其中，
所述至少一个加强构件包括多个加强构件，并且
所述多个加强构件在所述配线基板的两个端部上形成。
5.根据权利要求1所述的配线基板，其中，
所述至少一个加强构件包括多个加强构件，并且
所述多个加强构件在所述配线基板的角部附近形成。
6.根据权利要求1所述的配线基板，其中，
所述配线结构具有多层配线结构。
7.根据权利要求1所述的配线基板，其中，
所述加强构件由有机芯材料或金属材料制成。
8.一种配线基板，包括：
至少一个半导体芯片；
绝缘层，其中嵌入所述至少一个半导体芯片；
配线结构，其与所述至少一个半导体芯片连接；
至少一个加强构件，其用于加强所述绝缘层，并且所述加强构件嵌入在所述绝缘层中；
第一端子连接部，其在所述配线基板的第一表面上形成，所述第一端子连接部通过所述配线结构与所述半导体芯片连接；以及
第二端子连接部，其在所述配线基板的第二表面上形成，所述第二端子连接部通过所述配线结构与所述半导体芯片连接。
9.一种制造配线基板的方法，所述方法包括：
形成下层配线结构；
将至少一个半导体芯片安装在所述下层配线结构上，并且将所述至少一个半导体芯片与所述下层配线结构连接；
形成至少一个加强构件；以及
形成绝缘层，以便将所述半导体芯片和所述加强构件嵌入在所述绝缘层中，所述加强构件用于加强所述绝缘层。
10.根据权利要求9所述的制造配线基板的方法，其中，
所述加强构件与所述半导体芯片安装在相同的平面上。
11.根据权利要求9所述的制造配线基板的方法，还包括：
在所述绝缘层中形成导通塞，并将导通塞与下层配线结构连接；以及
形成上层配线结构，以使所述半导体芯片安装在所述下层配线结构与所述上层配线结构之间，并且将所述上层配线结构与所述导通塞连接。
12.根据权利要求9所述的制造配线基板的方法，其中，
所述下层配线结构形成在芯板上，并且所述方法还包括：
去除所述芯板。
13.根据权利要求12所述的制造配线基板的方法，其中，
所述芯板由导电材料制成，并且形成所述下层配线结构的步骤包括：
通过使用所述芯板作为电极的电镀形成下层配线结构。
14.根据权利要求9所述的制造配线基板的方法，其中，
所述半导体芯片通过在半导体芯片上形成的柱形凸点电连接到所述下层配线结构上。
15.根据权利要求14所述的制造配线基板的方法，还包括：
在所述柱形凸点与下层配线结构之间形成由焊料制成的连接部。
16.根据权利要求9所述的制造配线基板的方法，其中，
形成所述绝缘层的步骤包括：
形成第一绝缘层，以便覆盖所述半导体芯片和所述下层配线结构；以及
形成第二绝缘层，以便覆盖所述半导体芯片和所述加强构件，所述加强构件在所述第一绝缘层上形成。
17.根据权利要求16所述的制造配线基板的方法，还包括：
通过加热使所述第一绝缘层和所述第二绝缘层硬化，其中，
所述第一绝缘层和所述第二绝缘层由热硬化树脂材料制成。
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