WO2005074340A1 - 多層プリント配線板及びその製造方法 - Google Patents
多層プリント配線板及びその製造方法 Download PDFInfo
- Publication number
- WO2005074340A1 WO2005074340A1 PCT/JP2005/001628 JP2005001628W WO2005074340A1 WO 2005074340 A1 WO2005074340 A1 WO 2005074340A1 JP 2005001628 W JP2005001628 W JP 2005001628W WO 2005074340 A1 WO2005074340 A1 WO 2005074340A1
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- WIPO (PCT)
- Prior art keywords
- conductor
- printed wiring
- wiring board
- layer
- multilayer printed
- Prior art date
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49128—Assembling formed circuit to base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49204—Contact or terminal manufacturing
Definitions
- the present invention relates to a multilayer printed wiring board and a method for manufacturing the same.
- a multilayer printed wiring board As a form of mounting semiconductor chips used in these electronic devices on a multilayer printed wiring board at a high density, a flip chip method in which a semiconductor chip is directly surface-mounted on a multilayer printed wiring board is adopted.
- a multilayer printed wiring board includes a core substrate, a build-up layer formed on the core substrate, and mounting electrodes on which a semiconductor chip is mounted via solder bumps on the upper surface of the build-up layer.
- the core substrate epoxy resin, BT (bismaleimide / triazine) resin, polyimide resin, polybutylene resin, phenol resin, and the like, which are molded together with a reinforcing material such as glass fiber, are used.
- the thermal expansion coefficient of the core substrate is about 12 to 20 ppm / ° C (30 to 200 ° C), compared to the thermal expansion coefficient of silicon (about 3.5 ppm / ° C) for semiconductor chips. Then it is about four times larger. Therefore, in the above-described flip-chip method, when the temperature change due to the heat generation of the semiconductor chip repeatedly occurs, the solder bumps and the semiconductor chip may be changed due to the difference in the amount of thermal expansion and contraction between the semiconductor chip and the core substrate. There was a possibility that the insulating layer of the above was destroyed.
- a low modulus stress relief on the build-up layer There has been proposed a multilayer printed wiring board in which a mounting layer is provided, a mounting electrode is provided on an upper surface of the stress relaxation layer, and a conductive pattern on the build-up layer and the mounting electrode are connected by a conductive boss (Japanese Patent Application Laid-Open No. Sho. 8-284884, JP-A-2001-36653).
- a low elastic modulus layer 140 is laminated on the upper surface of the build-up layer 130, as shown in FIG.
- a multilayer printed wiring board 100 in which the conductor pattern 1 32 on the upper surface of 130 and the mounting electrode 1 42 formed on the upper surface of the low elastic modulus layer 140 are connected via holes 150 is disclosed. Have been. Disclosure of the invention
- the present invention has been made to solve such a problem, and a multilayer print that can prevent connection breakdown with an electronic component due to thermal expansion and thermal contraction and can stably supply power to the electronic component.
- the purpose is to provide a wiring board. It is another object of the present invention to provide a method for manufacturing such a multilayer printed wiring board.
- the present inventors have conducted intensive studies and found that the conventional multilayer printed wiring board has a small aspect ratio, that is, a height / diameter of a via hole penetrating through a low-modulus layer (for example, see Japanese Patent Application Laid-Open No. 2000-200).
- a low-modulus layer for example, see Japanese Patent Application Laid-Open No. 2000-200.
- the low elastic modulus layer was not deformed, stress was concentrated on the solder bumps, and it was found that a defect occurred, and the present invention was completed. Reached.
- the present invention The following measures were taken in order to achieve the above object.
- the multilayer printed wiring board of the present invention comprises: a core substrate; a build-up layer formed on the core substrate and provided with a conductor pattern on an upper surface; and a low elastic modulus formed on the build-up layer.
- a mounting electrode provided on an upper surface of the low elastic modulus layer and connected to an electronic component via a connection portion; and electrically connecting the mounting electrode and the conductor pattern through the low elastic modulus layer.
- a conductor post connected to the printed circuit board, wherein the conductor post has an aspect ratio R as ⁇ of 4 ⁇ R asp ⁇ 20.
- the conductor boss has an aspect ratio R asp of 4 ⁇ R asp 220, so even if stress is generated due to the difference in thermal expansion coefficient between the core board and the electronic component, The stress can be surely alleviated, and connection destruction with electronic components due to thermal expansion and thermal contraction can be prevented. In addition, the rate of change in electric resistance when heating and cooling are repeated can be suppressed to a small value, and power can be stably supplied to the mounted electronic components. It is presumed that such an effect is obtained because the conductor post is deformed in accordance with the low elastic modulus layer because the aspect ratio R asp of the conductor post is large.
- the aspect ratio R asp of the conductor post refers to the height of the conductor post / the diameter of the conductor post (the minimum diameter when the diameter is not uniform).
- the aspect ratio R asp of the conductor post when the aspect ratio R asp of the conductor post is less than 4, the electrical resistance changes greatly when heating and cooling are repeated, which is not preferable. In some cases, cracks may occur in the conductor boss. In other words, if the aspect ratio R asp is less than 4, the conductor boss is not deformed and hinders the deformation of the low elasticity layer. If it is 20 or more, the conductor bost is undesirably deformed excessively, causing fatigue rupture. This Ask The ratio R asp is preferably 4 ⁇ R asp ⁇ 6.5.
- the conductor post preferably has a diameter exceeding 30 ° ⁇ . In this way, a voltage drop when power is supplied to the mounted electronic component can be suppressed, and malfunction of the electronic component can be prevented. Also, the electrical resistance of the conductor post can be kept low.
- the electronic component is an IC chip of 1 GHz or less, a voltage drop hardly occurs even if the conductor bost is set to 30 or less, but in a high-speed IC chip of 3 GHz or more, the voltage drop is small. Since it becomes remarkable, it is preferable that the diameter of the conductor post exceeds 30 xm.
- the diameter of the thinnest portion exceeds 30 m. This is because the conductor resistance of the conductor post decreases and the fatigue deterioration resistance / heat cycle resistance improves.
- the diameter of the conductor bost is preferably more than 30 m and not more than 60 im.
- the conductor post may be formed in a shape having cracks. By doing so, the rate of change in electrical resistance when heating and cooling are repeated can be further suppressed, as compared with a substantially straight conductor bost. This is because the conductor post is deformed around the cupile (starting point) according to the low-modulus layer.
- a crack is a portion that is thinner than the upper and lower portions when the conductor bost is viewed along the axial direction. In the conductor post having such a crack, it is preferable that the diameter of the thickest part (the thickest part and the thinnest part) is 2 or more with respect to the diameter of the thinnest part of the conductor bost.
- the mounting electrode may be a top of the conductor boss formed so as to be substantially flush with an upper surface of the low elasticity layer. In this way, the mounting electrodes are formed separately from the conductor posts. It can be manufactured more easily than in the case of
- the low elastic modulus layer preferably has a Young's modulus at 30 ° C. of 1 OMPa to 1 GPa. This makes it possible to more surely alleviate the stress caused by the difference in thermal expansion coefficient. Further, the low elastic modulus layer has a Young's modulus at 30 ° C. of preferably 1 OMPa to 30 OMPa, most preferably 10 MPa to 10 OMPa.
- the conductor post is preferably formed of a material having good conductivity, and is preferably formed of, for example, copper, solder, or an alloy containing any of these.
- a method for manufacturing a multilayer printed wiring board having a conductor boss having a cracked shape among the multilayer printed wiring boards of the present invention includes:
- the conductor bost can be formed into a shape having cracks.
- the relationship between the etching time and the shape of the conductor boss may be appropriately set by conducting experiments in advance according to the type of the etching solution and the material of the conductor boss.
- FIG. 1 is a cross-sectional view of the multilayer printed wiring board of the present embodiment
- FIG. 2 is a cross-sectional view of the multi-layer printed wiring board of the present embodiment in the process of being manufactured
- FIG. 3 is a cross-sectional view of the multi-layer printed wiring board of the present embodiment in the process of being manufactured
- FIG. FIG. 5 is a cross-sectional view illustrating the process of forming the multilayer printed wiring board of the present embodiment
- FIG. 6 is a cross-sectional view illustrating the process of forming the multilayer printed wiring board of the present embodiment.
- FIG. 8 is a cross-sectional view of the multi-layer printed wiring board of the embodiment in the process of being manufactured
- FIG. 8 is a cross-sectional view of the multi-layer printed wiring board of the present embodiment in the process of manufacturing
- FIG. 9 shows the relationship between the shape of the conductor bost and the rate of change in electrical resistance.
- Figure 10 is a table and graph showing the relationship between the minimum diameter of the conductor bost and the amount of voltage drop.
- FIG. 11 is a table and graph showing the relationship between the conductor bost's aspect ratio and stress ratio
- FIG. 12 is a cross-sectional view of a conventional multilayer printed wiring board
- Figure 13 is a table showing the relationship between the shape of the conductor boss and the rate of change in electrical resistance.
- FIG. 1 is a cross-sectional view of a multilayer printed wiring board according to one embodiment of the present invention. Note that the terms “up” and “down” are used below, but this is only a convenient expression of the relative positional relationship. Or you may.
- the multilayer printed wiring board 10 of the present embodiment is configured such that wiring patterns 22 formed on both upper and lower surfaces are connected to each other through through-hole conductors 24.
- solder bump 66 Electrode for mounting
- the core substrate 20 is made of a wiring pattern 22, 22 made of copper on both upper and lower surfaces of a core substrate body 21 made of BT (bismaleimide-triazine) resin or glass epoxy resin, and a top and bottom of the core substrate body 21. And a through-hole conductor 24 made of copper formed on the inner peripheral surface of the through hole penetrating therethrough. Both wiring patterns 22 and 22 are electrically connected through the through-hole conductor 24. I have.
- the build-up layer 30 is formed by alternately laminating a resin insulation layer 36 and a conductor pattern 32 on both the upper and lower surfaces of the core substrate 20, and includes a wiring pattern 22 of the core substrate 20 and a build-up layer 30. Electrical connection with the conductor pattern 32 The electrical connection between the conductor patterns 32 and 32 in the build-up layer 30 is ensured by via holes 34 penetrating above and below the resin insulation layer 36. I have.
- Such a build-up layer 30 is formed by a well-known subtractive method or an additive method (including a semi-additive method and a full-additive method). Specifically, for example, it is formed as follows.
- a resin sheet to be the resin insulating layer 36 is attached to the upper and lower surfaces of the core substrate 20.
- This resin sheet is formed of a modified epoxy resin sheet, a polyphenylene ether resin sheet, a polyimide resin sheet, a cyanoester resin sheet, etc., and has a thickness of about 20 to 8 0 m, and the Young's modulus at room temperature is 2 to 7 GPa.
- An inorganic filler may be dispersed in this resin sheet.
- a thermosetting resin film product name: ABF-45SH, Young's modulus: 3.O GPa manufactured by Ajinomoto Co. was used.
- through holes are formed in the attached resin sheet using a carbon dioxide gas laser, a UV laser, a YAG laser, an excimer laser, or the like.
- electroless copper plating is performed, a resist is formed on the electroless copper plating layer, and exposure and development are performed.
- the wiring pattern 32 is formed by etching the portion of the electroless copper plating where the resist was present with an etching solution of a sulfuric acid / hydrogen peroxide system.
- the conductor layer inside the through hole becomes the via hole 34.
- the build-up layer 30 is formed by repeating this procedure.
- the low elastic modulus layer 40 is an elastic material having a Young's modulus at 30 ° C. of 10 to 100 MPa (preferably 10 to 300 MPa, more preferably 10 to 100 MPa). It is formed with. If the Young's modulus of the low elastic modulus layer 40 is in this range, it is caused by a difference in thermal expansion coefficient between the semiconductor chip 70 electrically connected to the land 52 via the solder bump 66 and the core substrate 20. Even if stress is generated, it can be relieved.
- the elastic material used for the low elastic modulus layer 40 include thermosetting resins such as epoxy resin, imide resin, phenol resin, and silicone resin, polyolefin resin, vinyl resin, and imide resin.
- thermoplastic resins mentioned above those which have a rubber component such as polybutadiene, silicone rubber, urethane, SBR, NBR, or an inorganic component such as silica, alumina, or zirconia dispersed in the thermoplastic resin, etc. .
- the components dispersed in the resin may be one type or two or more types, and both the rubber component and the inorganic component may be dispersed.
- thermosetting resin dicyandiamide or the like
- a curing agent may be dispersed.
- a resin in which a urethane resin is dispersed by 60% by 1% in an epoxy resin in which a curing agent is dispersed is used as the elastic material of the low elastic modulus layer 40.
- the conductor bost 50 is formed mainly of copper so as to penetrate the low elasticity layer 40 in the vertical direction, and electrically connects the land 52 to the conductor pattern 32 provided on the upper surface of the build-up layer 30. Connected.
- the conductor boss 50 is formed in a shape having cracks, specifically, a shape in which the diameter of the middle part is smaller than the diameter of the upper part and the diameter of the lower part. In this embodiment, the diameter of the upper part is 80 m, the diameter of the lower part is 80 im, the diameter of the middle part is 35 m, and the height is 200 m. Therefore, the conductor post 50 has an aspect ratio R asp which is the ratio of the height of the conductor post to the diameter of the narrowest middle part. Is 2.3.
- the land 52 is the top of each conductor post 50 exposed from the low elastic modulus layer 40.
- the lands 52 are connected to the electrode portions of the semiconductor chip 70 via the solder bumps 66 after nickel plating and gold plating are performed in this order.
- FIG. 2 is a partial cross-sectional view of the build-up layer 30 formed on the upper surface of the core substrate 20.
- the surface of the uppermost resin insulating layer 36 is still covered with the electroless copper plating layer 304. That is, the electroless copper plating is applied to the resin insulating layer 36 after the formation of the through hole, and the electroless copper plating layer 304 After the photoresist is formed and patterned, a portion where the photoresist is not formed is subjected to electrolytic copper plating to form an electroless copper plating layer 304 and an electrolytic copper plating layer, Thereafter, the photoresist is stripped.
- the electrolytic copper plating layer is patterned to form a patterned plating layer 302, but the electroless copper plating layer 304 remains.
- the thickness of the electroless copper plating layer 304 is several im.
- a dry film 303 (CX—A240 made by Asahi Kasei Corporation, thickness of 240 m) is stuck, and it is put in place.
- An opening 308 of ⁇ 120 zm is formed by a carbon dioxide laser (see Fig. 3).
- the substrate in the middle of the preparation was subjected to electrolytic copper plating from the bottom of the opening 308 of the dry film 306 so as to fill the opening 308 with the columnar copper layer 310 and further fill the opening.
- the solder layer 312 is formed on the upper surface of the copper layer 310 (see FIG. 4).
- the electrolytic copper plating solution having the following composition was used. Sulfuric acid 2.24 mo 1 / copper sulfate 0.26 mo 1 Z1, additive 19.5 m 1/1 (Atotech Japan Co., Capparaside GL).
- the electrolytic copper plating was performed under the following conditions. Current density l A / dm 2, time 1 7 hours, temperature 2 2 ⁇ 2 ° (:.
- etching was performed by immersing the substrate being formed in an ammonia alkali etching solution (trade name: A-Process, manufactured by Meltex Co., Ltd.). This etching removes the portion of the electroless copper plating layer 304 that was covered with the dry film 303, that is, the portion that was not covered with the electrolytic copper plating layer 302, and removed the columnar copper layer. The middle part of 310 was eroded, resulting in a shape with cracks (see Fig. 5).
- the solder layer 312 functions as an etching resist.
- how much the middle portion of the copper layer 310 is eroded can be controlled by the etching time. For example, if the etching time is 10 to 60 seconds, the maximum diameter (upper or lower diameter) of the copper layer 310 is 60 to 120 / im, and the diameter of the middle part is 30 to 60 Aim. However, the maximum diameter and the diameter of the intermediate portion can be set to other sizes by changing the diameter of the opening 308.
- solder layer 312 is immersed in a solder release agent (trade name: Enstrip TL-106, manufactured by Meltex Co., Ltd.) and removed.
- Laminate resin film 3 16 500MPa) with 1% dispersion of 60 V o (see Fig. 6), cure at 150 ° C for 60 minutes, and then grind until the surface of conductor post 50 is exposed ( See Figure 7).
- the polished resin film 316 becomes the low elastic modulus layer 40.
- the top of the conductor post 50 exposed from the low elastic modulus layer 40 becomes the land 52.
- the height of the conductor bost 50 was 200 m.
- the substrate in the process of immersion is immersed in an acidic solution containing a palladium catalyst that activates the copper surface, and then nickel chloride 30 gZl, sodium hypophosphite 10 g / l, sodium citrate l O gZl
- the lands 52 were immersed in an electroless nickel plating solution having a pH of 5 for 20 minutes to form a nickel plating layer having a thickness of 5 m on the lands 52.
- the substrate was placed in an electroless plating solution consisting of 2 gZ1 of gold cyanide, 75 g / 1 of ammonium chloride, 50 gZ1 of sodium citrate, and lOg / 1 of sodium hypophosphite. It was immersed at 23 ° C.
- solder paste was printed and reflowed at 200 ° C. to form solder bumps 66 on the lands 52 to produce a multilayer printed wiring board 10 (see FIGS. 8 and 1).
- the thermal expansion coefficient difference between the core substrate 20 and the semiconductor chip 70 is different. Even if a stress caused by the semiconductor chip is generated, the stress can be surely relieved, so that the connection breakdown with the semiconductor chip 70 and the breakdown of the insulating layer of the semiconductor chip 70 due to thermal expansion and thermal contraction can be prevented. In addition, since the rate of change in electrical resistance when heating and cooling are repeated can be suppressed to a small value, power can be stably supplied to the semiconductor chip 70.
- the conductor post 50 since the diameter of the narrowest part of the conductor post 50 exceeds 30 m, a voltage drop when power is supplied to the semiconductor chip 70 can be suppressed, and the semiconductor chip 70 may malfunction. Can be prevented. This effect is particularly remarkable when an IC chip 70 of 3 GHz or more is mounted. Further, since the conductor post 50 is formed in a shape having a crack, and the diameter of the thickest portion (the thickest portion Z the thinnest portion) with respect to the diameter of the thinnest portion is 2 or more, the conductor post 50 has a substantially straight shape. The rate of change in electrical resistance when heating and cooling are repeated can be further suppressed compared to bost. This is because the low-modulus layer 40 and the conductor post 50 are deformed together.
- the land 52 since the top of the conductor post 50 formed so as to be flush with the upper surface of the low elastic modulus layer 40 is used as the land 52, the land is separate from the conductor post 50. It can be easily manufactured as compared with the case of forming a. Further, since the low modulus layer 40 has a Young's modulus at 30 ° C of 1 OMPa to 1 GPa, it is possible to more reliably relieve the stress caused by the difference in thermal expansion coefficient.
- the shape of the conductor post 50 is a shape having a crack, but may be a substantially straight columnar shape.
- etching may be performed by spraying an etching solution linearly with a slit nozzle or the like. If the aspect ratio R asp of 0 is 4 ⁇ R asp ⁇ 20, the connection breakdown with the semiconductor chip 70 due to thermal expansion and thermal contraction can be prevented and the semiconductor chip can be prevented, as in the above-described embodiment. 70 malfunctions can be prevented.
- the diameter of the cross section of the conductor post 50 exceeds 30 m, since the amount of voltage drop can be suppressed low. However, if it exceeds 80 x m, the conductor posts 50 may hinder the deformation of the low elastic modulus layer 40. Therefore, it is more than 30 // m but more preferably 80 m or less. These have also been demonstrated as described in the experimental examples described below.
- a solder resist layer may be formed on the low elastic modulus layer 40 of the above-described embodiment.
- an opening is provided in the solder resist layer so that the land 52 is exposed to the outside.
- solder resist layer can be formed by an ordinary method.
- the land 52 is the top of the conductor post 50, that is, a part of the conductor post 50.
- the land 52 may be separate from the conductor post 50.
- Those having the same minimum diameter and maximum diameter are substantially straight pillar-shaped conductor posts, and those having different minimum and maximum diameters are conductor posts having cracks.
- Spray etching using a slit nozzle was adopted for the straight conductor bost.
- An IC chip was mounted on the multilayer printed wiring board of each example manufactured in this manner, and then a sealing resin was filled between the IC chip and the multilayer printed wiring board to obtain an IC mounting board. Then, the electric resistance of the specific circuit via the IC chip (the electric resistance between a pair of electrodes exposed on the surface of the IC mounting substrate opposite to the surface on which the IC chip is mounted and electrically connected to the IC chip) is measured. The value was set as the initial value.
- the target specification was set so that the rate of change at the 100th cycle was within ⁇ 10% (that is, “normal” and “good” in the evaluation).
- the aspect ratio R asp was 4 or more
- the evaluation was “good” until at least the 100th cycle
- the aspect ratio R asp was Below 3.3
- the evaluation was almost “poor”.
- the aspect ratio R asp was 20
- cracks occurred in the conductor boss and the conductor was broken.
- the aspect ratio R asp of the conductor post was the same, the shape having cracks was better than the almost straight shape.
- the multilayer printed wiring boards of Experimental Examples 13 to 18 shown in the table of FIG. 10 were manufactured according to the above-described embodiment. Specifically, in each experimental example, the hole diameter of the opening 308 formed using a carbon dioxide laser in the dry film 306 (thickness 240 m) in Fig. The etching time of the copper layer 310 in FIG. 5 was set in accordance with the minimum diameter of the conductor post. A voltage drop when starting this IC chip by supplying a fixed amount of power by mounting an IC chip driven at 3.1 GHz at high speed on the multilayer printed wiring board of each embodiment fabricated in this way. The amount was measured.
- the stress ratio greatly changes when the aspect ratio Rasp is 4 or more. That is, the stress ratio is small when the aspect ratio R asp is 4 or more, but becomes large when the aspect ratio R asp is less than 4.
- the conductor boss having the same minimum diameter and the maximum diameter is a substantially straight pillar-shaped conductor boss, and the conductor boss having the minimum diameter and the maximum diameter different from each other is a conductor boss having a crack.
- Spray etching using a slit nozzle was adopted for the straight conductor post.
- An IC chip was mounted on the multilayer printed wiring board of each example manufactured in this manner, and then a sealing resin was filled between the IC chip and the multilayer printed wiring board to obtain an IC mounting board. Then, the same heat cycle test as in Examples 1 to 18 described above was performed. However, the electrical resistance was also measured and evaluated at the 1750th cycle, the 20000th cycle, and the 2500th cycle.
- the shape of the cracked shape is evaluated as “normal” at least up to 150 cycles. Or, while the shape was straight, the straight shape was evaluated as “normal” or “good” for at least 100 cycles, and the evaluation was “bad” or “normal” for 150 cycles. Was. This is presumed to be because the cracked shape is more likely to deform together with the low modulus layer around the cracked portion.
- the minimum diameter of the conductor post a preferable result was obtained when the minimum diameter was more than 30 / im and not more than 60 zzm.
- the resin insulation layer used to form the build-up layer instead of the low modulus layer, the resin insulation layer used to form the build-up layer
- the multilayer printed wiring board of the present invention is used for mounting a semiconductor element such as an IC chip, and is used in, for example, an electric-related industry and a communication-related industry.
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
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EP05704388A EP1677585A4 (en) | 2004-01-30 | 2005-01-28 | MULTILAYER PCB AND MANUFACTURING METHOD THEREFOR |
JP2005517576A JP4504925B2 (ja) | 2004-01-30 | 2005-01-28 | 多層プリント配線板及びその製造方法 |
US11/397,802 US7754978B2 (en) | 2004-01-30 | 2006-04-05 | Multilayer printed wiring board and method of manufacturing the same |
US12/652,255 US7971354B2 (en) | 2004-01-30 | 2010-01-05 | Method of manufacturing a multilayer printed wiring board |
Applications Claiming Priority (4)
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JP2004-023271 | 2004-01-30 | ||
JP2004023271 | 2004-01-30 | ||
JP2004-139862 | 2004-05-10 | ||
JP2004139862 | 2004-05-10 |
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US11/397,802 Continuation US7754978B2 (en) | 2004-01-30 | 2006-04-05 | Multilayer printed wiring board and method of manufacturing the same |
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WO2005074340A1 true WO2005074340A1 (ja) | 2005-08-11 |
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PCT/JP2005/001628 WO2005074340A1 (ja) | 2004-01-30 | 2005-01-28 | 多層プリント配線板及びその製造方法 |
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US (2) | US7754978B2 (ja) |
EP (1) | EP1677585A4 (ja) |
JP (1) | JP4504925B2 (ja) |
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TW (1) | TW200531610A (ja) |
WO (1) | WO2005074340A1 (ja) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1705972A4 (en) * | 2004-04-28 | 2010-05-19 | Ibiden Co Ltd | MULTILAYER CONDUCTOR PLATE |
JP4846572B2 (ja) * | 2004-05-27 | 2011-12-28 | イビデン株式会社 | 多層プリント配線板 |
JP4824397B2 (ja) * | 2005-12-27 | 2011-11-30 | イビデン株式会社 | 多層プリント配線板 |
US7462784B2 (en) * | 2006-05-02 | 2008-12-09 | Ibiden Co., Ltd. | Heat resistant substrate incorporated circuit wiring board |
GB2444775B (en) | 2006-12-13 | 2011-06-08 | Cambridge Silicon Radio Ltd | Chip mounting |
US8455766B2 (en) * | 2007-08-08 | 2013-06-04 | Ibiden Co., Ltd. | Substrate with low-elasticity layer and low-thermal-expansion layer |
US8829355B2 (en) * | 2009-03-27 | 2014-09-09 | Ibiden Co., Ltd. | Multilayer printed wiring board |
US9312230B2 (en) | 2010-02-08 | 2016-04-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Conductive pillar structure for semiconductor substrate and method of manufacture |
US9059187B2 (en) * | 2010-09-30 | 2015-06-16 | Ibiden Co., Ltd. | Electronic component having encapsulated wiring board and method for manufacturing the same |
US20120090883A1 (en) * | 2010-10-13 | 2012-04-19 | Qualcomm Incorporated | Method and Apparatus for Improving Substrate Warpage |
US9368439B2 (en) * | 2012-11-05 | 2016-06-14 | Nvidia Corporation | Substrate build up layer to achieve both finer design rule and better package coplanarity |
US20150195912A1 (en) | 2014-01-08 | 2015-07-09 | Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. | Substrates With Ultra Fine Pitch Flip Chip Bumps |
US10090267B2 (en) * | 2014-03-13 | 2018-10-02 | Taiwan Semiconductor Manufacturing Co., Ltd | Bump structure and method for forming the same |
WO2017159386A1 (ja) * | 2016-03-18 | 2017-09-21 | 株式会社村田製作所 | 実装構造体、及び、積層コンデンサ内蔵基板 |
US11101203B2 (en) * | 2019-07-31 | 2021-08-24 | Advanced Semiconductor Engineering, Inc. | Wiring structure comprising intermediate layer including a plurality of sub-layers |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001036253A (ja) | 1999-07-26 | 2001-02-09 | Shinko Electric Ind Co Ltd | 多層配線回路基板及びその製造方法 |
JP2001085802A (ja) * | 1999-09-16 | 2001-03-30 | Hitachi Cable Ltd | 配線基板及びそれを用いた電子装置及びその製造方法 |
JP2001298272A (ja) * | 2000-04-13 | 2001-10-26 | Nec Corp | プリント基板 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2097998B (en) * | 1981-05-06 | 1985-05-30 | Standard Telephones Cables Ltd | Mounting of integrated circuits |
US5116459A (en) * | 1991-03-06 | 1992-05-26 | International Business Machines Corporation | Processes for electrically conductive decals filled with organic insulator material |
JPH0547842A (ja) * | 1991-08-21 | 1993-02-26 | Hitachi Ltd | 半導体装置 |
JP3428070B2 (ja) | 1993-06-07 | 2003-07-22 | 株式会社東芝 | 印刷配線板の製造方法 |
DE69634597T2 (de) * | 1995-11-17 | 2006-02-09 | Kabushiki Kaisha Toshiba, Kawasaki | Mehrschichtige leiterplatte, vorgefertigtes material für diese leiterplatte, verfahren zur herstellung einer mehrschichtigen leiterplatte, packung elektronischer bauelemente und verfahren zur herstellung vertikaler, elektrisch leitender verbindungen |
JPH10270496A (ja) * | 1997-03-27 | 1998-10-09 | Hitachi Ltd | 電子装置、情報処理装置、半導体装置並びに半導体チップの実装方法 |
JP3057156B2 (ja) * | 1998-10-08 | 2000-06-26 | 日本特殊陶業株式会社 | 配線基板とその製造方法 |
JP3865989B2 (ja) * | 2000-01-13 | 2007-01-10 | 新光電気工業株式会社 | 多層配線基板、配線基板、多層配線基板の製造方法、配線基板の製造方法、及び半導体装置 |
US6729023B2 (en) * | 2000-05-26 | 2004-05-04 | Visteon Global Technologies, Inc. | Method for making a multi-layer circuit board assembly having air bridges supported by polymeric material |
JP2003008228A (ja) * | 2001-06-22 | 2003-01-10 | Ibiden Co Ltd | 多層プリント配線板およびその製造方法 |
US20030034565A1 (en) * | 2001-08-18 | 2003-02-20 | Lan James Jaen-Don | Flip chip substrate with metal columns |
EP1705972A4 (en) * | 2004-04-28 | 2010-05-19 | Ibiden Co Ltd | MULTILAYER CONDUCTOR PLATE |
-
2005
- 2005-01-28 EP EP05704388A patent/EP1677585A4/en not_active Withdrawn
- 2005-01-28 TW TW094102771A patent/TW200531610A/zh not_active IP Right Cessation
- 2005-01-28 JP JP2005517576A patent/JP4504925B2/ja not_active Expired - Fee Related
- 2005-01-28 KR KR1020067007948A patent/KR100942400B1/ko not_active IP Right Cessation
- 2005-01-28 WO PCT/JP2005/001628 patent/WO2005074340A1/ja not_active Application Discontinuation
-
2006
- 2006-04-05 US US11/397,802 patent/US7754978B2/en active Active
-
2010
- 2010-01-05 US US12/652,255 patent/US7971354B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001036253A (ja) | 1999-07-26 | 2001-02-09 | Shinko Electric Ind Co Ltd | 多層配線回路基板及びその製造方法 |
JP2001085802A (ja) * | 1999-09-16 | 2001-03-30 | Hitachi Cable Ltd | 配線基板及びそれを用いた電子装置及びその製造方法 |
JP2001298272A (ja) * | 2000-04-13 | 2001-10-26 | Nec Corp | プリント基板 |
Non-Patent Citations (1)
Title |
---|
See also references of EP1677585A4 * |
Also Published As
Publication number | Publication date |
---|---|
US7971354B2 (en) | 2011-07-05 |
EP1677585A1 (en) | 2006-07-05 |
KR100942400B1 (ko) | 2010-02-17 |
JP4504925B2 (ja) | 2010-07-14 |
TW200531610A (en) | 2005-09-16 |
EP1677585A4 (en) | 2010-05-19 |
US20060180341A1 (en) | 2006-08-17 |
TWI331498B (ja) | 2010-10-01 |
US20100108637A1 (en) | 2010-05-06 |
US7754978B2 (en) | 2010-07-13 |
KR20060061397A (ko) | 2006-06-07 |
JPWO2005074340A1 (ja) | 2007-09-13 |
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