JP4518114B2 - 電子部品内蔵基板及びその製造方法 - Google Patents
電子部品内蔵基板及びその製造方法 Download PDFInfo
- Publication number
- JP4518114B2 JP4518114B2 JP2007193838A JP2007193838A JP4518114B2 JP 4518114 B2 JP4518114 B2 JP 4518114B2 JP 2007193838 A JP2007193838 A JP 2007193838A JP 2007193838 A JP2007193838 A JP 2007193838A JP 4518114 B2 JP4518114 B2 JP 4518114B2
- Authority
- JP
- Japan
- Prior art keywords
- electronic component
- substrate
- insulating layer
- manufacturing
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01012—Magnesium [Mg]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0102—Calcium [Ca]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01024—Chromium [Cr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0103—Zinc [Zn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01038—Strontium [Sr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0104—Zirconium [Zr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01057—Lanthanum [La]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01073—Tantalum [Ta]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/049—Nitrides composed of metals from groups of the periodic table
- H01L2924/0495—5th Group
- H01L2924/04953—TaN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19042—Component type being an inductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10204—Dummy component, dummy PCB or template, e.g. for monitoring, controlling of processes, comparing, scanning
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10636—Leadless chip, e.g. chip capacitor or resistor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
図1は、本発明による電子部品内蔵基板の第1実施形態の要部を示す概略断面図である。ワークシート100は、碁盤目状に2×2の配列で計4個の個別基板をシート面内に包含する電子部品内蔵集合基板であり、略矩形状の基体11の一方の面(図示上面)に絶縁層21,31を備え、絶縁層21の内部の所定位置に電子部品41及びチップ状ダミー部品51(素体)が埋設されたものである。
図16及び図17は、本発明による電子部品内蔵基板の第2実施形態の概略構成を示す平面図及び断面図である。ワークシート300は、図示の如く、ワークシートの周縁領域に配置された一部のチップ状ダミー部品51に代えて、チップ状ダミー部品81(素体)を備えること以外は、上記の第1実施形態のワークシート100と同様に構成されたものである。チップ状ダミー部品81は、図示の如く、基体11の周縁領域に枠状に配置され、その枠内にチップ状ダミー部品51が十字状に配置されている。チップ状ダミー部品81は、チップ状ダミー部品51よりも厚さが薄くされ、また、図示の如く、基体11の外周方向へ向かって傾斜する傾斜面81aを有し、これにより、チップ状ダミー部品81は、基体11の外周方向へ向かって厚さが薄くなっている。
図18及び図19は、本発明による電子部品内蔵基板の第3実施形態の概略構成を示す平面図及び断面図である。ワークシート400は、チップ状ダミー部品51に代えて、チップ状ダミー部品91(素体)を備えること以外は、上記の第1実施形態のワークシート100と同様に構成されたものである。チップ状ダミー部品91は、図示の如く、電子部品41に比して、平面視における面積が小さく且つ断面厚さ(最厚部)が薄くされ、また、粗面化された天面91aを有する。
図20及び図21は、本発明による電子部品内蔵基板の第4実施形態の概略構成を示す平面図及び断面図である。ワークシート500は、図示の如く、外周に配置されたチップ状ダミー部品51に代えて、第3実施形態にて用いたチップ状ダミー部品91を備えること以外は、上記の第1実施形態のワークシート100と同様に構成されたものである。このようにチップ状ダミー部品51,91を用いても、上記第1乃至第3実施形態と同様の作用効果が奏される。
Claims (5)
- 基体を準備する工程と、
前記基体上に電子部品を載置する工程と、
前記基体における前記電子部品の非載置部に、該電子部品の主材料と線熱膨張係数が同等の材料を主材料とする素体を載置する工程と、
前記基体上に、前記電子部品及び前記素体を覆うように、絶縁層を形成する工程と、
前記基体及び/又は絶縁層に配線層を形成する工程と、
を有し、
前記素体として、前記絶縁層中で占有する空間体積率が前記基体の外周方向に向かって小さくなるものを用いる、
電子部品内蔵基板の製造方法。 - 前記素体を載置する工程においては、前記電子部品と略等間隔に、前記素体を載置する、
請求項1に記載の電子部品内蔵基板の製造方法。 - 前記素体を載置する工程においては、前記電子部品を取り囲むように、前記素体を載置する、
請求項1又は2に記載の電子部品内蔵基板の製造方法。 - 前記素体を載置する工程においては、前記電子部品及び前記素体を、略同一平面上に載置する、
請求項1乃至3のいずれか1項に記載の電子部品内蔵基板の製造方法。 - 基体と、
前記基体上に載置された電子部品と、
前記基体における前記電子部品の非載置部に載置されており、且つ、該電子部品の主材料と線熱膨張係数が同等の材料を主材料とする素体と、
前記基体上に、前記電子部品及び前記素体を覆うように形成された絶縁層と、
前記基体及び/又は絶縁層に形成された配線層と、
を有し、
前記素体は、前記絶縁層中で占有する空間体積率が前記基体の外周方向に向かって小さくなる、
電子部品内蔵基板。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007193838A JP4518114B2 (ja) | 2007-07-25 | 2007-07-25 | 電子部品内蔵基板及びその製造方法 |
US12/219,354 US20090025961A1 (en) | 2007-07-25 | 2008-07-21 | Electronic component-embedded board and method of manufacturing the same |
AT08013360T ATE516694T1 (de) | 2007-07-25 | 2008-07-24 | Leiterplatte mit integrierten elektronischen komponenten und herstellungsverfahren dafür |
EP08013360A EP2019574B1 (en) | 2007-07-25 | 2008-07-24 | Electronic component-embedded board and method of manufacturing the same |
CN2008101442121A CN101355857B (zh) | 2007-07-25 | 2008-07-25 | 电子部件内置基板及其制造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007193838A JP4518114B2 (ja) | 2007-07-25 | 2007-07-25 | 電子部品内蔵基板及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009032824A JP2009032824A (ja) | 2009-02-12 |
JP4518114B2 true JP4518114B2 (ja) | 2010-08-04 |
Family
ID=40019399
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007193838A Active JP4518114B2 (ja) | 2007-07-25 | 2007-07-25 | 電子部品内蔵基板及びその製造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US20090025961A1 (ja) |
EP (1) | EP2019574B1 (ja) |
JP (1) | JP4518114B2 (ja) |
CN (1) | CN101355857B (ja) |
AT (1) | ATE516694T1 (ja) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8921705B2 (en) * | 2008-11-28 | 2014-12-30 | Ibiden Co., Ltd. | Wiring board and fabrication method therefor |
WO2012042668A1 (ja) * | 2010-10-01 | 2012-04-05 | 株式会社メイコー | 部品内蔵基板及び部品内蔵基板の製造方法 |
JP2013098410A (ja) * | 2011-11-02 | 2013-05-20 | Ibiden Co Ltd | 多数個取り基板 |
KR101613912B1 (ko) * | 2012-07-05 | 2016-04-20 | 가부시키가이샤 무라타 세이사쿠쇼 | 부품 내장 기판 |
CN204498488U (zh) * | 2012-10-03 | 2015-07-22 | 株式会社村田制作所 | 元器件内置基板 |
JP2014107433A (ja) * | 2012-11-28 | 2014-06-09 | Ibiden Co Ltd | 多数個取り基板 |
CN105224536A (zh) * | 2014-05-29 | 2016-01-06 | 国际商业机器公司 | 划分数据库的方法和装置 |
KR102368069B1 (ko) | 2014-10-22 | 2022-02-25 | 삼성전자주식회사 | 반도체 패키지의 제조 방법 |
KR102207272B1 (ko) * | 2015-01-07 | 2021-01-25 | 삼성전기주식회사 | 인쇄회로기판, 그 제조방법, 및 전자부품 모듈 |
WO2017147151A1 (en) * | 2016-02-22 | 2017-08-31 | The Charles Stark Draper Laboratory, Inc. | Method of manufacturing an implantable neural electrode interface platform |
JP6902633B2 (ja) * | 2018-02-12 | 2021-07-14 | 株式会社Fuji | 装着精度測定用チップおよび装着精度測定用キット |
JP7235379B2 (ja) * | 2019-06-19 | 2023-03-08 | 住友電工デバイス・イノベーション株式会社 | 電子デバイスの製造方法 |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11112114A (ja) * | 1997-10-06 | 1999-04-23 | Denso Corp | プリント基板 |
JP2002016173A (ja) * | 2000-06-30 | 2002-01-18 | Mitsubishi Electric Corp | 半導体装置 |
JP2002324973A (ja) * | 2001-04-26 | 2002-11-08 | Sumitomo Metal Electronics Devices Inc | セラミック多層基板 |
JP2003347452A (ja) * | 2002-05-27 | 2003-12-05 | Tdk Corp | 電子部品用構造物 |
JP2004071698A (ja) * | 2002-08-02 | 2004-03-04 | Hitachi Metals Ltd | 半導体パッケージ |
JP2004072032A (ja) * | 2002-08-09 | 2004-03-04 | Casio Comput Co Ltd | 半導体装置およびその製造方法 |
JP2004311598A (ja) * | 2003-04-03 | 2004-11-04 | Ngk Spark Plug Co Ltd | 補強材付き基板、半導体素子と補強材と基板とからなる配線基板 |
JP2005251792A (ja) * | 2004-03-01 | 2005-09-15 | Fujitsu Ltd | 配線基板およびその製造方法 |
JP2006261245A (ja) * | 2005-03-15 | 2006-09-28 | Shinko Electric Ind Co Ltd | 配線基板の製造方法 |
JP2006261246A (ja) * | 2005-03-15 | 2006-09-28 | Shinko Electric Ind Co Ltd | 配線基板および配線基板の製造方法 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0770645B2 (ja) | 1986-06-11 | 1995-07-31 | 日本電気株式会社 | 混成集積回路 |
US5844319A (en) * | 1997-03-03 | 1998-12-01 | Motorola Corporation | Microelectronic assembly with collar surrounding integrated circuit component on a substrate |
EP1098368B1 (en) | 1999-04-16 | 2011-12-21 | Panasonic Corporation | Module component and method of manufacturing the same |
WO2001024598A1 (fr) * | 1999-09-27 | 2001-04-05 | Matsushita Electric Industrial Co., Ltd. | Procede et dispositif de montage de composants |
JP2001284783A (ja) * | 2000-03-30 | 2001-10-12 | Shinko Electric Ind Co Ltd | 表面実装用基板及び表面実装構造 |
JP3816380B2 (ja) * | 2001-12-14 | 2006-08-30 | 富士通株式会社 | 吸熱用ダミー部品を備えた基板ユニット及びその製造方法 |
US8829661B2 (en) * | 2006-03-10 | 2014-09-09 | Freescale Semiconductor, Inc. | Warp compensated package and method |
-
2007
- 2007-07-25 JP JP2007193838A patent/JP4518114B2/ja active Active
-
2008
- 2008-07-21 US US12/219,354 patent/US20090025961A1/en not_active Abandoned
- 2008-07-24 AT AT08013360T patent/ATE516694T1/de not_active IP Right Cessation
- 2008-07-24 EP EP08013360A patent/EP2019574B1/en active Active
- 2008-07-25 CN CN2008101442121A patent/CN101355857B/zh active Active
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11112114A (ja) * | 1997-10-06 | 1999-04-23 | Denso Corp | プリント基板 |
JP2002016173A (ja) * | 2000-06-30 | 2002-01-18 | Mitsubishi Electric Corp | 半導体装置 |
JP2002324973A (ja) * | 2001-04-26 | 2002-11-08 | Sumitomo Metal Electronics Devices Inc | セラミック多層基板 |
JP2003347452A (ja) * | 2002-05-27 | 2003-12-05 | Tdk Corp | 電子部品用構造物 |
JP2004071698A (ja) * | 2002-08-02 | 2004-03-04 | Hitachi Metals Ltd | 半導体パッケージ |
JP2004072032A (ja) * | 2002-08-09 | 2004-03-04 | Casio Comput Co Ltd | 半導体装置およびその製造方法 |
JP2004311598A (ja) * | 2003-04-03 | 2004-11-04 | Ngk Spark Plug Co Ltd | 補強材付き基板、半導体素子と補強材と基板とからなる配線基板 |
JP2005251792A (ja) * | 2004-03-01 | 2005-09-15 | Fujitsu Ltd | 配線基板およびその製造方法 |
JP2006261245A (ja) * | 2005-03-15 | 2006-09-28 | Shinko Electric Ind Co Ltd | 配線基板の製造方法 |
JP2006261246A (ja) * | 2005-03-15 | 2006-09-28 | Shinko Electric Ind Co Ltd | 配線基板および配線基板の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
EP2019574B1 (en) | 2011-07-13 |
CN101355857A (zh) | 2009-01-28 |
ATE516694T1 (de) | 2011-07-15 |
US20090025961A1 (en) | 2009-01-29 |
EP2019574A2 (en) | 2009-01-28 |
JP2009032824A (ja) | 2009-02-12 |
CN101355857B (zh) | 2011-04-06 |
EP2019574A3 (en) | 2009-07-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4518114B2 (ja) | 電子部品内蔵基板及びその製造方法 | |
JP4518113B2 (ja) | 電子部品内蔵基板及びその製造方法 | |
JP4487271B2 (ja) | 集合基板及びその製造方法 | |
JP4661787B2 (ja) | 配線基板とその製造方法 | |
JP4277036B2 (ja) | 半導体内蔵基板及びその製造方法 | |
CN106328607B (zh) | 半导体器件及其制造方法 | |
KR101055509B1 (ko) | 전자부품 내장형 인쇄회로기판 | |
JP2003298005A (ja) | 半導体装置およびその製造方法 | |
US20120292778A1 (en) | Embedded semiconductor power modules and packages | |
JP2016025281A (ja) | 半導体装置及びその製造方法 | |
JP2011151048A (ja) | 電子部品の製造方法および電子部品 | |
JP4324732B2 (ja) | 半導体装置の製造方法 | |
JP2010283300A (ja) | 突起電極付き配線基板及び突起電極付き配線基板の製造方法 | |
JP5097006B2 (ja) | プリント配線基板及びその製造方法 | |
JP2005123493A (ja) | 配線基板及び素子実装基板 | |
JP5013138B2 (ja) | 集合基板及びその製造方法 | |
JP2008147228A (ja) | 配線基板及びその製造方法 | |
JP2005191157A (ja) | 半導体装置およびその製造方法 | |
TWI248148B (en) | Semiconductor device having heat dissipation layer cross-reference to related applications | |
JP2005235881A (ja) | 半導体装置およびその製造方法 | |
JP2013062424A (ja) | 半導体装置の製造方法およびその方法により製造された半導体装置 | |
JP2012069556A (ja) | 半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20090324 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20090716 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20090721 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090915 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100305 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100408 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20100427 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20100510 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130528 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4518114 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140528 Year of fee payment: 4 |