TWI394503B - 佈線板及其製造方法 - Google Patents
佈線板及其製造方法 Download PDFInfo
- Publication number
- TWI394503B TWI394503B TW095108709A TW95108709A TWI394503B TW I394503 B TWI394503 B TW I394503B TW 095108709 A TW095108709 A TW 095108709A TW 95108709 A TW95108709 A TW 95108709A TW I394503 B TWI394503 B TW I394503B
- Authority
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- Taiwan
- Prior art keywords
- wiring board
- wiring
- insulating layer
- semiconductor wafer
- manufacturing
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 39
- 239000004065 semiconductor Substances 0.000 claims abstract description 95
- 230000003014 reinforcing effect Effects 0.000 claims abstract description 50
- 229910000679 solder Inorganic materials 0.000 claims description 36
- 238000009713 electroplating Methods 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 11
- 230000002787 reinforcement Effects 0.000 claims description 10
- 239000011347 resin Substances 0.000 claims description 7
- 229920005989 resin Polymers 0.000 claims description 7
- 238000010438 heat treatment Methods 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 3
- 229920001187 thermosetting polymer Polymers 0.000 claims description 2
- 230000009467 reduction Effects 0.000 abstract description 4
- 230000001629 suppression Effects 0.000 abstract description 2
- 235000012431 wafers Nutrition 0.000 description 87
- 239000011162 core material Substances 0.000 description 28
- 229910052802 copper Inorganic materials 0.000 description 11
- 239000010949 copper Substances 0.000 description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 10
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 230000004048 modification Effects 0.000 description 8
- 238000012986 modification Methods 0.000 description 8
- 238000007747 plating Methods 0.000 description 8
- 239000003351 stiffener Substances 0.000 description 7
- 239000010931 gold Substances 0.000 description 6
- 238000009413 insulation Methods 0.000 description 5
- 239000003822 epoxy resin Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000003475 lamination Methods 0.000 description 4
- 238000001459 lithography Methods 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 239000009719 polyimide resin Substances 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 238000001723 curing Methods 0.000 description 2
- 238000005202 decontamination Methods 0.000 description 2
- 230000003588 decontaminative effect Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000000843 powder Substances 0.000 description 2
- 239000000956 alloy Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000013007 heat curing Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- XEEYBQQBJWHFJM-UHFFFAOYSA-N iron Substances [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
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- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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Description
本案係主張於2005年3月15日提出申請之日本專利申請案第2005-073946號之國外優先權,該案全文內容以引用方式併入本文。
本發明係關於一種佈線板之製造方法,更特別係關於結合半導體晶片之佈線板之製造方法。
目前,使用半導體裝置諸如半導體晶片的電子裝置的效能提升已經有重大進展。需要有更高密度之半導體晶片安裝於板上,安裝半導體晶片的板的尺寸縮小,以及板之空間的節省。
如此提出一種嵌入半導體晶片之板,亦即已提出之內建晶片型佈線板。曾經提出多種結合半導體晶片於板之組態(例如參考JP-A-2001-196525)。此種內建晶片型佈線板具有佈線結構連接至半導體晶片。此外,終端連接部係形成於佈線板上,讓佈線板可連接至另一裝置、主機板等。
但於內建晶片型佈線板實現厚度之縮小(減薄)且較高密度的情況下,佈線板的翹曲可能成問題。為了處理佈線板的此種翹曲問題,需要層合具有預定厚度之板諸如芯板,該板具有半導體晶片嵌入其中之一層,讓佈線板具有抑制翹曲的結構。結果於具有此種層合結構之內建晶片型佈線板中,難以實現佈線板的厚度減薄與較高密度。
此外,難以達成佈線板厚度的縮小,同時抑制佈線板的翹曲。
本發明之目的係提供一種新穎且有用之佈線板及該佈線板之製造方法,藉此來解決前述問題。
本發明中,可達成結合半導體晶片之佈線板的厚度減薄,且抑制此種佈線板的翹曲。
於若干實作中,本發明之佈線板包含:至少一個半導體晶片;其中嵌置該至少一個半導體晶片之絕緣層;連接該半導體晶片之佈線結構;以及加強該絕緣層之至少一個加強件,該加強件係嵌置於該絕緣層內部。
此種佈線板具有可抑制佈線板翹曲且縮小佈線板厚度的結構。
於本發明之佈線板中,加強件和半導體晶片實質上係安裝於相同的平面上。如此,可達成佈線板厚度的減薄。
於本發明之佈線板中,加強件係形成為環繞該半導體晶片。如此可有利地提升抑制佈線板之翹曲的效果。
於本發明之佈線板中,佈線結構具有多層佈線結構。如此可連成較高密度佈線結構。如此本實施例為優異。
於本發明之佈線板中,佈線結構包括:形成於半導體晶片之第一側上之第一佈線次結構;及形成於該半導體晶片之第二側上之第二佈線次結構。如此可達成較高密度之佈線結構。結果本實施例為優異。
於本發明之佈線板中,第一佈線次結構和第二佈線次結構係藉形成於絕緣層之通孔插塞來連接。如此可達成較高密度之佈線結構。結果本實施例為優異。
本發明之佈線板進一步包含:形成於佈線板之第一表面上之第一終端連接部,該第一終端連接部係經由該佈線結構而連接至半導體晶片;以及形成於佈線板之第二表面上之第二終端連接部,該第二終端連接部係經由該佈線結構而連接至半導體晶片。如此,終端連接部係分別於與第一表面和第二表面相應的兩側各自連接半導體晶片。
於本發明之佈線板中,加強件係由有機芯材或金屬材料製成。
於若干實作中,本發明之一種佈線板之製造方法包含:形成一下層佈線結構;安裝至少一個半導體晶片於該下層佈線結構上,該半導體晶片係連接該下層佈線結構;形成至少一個加強件;以及形成一絕緣層,讓半導體晶片和加強件係嵌置於絕緣層,該加強件可加強該絕緣層。
此種佈線板之製造方法能抑制佈線板的翹曲,且減小佈線板之厚度。
於本發明之佈線板之製造方法中,加強件和半導體晶片係安裝於實質上相同的平面上。如此可達成佈線板之厚度的減薄。
本發明之佈線板之製造方法進一步包含:形成通孔插塞於絕緣層,連接該通孔插塞至下層佈線結構;以及形成一上層佈線結構讓半導體晶片係安裝於下層佈線結構與上層佈線結構間,以及連接上層佈線結構至該通孔插塞。如此可達成較高密度的佈線結構。結果,本實施例為優異。
於本發明之佈線板之製造方法中,下層佈線結構係形成於芯板上,以及該方法進一步包含:移除芯板。如此可達成佈線板之厚度的減薄。此外,可穩定地形成佈線板。結果本實施例為優異。
於本發明之佈線板之製造方法中,芯板係由導電材料所製成,下層佈線結構之形成步驟包括使用芯板作為電極,藉電解鍍覆來形成下層佈線結構。如此有助於在進行電解鍍覆時的電力供應。如此本實施例為優異。
於本發明之佈線板之製造方法中,半導體晶片係經由形成於該半導體晶片上之釦狀凸塊而電性連接下層佈線結構。如此可提升半導體晶片與佈線結構間的連接可靠度。
本發明之佈線板之製造方法進一步包含:於釦狀凸塊與下層佈線結構間形成由焊料製造之連接部。如此,可提升半導體晶片與佈線結構間的連接的可靠度。
根據本發明,可實現結合半導體晶片之佈線板之厚度的減薄,且抑制此種佈線板的翹曲是可能的。
其次將參考附圖說明本發明之實施例如下。
圖1為剖面圖,示意顯示根據本發明之第一實施例之佈線板100。
參考圖1,根據本實施例之佈線板100包括嵌置於絕緣層103之半導體晶片109,以及連接至半導體晶片109之佈線結構。此種佈線結構具有圖案佈線106和117及通孔插塞105和116。
此外,佈線板100具有形成於其第一側之終端連接部102,以及形成於第一側所相對之第二側之終端連接部119。終端連接部102和119係經由佈線結構而連接至半導體晶片109。
至目前為止,欲減薄此種內建半導體晶片型佈線板之厚度之情況下,偶爾層合佈線板和諸如芯板之結構本體,芯板可支持佈線板且抑制佈線板的翹曲。因而難以達成佈線板之厚度的減薄及抑制翹曲二者。
如此,根據本實施例之佈線板100係組態成藉加強絕緣層103以防止翹曲的加強件112係嵌置於絕緣層103,半導體晶片109也嵌置於絕緣層103。經由使用加強件112可抑制佈線板100的翹曲。於前述結構之情況下,可有效抑制佈線板100的翹曲,而實際上並未增加佈線板100的厚度。
於圖1中,單一半導體晶片109設置於佈線板100來簡化圖式與說明。但類似安裝單一半導體晶片109之組態,也可安裝多個半導體晶片109於佈線板100。此外,於此種情況下,經由將加強件112嵌置於絕緣層103,同樣可抑制佈線板100的翹曲。
如此,比較具有絕緣層103層合用以支持絕緣層103之芯板之結構的佈線板,本實施例具有可減薄佈線板之厚度的結構。
其次,將說明佈線板100之組配的細節。舉例言之,連接至半導體晶片109之佈線結構包括例如由銅製成之圖案佈線106和117及通孔插塞105和116。此等佈線結構係連接於半導體晶片109。
例如金製成的釦狀凸塊108係形成於半導體晶片109之電極墊(圖中未顯示)上,且係經由例如焊料所製成之連接部107而電性連接至圖案佈線106。經由使用釦狀凸塊108,可提升半導體晶片109與圖案佈線106間的電氣連接的可靠度。此外,經由形成連接部107於釦狀凸塊108與圖案佈線106間,可進一步提升其間的電氣連接的可靠度。
圖案佈線106係與通孔插塞佈線105整合式形成。例如包括Au/Ni鍍覆層的終端連接部102係形成於通孔插塞佈線105連接至圖案佈線106之該側的對側上。此終端連接部102係形成為其一面係從絕緣層103暴露出。焊料抗蝕劑層120係形成為覆蓋絕緣層103且環繞終端連接部102。若有所需,焊料凸塊121形成於終端連接部102上。
例如圖案佈線117係形成於絕緣層103上,位在與圖案佈線106所形成之該側相對的半導體晶片109之一側上。圖案佈線117及106係藉通孔插塞116連接。例如,通孔插塞116與圖案佈線117係一體成形。
例如包括Au/Ni鍍覆層的終端連接部119係形成於圖案佈線117上。焊料抗蝕劑層118係形成於絕緣層103和圖案佈線117上,因而環繞終端連接部119。
例如,用於所謂的堆疊板之堆疊樹脂可用於絕緣層103。舉例言之,可使用諸如環氧樹脂或聚醯亞胺樹脂之熱硬化樹脂。
較佳地,由樹脂材料所製成的底填補層110係形成於半導體晶片109與圖案佈線106間、或形成於半導體晶片109與絕緣層103間。
佈線板100之組態成可省略例如焊料抗蝕劑層118和120及焊料凸塊121。
於根據本實施例之佈線板100中,可連接至半導體晶片109之終端連接部係分別設置於佈線板之兩側上。如此,此佈線板100係組態成欲連接其上之物件諸如其它裝置、其它半導體晶片和主機板容易連接至佈線板100之兩側上。
多種材料可用於加強件112。舉例言之,可使用比絕緣層103更硬的樹脂材料,例如為用於芯板等之有機芯材(偶爾稱作為預浸材料)、諸如Cu、Ni、Fe之金屬材料、此等金屬材料之合金材料或複合材料。
較佳地,加強件112係形成於與半導體晶片109所形成之該平面而實質上相同平面上。如此,加強件112嵌置於絕緣層103內部,而未增加絕緣層103之厚度。
根據本實施例之佈線板100可根據半導體晶片之規格和連接規格而形成為各種形狀與厚度。佈線板之實用厚度實例說明如後。
舉例言之,半導體晶片109之厚度D2設定為80微米的情況,從半導體晶片109之上端面至焊料抗蝕劑層118之距離D1為20微米。從半導體晶片109之下端面至圖案佈線106之上端面之距離D3為45微米。
焊料抗蝕劑層118之厚度d1和焊料抗蝕劑層120之厚度d5為30微米。從焊料抗蝕劑層120之上端面至圖案佈線106之下端面之距離d4為25微米。圖案佈線106之厚度d3為10微米。從圖案佈線106之上端面至焊料抗蝕劑層118之下端面之距離d2為145微米。
此種情況下,佈線板厚度(焊料凸塊121除外)係等於240微米。
圖2A示意顯示圖1所示佈線板100之平面圖。附帶地,於圖2A中,省略半導體晶片109和加強件112以外的其它元件的繪圖。如圖2A所示,加強件112係形成為環繞半導體晶片109因而例如包圍半導體晶片109。如此,可有利地提升防止翹曲的優點。附帶地,單一半導體晶片或多個半導體晶片可安裝於其上。
加強件非僅限於前述實例。例如,加強件形狀可以後文說明之多種方式改變。
圖2B和圖2C為顯示圖2A所示加強件之修改例之視圖。附帶地,前述圖2A所示的各個元件於圖2B和圖2C中係以與圖2A使用的元件符號相同的元件符號標示。如此,省略該等元件之說明。加強件可經修改成例如圖2B所示之加強件112A,其分別設置於佈線板兩側(端部)且彼此相對。另外,加強件可經修改如圖2C所示之加強件112B,其係分別設置於佈線板之角隅部附近且彼此相對。圖2C中,加強件112係形成為部分環繞多個半導體晶片。如前述,可根據半導體晶片之大小、佈線結構或佈線板的規格做出加強件之多項修改及變化。
其次,於後文將以參考圖3A至圖3O之步驟順序,循序說明根據本發明之此實施例在圖1所示佈線板100之製造方法之實例。
首先如圖3A所示,製備例如厚200微米之銅所製成的芯板101。
隨後,於圖3B所示步驟中,經由使用其上藉微影術處理而進行圖案製作之光阻圖案作為光罩,也使用芯板作為電極,藉電解鍍覆而形成例如Au/Ni所製成之終端連接部102於芯板101上。如此,於芯板101係由導電材料所製成之情況,芯板可用作為電極而用於電解鍍覆。於隨後步驟進行電解鍍覆之情況下,視需要,使用芯板作為電極(或於電解鍍覆時使用芯板作為激化路徑)。於終端連接部102形成後,光阻圖案被剝離。
隨後,於圖3C所示步驟中,樹脂材料諸如環氧樹脂所製成的絕緣層103例如係經由層合或施用等方式形成來覆蓋終端連接部102。此外,通孔103A例如使用雷射光束處理來暴露出終端連接部。也較佳於形成通孔103A後,視需要進行除污處理,其中殘餘物被去除,而絕緣層103之表面被粗化。
隨後,於圖3D所示步驟中,晶種層104例如藉無電極鍍銅而形成於絕緣層103之表面上和終端連接部102之表面上。
隨後,於圖3E所示步驟中,使用其上藉微影術進行製作圖案之光阻圖案作為光罩,藉例如電解鍍銅而形成通孔插塞,因而埋設通孔103A。此外,欲連接至通孔插塞105之圖案佈線106係與通孔插塞105整合式形成。當進行電解鍍覆完成時,剝離光阻圖案。
隨後於圖3F所示步驟中,藉蝕刻去除形成於絕緣層103上之晶種層104之不必要的部分。然後,使用形成於絕緣層103和圖案佈線106上之光阻圖案,且使用其上藉微影術進行製作圖案之光阻圖案作為光罩,藉電解鍍覆而於圖案佈線106上形成例如由焊料所製成之連接部107。
此種情況下,較佳地,鎳層係形成於連接部107與圖案佈線106間來作為障層。當電解鍍覆完成時,光阻圖案被剝離。此外,於此種情況下,連接部107之形成方法並非限於電解鍍覆。舉例言之,可採用一種方法,施用黏著劑材料於圖案佈線106上,以及施用細的焊料粉末,讓焊料粉末黏貼於黏著劑材料。
隨後,於圖3G所示步驟中,設置(安裝)半導體晶片109於圖案佈線106上。於此種情況下,例如金製成的釦狀凸塊108係設置於半導體晶片109之電極墊(圖中未顯示)上。半導體晶片109係安裝於其上,讓釦狀凸塊108變成與連接部107接觸。此時,加熱板來進行再流動焊接。如此提升釦狀凸塊108與連接部107間的連接的可靠度。
較佳地例如,樹脂材料填補於半導體晶片109與圖案佈線106間的空間、或半導體晶片109與絕緣層103間的空間,因而形成底填補層110。
隨後,於圖3H所示步驟中,例如由可熱固化環氧樹脂或可熱固化聚醯亞胺樹脂所製成之絕緣層111例如係藉層合形成而覆蓋絕緣層103、圖案佈線106和半導體晶片109之上。
絕緣層111可防止於隨後步驟設置的加強件、或圖案佈線106因加強件接觸圖案佈線106而受損。此種情況下,絕緣層111係形成為例如具有約25微米之厚度。
特別地,於絕緣層111係由與絕緣層103之材料之相同材料製成時,絕緣層103和111彼此完全一體成形。因此,於本圖及隨後各圖中,假設絕緣層103和111形成為一層絕緣層,包括絕緣層111的絕緣層103顯示為絕緣層103。
隨後,於圖3I所示步驟中,例如厚100微米且由有機芯材(預浸材料)所製成的加強件112係經由絕緣層103而設置(安裝)於圖案佈線106上。於此種情況下,諸如銅和鎳之金屬材料可用於加強件112。另外,加強件112例如可藉鍍覆法形成。
隨後,於圖3J所示步驟中,例如由可熱固化環氧樹脂或可熱固化聚醯亞胺樹脂所製成之絕緣層113係藉層合形成,因而覆蓋加強件112和半導體晶片109之上。
特別地,於絕緣層113係由與絕緣層103之材料之相同材料製成的情況,絕緣層103與113變成彼此完全一體成形。因此,於本圖及隨後各圖中,假設絕緣層103與113形成單一絕緣層,含括絕緣層113的絕緣層103顯示為絕緣層103。
隨後,於圖3K所示步驟中,藉加熱絕緣層103來進行熱固化步驟(固化步驟)。於此種情況下,加強件112係嵌置於絕緣層103。如此,因溫度改變造成的絕緣層103的翹曲程度受到壓抑,讓絕緣層103可維持有利的平坦度。
隨後,於圖3L所示步驟中,例如經由使用雷射光束於絕緣層103形成通孔114到達圖案佈線106。此外,可視需要來施行除污步驟。然後,晶種層115形成於包括通孔114之內側壁的絕緣層103上,例如藉無電極鍍銅來暴露出圖案佈線106。
隨後,於圖3M所示步驟中,使用其上藉微影術進行圖案製作的光阻圖案作為光罩,藉電解鍍銅來形成通孔插塞116因而埋設通孔114。此外,欲連接至通孔插塞116的圖案佈線117係與通孔插塞116一體成形。於進行電解鍍覆完成時,光阻圖案被剝離。此外,藉蝕刻去除形成於絕緣層103上之晶種層115不必要的部分。
隨後,於圖3N所示步驟中,焊料抗蝕劑層118係形成於圖案佈線117和絕緣層103上,讓圖案佈線117的某些部分暴露出。然後,例如由Ni/Au所製成的終端連接部119係藉無電解鍍覆而形成於暴露出的圖案佈線117之暴露部分上。
隨後,於圖30所示步驟中,例如由銅所製成之芯板101例如藉蝕刻去除。然後,如圖1所示,形成焊料抗蝕劑層120。然後,視需要,形成焊料凸塊121。如此形成佈線板100。
於本實施例中,例如由銅所製成之芯板101係藉蝕刻去除。但另外,經由製備芯板101於其上將施用黏著劑離型帶,芯板101可於欲與絕緣層103接觸之該側上設置離型層。較佳地,離型層之黏著強度藉加熱而下降。於此種情況下,如圖30所示,於從絕緣層103去除芯板101之步驟中,經由例如使用烤爐加熱整個佈線板,來從離型層剝離絕緣層103。
根據本實施例之製造方法,加強件112係於圖3I所示之步驟中設置。然後,於圖3K所示步驟中,於其中嵌置加強件112之絕緣層103上進行固化。如此,於隨後各步驟,獲得抑制絕緣層103或整片佈線板之翹曲程度的優點。特別地,比較相關方法,可更加有效抑制因溫度的升/降所造成的應力變化、及因鍍覆、除污處理、層合處理等所造成之應力變化而導致的翹曲之程度。結果,可形成平坦度高且高可靠度的佈線板。
此外,於本實施例中,例如於預定製造步驟中,佈線板100係形成於例如由銅所製成之芯板101上。如此,可抑制製造程序中的翹曲之程度。此外,於預定處理程序完成時,去除芯板101。如此可達成佈線板之厚度的減薄。
根據本發明之佈線板非僅限於前述實施例。例如,佈線結構或加強件可以多種方式修改或變化。
例如,圖4示意顯示佈線板200,其為佈線板100之修改例。
參考圖4,於本圖所示之佈線板200中,絕緣層203、終端連接部202和219、半導體晶片209、釦狀凸塊208、連接部207、底填補層210、焊料抗蝕劑層218和220、及加強件212分別係與圖1所示佈線板100之絕緣層103、終端連接部102和119、半導體晶片109、釦狀凸塊108、連接部107、底填補層110、焊料抗蝕劑層118和120、及加強件112相對應。佈線板200具有類似於佈線板100之結構的結構。
以佈線板200為例,連接於半導體晶片209的佈線結構之層數比佈線板100增加。例如,佈線板100共有兩層佈線,其中一層係設置於半導體晶片之底側,而另一層係設置於半導體晶片之頂側。佈線板200共有四層,其中兩層係設置於半導體晶片的底側,而剩下的兩層係設置於半導體晶片的頂側。
以佈線板200為例,通孔插塞205和216係連接至半導體晶片所連接的圖案佈線206。此外,通孔插塞205係連接至圖案佈線223,且圖案佈線223係連接至其上形成有終端連接部202的通孔插塞222。另一方面,圖案佈線217係連接至通孔插塞216。圖案佈線217係經由通孔插塞224而連接於圖案佈線225,於圖案佈線225上形成終端連接部219。
如此,可視需要,改變佈線之層數。
根據半導體晶片的規格和連接的規格,佈線板200可形成為多種形狀和厚度。佈線板之實際厚度的實例說明如後。
例如於半導體晶片209之厚度D5設定為80微米之情況下,從半導體晶片209之上端面至圖案佈線217之距離D4為20微米。從半導體晶片209之下端面至圖案佈線206之上端面之距離D6為45微米。
焊料抗蝕劑層218之厚度d6和焊料抗蝕劑層220之厚度d12為30微米。從焊料抗蝕劑層220之上端面至圖案佈線223之下端面之距離d11為25微米。圖案佈線223之下端面至圖案佈線206之下端面之距離d10微25微米。圖案佈線206之厚度d9為10微米。從圖案佈線206之上端面至圖案佈線217之下端面之距離d8為145微米。從圖案佈線217之下端面至焊料抗蝕劑層218之下端面之距離d7為25微米。
本例中,佈線板200之厚度(焊料凸塊除外)係等於290微米。
圖5為視圖,示意顯示佈線板200A,佈線板200A為佈線板100之另一修改例。附帶地,本圖中,前述各元件係標示以相同的參考號碼。如此,省略此等元件之說明。
參考圖5,本圖所示佈線板200A中,與加強件212相應的加強件212A也形成於半導體晶片209附近。加強件212A之總面積係大於加強件212的總面積。
此種情況下,形成通孔插塞216用之通孔部係形成於加強件212A。
如此,可視需要,對加強件和佈線結構做出多種修改與變化。
於前述實施例中,加強件係安裝於面向下型別(複晶型)佈線板,來抑制佈線板的翹曲。但另外,加強件也可安裝於面向上型別之佈線板。此外,經由安裝加強件於其中嵌置半導體晶片的絕緣層中,可有效抑制面向上佈線板的翹曲,而實際上並未增加面向上型別佈線板的厚度。
雖然係參考特定實施例說明本發明,但熟諳技藝人士未悖離如隨附之申請專利範圍所述之本發明之精髓與範圍可做出多項修改及變化。
根據本發明,能使結合半導體晶片之佈線板之厚度減薄,且此種佈線板之翹曲的抑制是有可能的。
100...佈線板
101...芯板
102...終端連接部
103...絕緣層
103A...通孔
104...晶種層
105...通孔插塞
106...圖案佈線
107...連接部
108...釦狀凸塊
109...半導體晶片
110...底填補層
111...絕緣層
112...加強件
112A...加強件
112B...加強件
114...通孔
115...晶種層
116...通孔插塞
117...圖案佈線
118...焊料抗蝕劑層
119...終端連接部
120...焊料抗蝕劑層
121...焊料凸塊
200...佈線板
200A...佈線板
201...芯板
202...終端連接部
203...絕緣層
204...晶種層
205...通孔插塞
206...圖案佈線
207...連接部
208...釦狀凸塊
209...半導體晶片
210...底填補層
211...絕緣層
212...加強件
212A...加強件
214...通孔
215...晶種層
216...通孔插塞
217...圖案佈線
218...焊料抗蝕劑層
219...終端連接部
220...焊料抗蝕劑層
221...焊料凸塊
222...通孔插塞
223...圖案佈線
224...通孔插塞
225...圖案佈線
圖1為剖面圖,示意顯示根據本發明之第一實施例之佈線板。
圖2A為第一視圖,顯示根據第一實施例之加強件設置方法。
圖2B為第二視圖,顯示根據第一實施例之加強件設置方法。
圖2C為第三視圖,顯示根據第一實施例之加強件設置方法。
圖3A為第一視圖,顯示根據第一實施例之佈線板之製造方法。
圖3B為第二視圖,顯示根據第一實施例之佈線板之製造方法。
圖3C為第三視圖,顯示根據第一實施例之佈線板之製造方法。
圖3D為第四視圖,顯示根據第一實施例之佈線板之製造方法。
圖3E為第五視圖,顯示根據第一實施例之佈線板之製造方法。
圖3F為第六視圖,顯示根據第一實施例之佈線板之製造方法。
圖3G為第七視圖,顯示根據第一實施例之佈線板之製造方法。
圖3H為第八視圖,顯示根據第一實施例之佈線板之製造方法。
圖3I為第九視圖,顯示根據第一實施例之佈線板之製造方法。
圖3J為第十視圖,顯示根據第一實施例之佈線板之製造方法。
圖3K為第十一視圖,顯示根據第一實施例之佈線板之製造方法。
圖3L為第十二視圖,顯示根據第一實施例之佈線板之製造方法。
圖3M為第十三視圖,顯示根據第一實施例之佈線板之製造方法。
圖3N為第十四視圖,顯示根據第一實施例之佈線板之製造方法。
圖30為第十五視圖,顯示根據第一實施例之佈線板之製造方法。
圖4為顯示圖1所示佈線板之第一修改例之視圖。
圖5為顯示圖1所示佈線板之第二修改例之視圖。
100...佈線板
102...終端連接部
103...絕緣層
105...通孔插塞
106...圖案佈線
107...連接部
108...釦狀凸塊
109...半導體晶片
110...底填補層
112...加強件
116...通孔插塞
117...圖案佈線
118...焊料抗蝕劑層
119...終端連接部
120...焊料抗蝕劑層
121...焊料凸塊
Claims (8)
- 一種佈線板之製造方法,該方法包含:形成一下層佈線結構於一芯板上;安裝至少一個半導體晶片於該下層佈線結構上,且將該半導體晶片連接至該下層佈線結構;形成至少一個加強件;形成一絕緣層,係該半導體晶片和加強件嵌置於絕緣層,該加強件加強該絕緣層;以及完全地移除該芯板。
- 如申請專利範圍第1項之佈線板之製造方法,其中該加強件和該半導體晶片係實質上安裝於一相同平面上。
- 如申請專利範圍第1項之佈線板之製造方法,進一步包含:形成一通孔插塞於該絕緣層,且連接該通孔插塞至該下層佈線結構;以及形成一上層佈線結構,係該半導體晶片安裝於該下層佈線結構與該上層佈線結構間,以及連接該上層佈線結構至該通孔插塞。
- 如申請專利範圍第1項之佈線板之製造方法,其中該芯板係由導電材料所製成,以及下層佈線結構之形成步驟包括經由使用芯板作為電極,藉電解鍍覆來形成該下層佈線結構。
- 如申請專利範圍第1項之佈線板之製造方法,其中該半導體晶片係經由形成於該半導體晶片上之釦狀凸塊而 電性連接至該下層佈線結構。
- 如申請專利範圍第5項之佈線板之製造方法,進一步包含:於該釦狀凸塊與該下層佈線結構間形成由焊料所製造之一連接部。
- 如申請專利範圍第1項之佈線板之製造方法,其中該絕緣層之形成步驟包括:形成一第一絕緣層而覆蓋該半導體晶片和該下層佈線結構;以及形成一第二絕緣層而覆蓋該半導體晶片和該加強件,該加強件係形成於第一絕緣層上。
- 如申請專利範圍第7項之佈線板之製造方法,進一步包含:藉加熱而固化該第一絕緣層和該第二絕緣層,其中該第一絕緣層和該第二絕緣層係由熱硬化樹脂材料所製成。
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Families Citing this family (61)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4526983B2 (ja) | 2005-03-15 | 2010-08-18 | 新光電気工業株式会社 | 配線基板の製造方法 |
JP2008084959A (ja) | 2006-09-26 | 2008-04-10 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP4906462B2 (ja) * | 2006-10-11 | 2012-03-28 | 新光電気工業株式会社 | 電子部品内蔵基板および電子部品内蔵基板の製造方法 |
JP2008235550A (ja) * | 2007-03-20 | 2008-10-02 | Mitsubishi Electric Corp | プリント配線板、プリント配線板の製造方法、及びそれを用いた電子機器 |
US7498198B2 (en) * | 2007-04-30 | 2009-03-03 | International Business Machines Corporation | Structure and method for stress reduction in flip chip microelectronic packages using underfill materials with spatially varying properties |
US20080284047A1 (en) * | 2007-05-15 | 2008-11-20 | Eric Tosaya | Chip Package with Stiffener Ring |
US7863088B2 (en) * | 2007-05-16 | 2011-01-04 | Infineon Technologies Ag | Semiconductor device including covering a semiconductor with a molding compound and forming a through hole in the molding compound |
DE102007022959B4 (de) * | 2007-05-16 | 2012-04-19 | Infineon Technologies Ag | Verfahren zur Herstellung von Halbleitervorrichtungen |
JP4518114B2 (ja) * | 2007-07-25 | 2010-08-04 | Tdk株式会社 | 電子部品内蔵基板及びその製造方法 |
JP4518113B2 (ja) * | 2007-07-25 | 2010-08-04 | Tdk株式会社 | 電子部品内蔵基板及びその製造方法 |
JP5025399B2 (ja) * | 2007-09-27 | 2012-09-12 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
US7790576B2 (en) * | 2007-11-29 | 2010-09-07 | Stats Chippac, Ltd. | Semiconductor device and method of forming through hole vias in die extension region around periphery of die |
US20090170241A1 (en) * | 2007-12-26 | 2009-07-02 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier |
US8008133B2 (en) | 2008-02-11 | 2011-08-30 | Globalfoundries Inc. | Chip package with channel stiffener frame |
TWI356479B (en) * | 2008-03-04 | 2012-01-11 | Advanced Semiconductor Eng | Package structure with embedded die and method of |
US8313984B2 (en) * | 2008-03-19 | 2012-11-20 | Ati Technologies Ulc | Die substrate with reinforcement structure |
JP2010010644A (ja) * | 2008-05-27 | 2010-01-14 | Toshiba Corp | 半導体装置の製造方法 |
KR100965339B1 (ko) * | 2008-06-04 | 2010-06-22 | 삼성전기주식회사 | 전자부품 내장형 인쇄회로기판 및 그 제조방법 |
JP2009302427A (ja) * | 2008-06-17 | 2009-12-24 | Shinko Electric Ind Co Ltd | 半導体装置および半導体装置の製造方法 |
US7888184B2 (en) * | 2008-06-20 | 2011-02-15 | Stats Chippac Ltd. | Integrated circuit packaging system with embedded circuitry and post, and method of manufacture thereof |
JP2010021423A (ja) * | 2008-07-11 | 2010-01-28 | Tdk Corp | Ic内蔵基板及びその製造方法 |
US7923850B2 (en) * | 2008-08-26 | 2011-04-12 | Advanced Micro Devices, Inc. | Semiconductor chip with solder joint protection ring |
WO2010041621A1 (ja) * | 2008-10-06 | 2010-04-15 | 日本電気株式会社 | 機能素子内蔵基板及びその製造方法、並びに電子機器 |
TWI458400B (zh) * | 2008-10-31 | 2014-10-21 | Taiyo Yuden Kk | Printed circuit board and manufacturing method thereof |
US8354304B2 (en) * | 2008-12-05 | 2013-01-15 | Stats Chippac, Ltd. | Semiconductor device and method of forming conductive posts embedded in photosensitive encapsulant |
JP4924955B2 (ja) * | 2009-01-30 | 2012-04-25 | Tdk株式会社 | 電子部品内蔵基板、その製造方法、及びその検査方法 |
JP5477372B2 (ja) * | 2009-03-11 | 2014-04-23 | 日本電気株式会社 | 機能素子内蔵基板、及びその製造方法、並びに電子機器 |
US8026608B2 (en) | 2009-03-24 | 2011-09-27 | General Electric Company | Stackable electronic package |
US8216887B2 (en) * | 2009-05-04 | 2012-07-10 | Advanced Micro Devices, Inc. | Semiconductor chip package with stiffener frame and configured lid |
JPWO2011016555A1 (ja) | 2009-08-07 | 2013-01-17 | 日本電気株式会社 | 半導体装置とその製造方法 |
US8410376B2 (en) * | 2009-08-28 | 2013-04-02 | Ibiden Co., Ltd. | Printed wiring board and method for manufacturing the same |
DE102009029201B4 (de) | 2009-09-04 | 2019-05-09 | Robert Bosch Gmbh | Verfahren zur Herstellung eines ein mikro- oder nanostrukuriertes Bauelement umfassenden Bauteils |
US8796561B1 (en) * | 2009-10-05 | 2014-08-05 | Amkor Technology, Inc. | Fan out build up substrate stackable package and method |
US20110100692A1 (en) * | 2009-11-02 | 2011-05-05 | Roden Topacio | Circuit Board with Variable Topography Solder Interconnects |
US8937381B1 (en) | 2009-12-03 | 2015-01-20 | Amkor Technology, Inc. | Thin stackable package and method |
US8929090B2 (en) | 2010-01-22 | 2015-01-06 | Nec Corporation | Functional element built-in substrate and wiring substrate |
US8872334B2 (en) | 2010-03-23 | 2014-10-28 | Nec Corporation | Method for manufacturing semiconductor device |
US8338231B2 (en) * | 2010-03-29 | 2012-12-25 | Infineon Technologies Ag | Encapsulated semiconductor chip with external contact pads and manufacturing method thereof |
US8232138B2 (en) | 2010-04-14 | 2012-07-31 | Advanced Micro Devices, Inc. | Circuit board with notched stiffener frame |
US9735113B2 (en) * | 2010-05-24 | 2017-08-15 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming ultra thin multi-die face-to-face WLCSP |
US8105872B2 (en) | 2010-06-02 | 2012-01-31 | Stats Chippac, Ltd. | Semiconductor device and method of forming prefabricated EMI shielding frame with cavities containing penetrable material over semiconductor die |
US8097490B1 (en) | 2010-08-27 | 2012-01-17 | Stats Chippac, Ltd. | Semiconductor device and method of forming stepped interconnect layer for stacked semiconductor die |
JP2012069734A (ja) * | 2010-09-24 | 2012-04-05 | Toshiba Corp | 半導体装置の製造方法 |
US8976529B2 (en) * | 2011-01-14 | 2015-03-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lid design for reliability enhancement in flip chip package |
AT13055U1 (de) * | 2011-01-26 | 2013-05-15 | Austria Tech & System Tech | Verfahren zur integration eines elektronischen bauteils in eine leiterplatte oder ein leiterplatten-zwischenprodukt sowie leiterplatte oder leiterplatten-zwischenprodukt |
JP5540276B2 (ja) * | 2011-03-31 | 2014-07-02 | Tdk株式会社 | 電子部品内蔵基板及びその製造方法 |
US20130105975A1 (en) * | 2011-10-26 | 2013-05-02 | Rafiqul Hussain | Semiconductor chip device with thermal interface material frame |
CN103779290B (zh) * | 2012-10-26 | 2016-12-21 | 碁鼎科技秦皇岛有限公司 | 连接基板及层叠封装结构 |
US9867282B2 (en) | 2013-08-16 | 2018-01-09 | Ati Technologies Ulc | Circuit board with corner hollows |
TWI514530B (zh) * | 2013-08-28 | 2015-12-21 | Via Tech Inc | 線路基板、半導體封裝結構及線路基板製程 |
JP6761224B2 (ja) * | 2014-02-19 | 2020-09-23 | 味の素株式会社 | プリント配線板、半導体装置及び樹脂シートセット |
FR3018953B1 (fr) | 2014-03-19 | 2017-09-15 | St Microelectronics Crolles 2 Sas | Puce de circuit integre montee sur un interposeur |
JP6358431B2 (ja) | 2014-08-25 | 2018-07-18 | 新光電気工業株式会社 | 電子部品装置及びその製造方法 |
TWI582861B (zh) * | 2014-09-12 | 2017-05-11 | 矽品精密工業股份有限公司 | 嵌埋元件之封裝結構及其製法 |
KR102412612B1 (ko) | 2015-08-28 | 2022-06-23 | 삼성전자주식회사 | 패키지 기판 및 프리프레그 |
KR101787832B1 (ko) * | 2015-10-22 | 2017-10-19 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 제조 방법 및 이를 이용한 반도체 패키지 |
US9853011B2 (en) | 2016-03-29 | 2017-12-26 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure and method for manufacturing the same |
US10629519B2 (en) * | 2016-11-29 | 2020-04-21 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package and method of manufacturing the same |
DE102018200597A1 (de) * | 2018-01-15 | 2019-07-18 | Siemens Healthcare Gmbh | Trägersubstrat für eine Röntgendetektoranordnung, Röntgendetektoranordnung und Röntgengerät |
KR20220030551A (ko) | 2020-09-03 | 2022-03-11 | 삼성전자주식회사 | 반도체 패키지 |
US11848280B2 (en) * | 2020-11-25 | 2023-12-19 | ADVANCED SEMlCONDUCTOR ENGINEERING, INC. | Method for manufacturing assembly structure by using frame structure on substrate |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003347741A (ja) * | 2002-05-30 | 2003-12-05 | Taiyo Yuden Co Ltd | 複合多層基板およびそれを用いたモジュール |
JP2003347459A (ja) * | 2002-05-27 | 2003-12-05 | Nec Corp | 半導体装置搭載基板とその製造方法およびその基板検査法、並びに半導体パッケージ |
US20040188136A1 (en) * | 2003-03-26 | 2004-09-30 | Shinko Electric Industries Co., Ltd. | Method of production of multilayer circuit board with built-in semiconductor chip |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60116191A (ja) | 1983-11-29 | 1985-06-22 | イビデン株式会社 | 電子部品搭載用基板の製造方法 |
JPH0566973U (ja) * | 1992-02-04 | 1993-09-03 | 株式会社富士通ゼネラル | バンプ形成構造 |
SG76530A1 (en) | 1997-03-03 | 2000-11-21 | Hitachi Chemical Co Ltd | Circuit boards using heat resistant resin for adhesive layers |
JP3481444B2 (ja) | 1998-01-14 | 2003-12-22 | シャープ株式会社 | 半導体装置及びその製造方法 |
JP2001015638A (ja) | 1999-06-30 | 2001-01-19 | Mitsumi Electric Co Ltd | Icパッケージの基板 |
JP4251421B2 (ja) | 2000-01-13 | 2009-04-08 | 新光電気工業株式会社 | 半導体装置の製造方法 |
US6348728B1 (en) | 2000-01-28 | 2002-02-19 | Fujitsu Limited | Semiconductor device having a plurality of semiconductor elements interconnected by a redistribution layer |
EP1990832A3 (en) * | 2000-02-25 | 2010-09-29 | Ibiden Co., Ltd. | Multilayer printed circuit board and multilayer printed circuit board manufacturing method |
EP1325517A2 (en) | 2000-09-19 | 2003-07-09 | Nanopierce Technologies Inc. | Method for assembling components and antennae in radio frequency identification devices |
JP2002100696A (ja) | 2000-09-20 | 2002-04-05 | Hitachi Cable Ltd | 半導体装置及びその製造方法 |
TW511415B (en) | 2001-01-19 | 2002-11-21 | Matsushita Electric Ind Co Ltd | Component built-in module and its manufacturing method |
JP4248761B2 (ja) * | 2001-04-27 | 2009-04-02 | 新光電気工業株式会社 | 半導体パッケージ及びその製造方法並びに半導体装置 |
US6903278B2 (en) | 2001-06-29 | 2005-06-07 | Intel Corporation | Arrangements to provide mechanical stiffening elements to a thin-core or coreless substrate |
TW550997B (en) | 2001-10-18 | 2003-09-01 | Matsushita Electric Ind Co Ltd | Module with built-in components and the manufacturing method thereof |
US7474538B2 (en) * | 2002-05-27 | 2009-01-06 | Nec Corporation | Semiconductor device mounting board, method of manufacturing the same, method of inspecting the same, and semiconductor package |
FI20030293A (fi) | 2003-02-26 | 2004-08-27 | Imbera Electronics Oy | Menetelmä elektroniikkamoduulin valmistamiseksi ja elektroniikkamoduuli |
JP2004335641A (ja) * | 2003-05-06 | 2004-11-25 | Canon Inc | 半導体素子内蔵基板の製造方法 |
US6928726B2 (en) * | 2003-07-24 | 2005-08-16 | Motorola, Inc. | Circuit board with embedded components and method of manufacture |
US6864165B1 (en) | 2003-09-15 | 2005-03-08 | International Business Machines Corporation | Method of fabricating integrated electronic chip with an interconnect device |
DE102004022884B4 (de) | 2004-05-06 | 2007-07-19 | Infineon Technologies Ag | Halbleiterbauteil mit einem Umverdrahtungssubstrat und Verfahren zur Herstellung desselben |
TWI245388B (en) * | 2005-01-06 | 2005-12-11 | Phoenix Prec Technology Corp | Three dimensional package structure of semiconductor chip embedded in substrate and method for fabricating the same |
JP4526983B2 (ja) | 2005-03-15 | 2010-08-18 | 新光電気工業株式会社 | 配線基板の製造方法 |
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2005
- 2005-03-15 JP JP2005073946A patent/JP3914239B2/ja not_active Expired - Fee Related
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2006
- 2006-03-10 US US11/372,916 patent/US7884484B2/en not_active Expired - Fee Related
- 2006-03-14 KR KR1020060023432A patent/KR20060101286A/ko not_active Application Discontinuation
- 2006-03-15 TW TW095108709A patent/TWI394503B/zh not_active IP Right Cessation
- 2006-03-15 EP EP06005295A patent/EP1703558A3/en not_active Withdrawn
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Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003347459A (ja) * | 2002-05-27 | 2003-12-05 | Nec Corp | 半導体装置搭載基板とその製造方法およびその基板検査法、並びに半導体パッケージ |
JP2003347741A (ja) * | 2002-05-30 | 2003-12-05 | Taiyo Yuden Co Ltd | 複合多層基板およびそれを用いたモジュール |
US20040188136A1 (en) * | 2003-03-26 | 2004-09-30 | Shinko Electric Industries Co., Ltd. | Method of production of multilayer circuit board with built-in semiconductor chip |
Also Published As
Publication number | Publication date |
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EP1703558A2 (en) | 2006-09-20 |
JP3914239B2 (ja) | 2007-05-16 |
JP2006261246A (ja) | 2006-09-28 |
US20060208356A1 (en) | 2006-09-21 |
KR20060101286A (ko) | 2006-09-22 |
CN1835654B (zh) | 2011-06-29 |
EP1703558A3 (en) | 2010-01-20 |
US7884484B2 (en) | 2011-02-08 |
TW200640326A (en) | 2006-11-16 |
CN1835654A (zh) | 2006-09-20 |
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