TWI394503B - 佈線板及其製造方法 - Google Patents

佈線板及其製造方法 Download PDF

Info

Publication number
TWI394503B
TWI394503B TW095108709A TW95108709A TWI394503B TW I394503 B TWI394503 B TW I394503B TW 095108709 A TW095108709 A TW 095108709A TW 95108709 A TW95108709 A TW 95108709A TW I394503 B TWI394503 B TW I394503B
Authority
TW
Taiwan
Prior art keywords
wiring board
wiring
insulating layer
semiconductor wafer
manufacturing
Prior art date
Application number
TW095108709A
Other languages
English (en)
Other versions
TW200640326A (en
Inventor
Yamano Takaharu
Sunohara Masahiro
Iizuka Hajime
Koyama Tetsuya
Original Assignee
Shinko Electric Ind Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Ind Co filed Critical Shinko Electric Ind Co
Publication of TW200640326A publication Critical patent/TW200640326A/zh
Application granted granted Critical
Publication of TWI394503B publication Critical patent/TWI394503B/zh

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/8121—Applying energy for connecting using a reflow oven
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/38—Effects and problems related to the device integration
    • H01L2924/381—Pitch distance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49133—Assembling to base an electrical component, e.g., capacitor, etc. with component orienting
    • Y10T29/49135—Assembling to base an electrical component, e.g., capacitor, etc. with component orienting and shaping, e.g., cutting or bending, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths

Description

佈線板及其製造方法
本案係主張於2005年3月15日提出申請之日本專利申請案第2005－073946號之國外優先權，該案全文內容以引用方式併入本文。
本發明係關於一種佈線板之製造方法，更特別係關於結合半導體晶片之佈線板之製造方法。
目前，使用半導體裝置諸如半導體晶片的電子裝置的效能提升已經有重大進展。需要有更高密度之半導體晶片安裝於板上，安裝半導體晶片的板的尺寸縮小，以及板之空間的節省。
如此提出一種嵌入半導體晶片之板，亦即已提出之內建晶片型佈線板。曾經提出多種結合半導體晶片於板之組態(例如參考JP－A－2001－196525)。此種內建晶片型佈線板具有佈線結構連接至半導體晶片。此外，終端連接部係形成於佈線板上，讓佈線板可連接至另一裝置、主機板等。
但於內建晶片型佈線板實現厚度之縮小(減薄)且較高密度的情況下，佈線板的翹曲可能成問題。為了處理佈線板的此種翹曲問題，需要層合具有預定厚度之板諸如芯板，該板具有半導體晶片嵌入其中之一層，讓佈線板具有抑制翹曲的結構。結果於具有此種層合結構之內建晶片型佈線板中，難以實現佈線板的厚度減薄與較高密度。
此外，難以達成佈線板厚度的縮小，同時抑制佈線板的翹曲。
本發明之目的係提供一種新穎且有用之佈線板及該佈線板之製造方法，藉此來解決前述問題。
本發明中，可達成結合半導體晶片之佈線板的厚度減薄，且抑制此種佈線板的翹曲。
於若干實作中，本發明之佈線板包含：至少一個半導體晶片；其中嵌置該至少一個半導體晶片之絕緣層；連接該半導體晶片之佈線結構；以及加強該絕緣層之至少一個加強件，該加強件係嵌置於該絕緣層內部。
此種佈線板具有可抑制佈線板翹曲且縮小佈線板厚度的結構。
於本發明之佈線板中，加強件和半導體晶片實質上係安裝於相同的平面上。如此，可達成佈線板厚度的減薄。
於本發明之佈線板中，加強件係形成為環繞該半導體晶片。如此可有利地提升抑制佈線板之翹曲的效果。
於本發明之佈線板中，佈線結構具有多層佈線結構。如此可連成較高密度佈線結構。如此本實施例為優異。
於本發明之佈線板中，佈線結構包括：形成於半導體晶片之第一側上之第一佈線次結構；及形成於該半導體晶片之第二側上之第二佈線次結構。如此可達成較高密度之佈線結構。結果本實施例為優異。
於本發明之佈線板中，第一佈線次結構和第二佈線次結構係藉形成於絕緣層之通孔插塞來連接。如此可達成較高密度之佈線結構。結果本實施例為優異。
本發明之佈線板進一步包含：形成於佈線板之第一表面上之第一終端連接部，該第一終端連接部係經由該佈線結構而連接至半導體晶片；以及形成於佈線板之第二表面上之第二終端連接部，該第二終端連接部係經由該佈線結構而連接至半導體晶片。如此，終端連接部係分別於與第一表面和第二表面相應的兩側各自連接半導體晶片。
於本發明之佈線板中，加強件係由有機芯材或金屬材料製成。
於若干實作中，本發明之一種佈線板之製造方法包含：形成一下層佈線結構；安裝至少一個半導體晶片於該下層佈線結構上，該半導體晶片係連接該下層佈線結構；形成至少一個加強件；以及形成一絕緣層，讓半導體晶片和加強件係嵌置於絕緣層，該加強件可加強該絕緣層。
此種佈線板之製造方法能抑制佈線板的翹曲，且減小佈線板之厚度。
於本發明之佈線板之製造方法中，加強件和半導體晶片係安裝於實質上相同的平面上。如此可達成佈線板之厚度的減薄。
本發明之佈線板之製造方法進一步包含：形成通孔插塞於絕緣層，連接該通孔插塞至下層佈線結構；以及形成一上層佈線結構讓半導體晶片係安裝於下層佈線結構與上層佈線結構間，以及連接上層佈線結構至該通孔插塞。如此可達成較高密度的佈線結構。結果，本實施例為優異。
於本發明之佈線板之製造方法中，下層佈線結構係形成於芯板上，以及該方法進一步包含：移除芯板。如此可達成佈線板之厚度的減薄。此外，可穩定地形成佈線板。結果本實施例為優異。
於本發明之佈線板之製造方法中，芯板係由導電材料所製成，下層佈線結構之形成步驟包括使用芯板作為電極，藉電解鍍覆來形成下層佈線結構。如此有助於在進行電解鍍覆時的電力供應。如此本實施例為優異。
於本發明之佈線板之製造方法中，半導體晶片係經由形成於該半導體晶片上之釦狀凸塊而電性連接下層佈線結構。如此可提升半導體晶片與佈線結構間的連接可靠度。
本發明之佈線板之製造方法進一步包含：於釦狀凸塊與下層佈線結構間形成由焊料製造之連接部。如此，可提升半導體晶片與佈線結構間的連接的可靠度。
根據本發明，可實現結合半導體晶片之佈線板之厚度的減薄，且抑制此種佈線板的翹曲是可能的。
其次將參考附圖說明本發明之實施例如下。
[第一實施例]
圖1為剖面圖，示意顯示根據本發明之第一實施例之佈線板100。
參考圖1，根據本實施例之佈線板100包括嵌置於絕緣層103之半導體晶片109，以及連接至半導體晶片109之佈線結構。此種佈線結構具有圖案佈線106和117及通孔插塞105和116。
此外，佈線板100具有形成於其第一側之終端連接部102，以及形成於第一側所相對之第二側之終端連接部119。終端連接部102和119係經由佈線結構而連接至半導體晶片109。
至目前為止，欲減薄此種內建半導體晶片型佈線板之厚度之情況下，偶爾層合佈線板和諸如芯板之結構本體，芯板可支持佈線板且抑制佈線板的翹曲。因而難以達成佈線板之厚度的減薄及抑制翹曲二者。
如此，根據本實施例之佈線板100係組態成藉加強絕緣層103以防止翹曲的加強件112係嵌置於絕緣層103，半導體晶片109也嵌置於絕緣層103。經由使用加強件112可抑制佈線板100的翹曲。於前述結構之情況下，可有效抑制佈線板100的翹曲，而實際上並未增加佈線板100的厚度。
於圖1中，單一半導體晶片109設置於佈線板100來簡化圖式與說明。但類似安裝單一半導體晶片109之組態，也可安裝多個半導體晶片109於佈線板100。此外，於此種情況下，經由將加強件112嵌置於絕緣層103，同樣可抑制佈線板100的翹曲。
如此，比較具有絕緣層103層合用以支持絕緣層103之芯板之結構的佈線板，本實施例具有可減薄佈線板之厚度的結構。
其次，將說明佈線板100之組配的細節。舉例言之，連接至半導體晶片109之佈線結構包括例如由銅製成之圖案佈線106和117及通孔插塞105和116。此等佈線結構係連接於半導體晶片109。
例如金製成的釦狀凸塊108係形成於半導體晶片109之電極墊(圖中未顯示)上，且係經由例如焊料所製成之連接部107而電性連接至圖案佈線106。經由使用釦狀凸塊108，可提升半導體晶片109與圖案佈線106間的電氣連接的可靠度。此外，經由形成連接部107於釦狀凸塊108與圖案佈線106間，可進一步提升其間的電氣連接的可靠度。
圖案佈線106係與通孔插塞佈線105整合式形成。例如包括Au/Ni鍍覆層的終端連接部102係形成於通孔插塞佈線105連接至圖案佈線106之該側的對側上。此終端連接部102係形成為其一面係從絕緣層103暴露出。焊料抗蝕劑層120係形成為覆蓋絕緣層103且環繞終端連接部102。若有所需，焊料凸塊121形成於終端連接部102上。
例如圖案佈線117係形成於絕緣層103上，位在與圖案佈線106所形成之該側相對的半導體晶片109之一側上。圖案佈線117及106係藉通孔插塞116連接。例如，通孔插塞116與圖案佈線117係一體成形。
例如包括Au/Ni鍍覆層的終端連接部119係形成於圖案佈線117上。焊料抗蝕劑層118係形成於絕緣層103和圖案佈線117上，因而環繞終端連接部119。
例如，用於所謂的堆疊板之堆疊樹脂可用於絕緣層103。舉例言之，可使用諸如環氧樹脂或聚醯亞胺樹脂之熱硬化樹脂。
較佳地，由樹脂材料所製成的底填補層110係形成於半導體晶片109與圖案佈線106間、或形成於半導體晶片109與絕緣層103間。
佈線板100之組態成可省略例如焊料抗蝕劑層118和120及焊料凸塊121。
於根據本實施例之佈線板100中，可連接至半導體晶片109之終端連接部係分別設置於佈線板之兩側上。如此，此佈線板100係組態成欲連接其上之物件諸如其它裝置、其它半導體晶片和主機板容易連接至佈線板100之兩側上。
多種材料可用於加強件112。舉例言之，可使用比絕緣層103更硬的樹脂材料，例如為用於芯板等之有機芯材(偶爾稱作為預浸材料)、諸如Cu、Ni、Fe之金屬材料、此等金屬材料之合金材料或複合材料。
較佳地，加強件112係形成於與半導體晶片109所形成之該平面而實質上相同平面上。如此，加強件112嵌置於絕緣層103內部，而未增加絕緣層103之厚度。
根據本實施例之佈線板100可根據半導體晶片之規格和連接規格而形成為各種形狀與厚度。佈線板之實用厚度實例說明如後。
舉例言之，半導體晶片109之厚度D2設定為80微米的情況，從半導體晶片109之上端面至焊料抗蝕劑層118之距離D1為20微米。從半導體晶片109之下端面至圖案佈線106之上端面之距離D3為45微米。
焊料抗蝕劑層118之厚度d1和焊料抗蝕劑層120之厚度d5為30微米。從焊料抗蝕劑層120之上端面至圖案佈線106之下端面之距離d4為25微米。圖案佈線106之厚度d3為10微米。從圖案佈線106之上端面至焊料抗蝕劑層118之下端面之距離d2為145微米。
此種情況下，佈線板厚度(焊料凸塊121除外)係等於240微米。
圖2A示意顯示圖1所示佈線板100之平面圖。附帶地，於圖2A中，省略半導體晶片109和加強件112以外的其它元件的繪圖。如圖2A所示，加強件112係形成為環繞半導體晶片109因而例如包圍半導體晶片109。如此，可有利地提升防止翹曲的優點。附帶地，單一半導體晶片或多個半導體晶片可安裝於其上。
加強件非僅限於前述實例。例如，加強件形狀可以後文說明之多種方式改變。
圖2B和圖2C為顯示圖2A所示加強件之修改例之視圖。附帶地，前述圖2A所示的各個元件於圖2B和圖2C中係以與圖2A使用的元件符號相同的元件符號標示。如此，省略該等元件之說明。加強件可經修改成例如圖2B所示之加強件112A，其分別設置於佈線板兩側(端部)且彼此相對。另外，加強件可經修改如圖2C所示之加強件112B，其係分別設置於佈線板之角隅部附近且彼此相對。圖2C中，加強件112係形成為部分環繞多個半導體晶片。如前述，可根據半導體晶片之大小、佈線結構或佈線板的規格做出加強件之多項修改及變化。
其次，於後文將以參考圖3A至圖3O之步驟順序，循序說明根據本發明之此實施例在圖1所示佈線板100之製造方法之實例。
首先如圖3A所示，製備例如厚200微米之銅所製成的芯板101。
隨後，於圖3B所示步驟中，經由使用其上藉微影術處理而進行圖案製作之光阻圖案作為光罩，也使用芯板作為電極，藉電解鍍覆而形成例如Au/Ni所製成之終端連接部102於芯板101上。如此，於芯板101係由導電材料所製成之情況，芯板可用作為電極而用於電解鍍覆。於隨後步驟進行電解鍍覆之情況下，視需要，使用芯板作為電極(或於電解鍍覆時使用芯板作為激化路徑)。於終端連接部102形成後，光阻圖案被剝離。
隨後，於圖3C所示步驟中，樹脂材料諸如環氧樹脂所製成的絕緣層103例如係經由層合或施用等方式形成來覆蓋終端連接部102。此外，通孔103A例如使用雷射光束處理來暴露出終端連接部。也較佳於形成通孔103A後，視需要進行除污處理，其中殘餘物被去除，而絕緣層103之表面被粗化。
隨後，於圖3D所示步驟中，晶種層104例如藉無電極鍍銅而形成於絕緣層103之表面上和終端連接部102之表面上。
隨後，於圖3E所示步驟中，使用其上藉微影術進行製作圖案之光阻圖案作為光罩，藉例如電解鍍銅而形成通孔插塞，因而埋設通孔103A。此外，欲連接至通孔插塞105之圖案佈線106係與通孔插塞105整合式形成。當進行電解鍍覆完成時，剝離光阻圖案。
隨後於圖3F所示步驟中，藉蝕刻去除形成於絕緣層103上之晶種層104之不必要的部分。然後，使用形成於絕緣層103和圖案佈線106上之光阻圖案，且使用其上藉微影術進行製作圖案之光阻圖案作為光罩，藉電解鍍覆而於圖案佈線106上形成例如由焊料所製成之連接部107。
此種情況下，較佳地，鎳層係形成於連接部107與圖案佈線106間來作為障層。當電解鍍覆完成時，光阻圖案被剝離。此外，於此種情況下，連接部107之形成方法並非限於電解鍍覆。舉例言之，可採用一種方法，施用黏著劑材料於圖案佈線106上，以及施用細的焊料粉末，讓焊料粉末黏貼於黏著劑材料。
隨後，於圖3G所示步驟中，設置(安裝)半導體晶片109於圖案佈線106上。於此種情況下，例如金製成的釦狀凸塊108係設置於半導體晶片109之電極墊(圖中未顯示)上。半導體晶片109係安裝於其上，讓釦狀凸塊108變成與連接部107接觸。此時，加熱板來進行再流動焊接。如此提升釦狀凸塊108與連接部107間的連接的可靠度。
較佳地例如，樹脂材料填補於半導體晶片109與圖案佈線106間的空間、或半導體晶片109與絕緣層103間的空間，因而形成底填補層110。
隨後，於圖3H所示步驟中，例如由可熱固化環氧樹脂或可熱固化聚醯亞胺樹脂所製成之絕緣層111例如係藉層合形成而覆蓋絕緣層103、圖案佈線106和半導體晶片109之上。
絕緣層111可防止於隨後步驟設置的加強件、或圖案佈線106因加強件接觸圖案佈線106而受損。此種情況下，絕緣層111係形成為例如具有約25微米之厚度。
特別地，於絕緣層111係由與絕緣層103之材料之相同材料製成時，絕緣層103和111彼此完全一體成形。因此，於本圖及隨後各圖中，假設絕緣層103和111形成為一層絕緣層，包括絕緣層111的絕緣層103顯示為絕緣層103。
隨後，於圖3I所示步驟中，例如厚100微米且由有機芯材(預浸材料)所製成的加強件112係經由絕緣層103而設置(安裝)於圖案佈線106上。於此種情況下，諸如銅和鎳之金屬材料可用於加強件112。另外，加強件112例如可藉鍍覆法形成。
隨後，於圖3J所示步驟中，例如由可熱固化環氧樹脂或可熱固化聚醯亞胺樹脂所製成之絕緣層113係藉層合形成，因而覆蓋加強件112和半導體晶片109之上。
特別地，於絕緣層113係由與絕緣層103之材料之相同材料製成的情況，絕緣層103與113變成彼此完全一體成形。因此，於本圖及隨後各圖中，假設絕緣層103與113形成單一絕緣層，含括絕緣層113的絕緣層103顯示為絕緣層103。
隨後，於圖3K所示步驟中，藉加熱絕緣層103來進行熱固化步驟(固化步驟)。於此種情況下，加強件112係嵌置於絕緣層103。如此，因溫度改變造成的絕緣層103的翹曲程度受到壓抑，讓絕緣層103可維持有利的平坦度。
隨後，於圖3L所示步驟中，例如經由使用雷射光束於絕緣層103形成通孔114到達圖案佈線106。此外，可視需要來施行除污步驟。然後，晶種層115形成於包括通孔114之內側壁的絕緣層103上，例如藉無電極鍍銅來暴露出圖案佈線106。
隨後，於圖3M所示步驟中，使用其上藉微影術進行圖案製作的光阻圖案作為光罩，藉電解鍍銅來形成通孔插塞116因而埋設通孔114。此外，欲連接至通孔插塞116的圖案佈線117係與通孔插塞116一體成形。於進行電解鍍覆完成時，光阻圖案被剝離。此外，藉蝕刻去除形成於絕緣層103上之晶種層115不必要的部分。
隨後，於圖3N所示步驟中，焊料抗蝕劑層118係形成於圖案佈線117和絕緣層103上，讓圖案佈線117的某些部分暴露出。然後，例如由Ni/Au所製成的終端連接部119係藉無電解鍍覆而形成於暴露出的圖案佈線117之暴露部分上。
隨後，於圖30所示步驟中，例如由銅所製成之芯板101例如藉蝕刻去除。然後，如圖1所示，形成焊料抗蝕劑層120。然後，視需要，形成焊料凸塊121。如此形成佈線板100。
於本實施例中，例如由銅所製成之芯板101係藉蝕刻去除。但另外，經由製備芯板101於其上將施用黏著劑離型帶，芯板101可於欲與絕緣層103接觸之該側上設置離型層。較佳地，離型層之黏著強度藉加熱而下降。於此種情況下，如圖30所示，於從絕緣層103去除芯板101之步驟中，經由例如使用烤爐加熱整個佈線板，來從離型層剝離絕緣層103。
根據本實施例之製造方法，加強件112係於圖3I所示之步驟中設置。然後，於圖3K所示步驟中，於其中嵌置加強件112之絕緣層103上進行固化。如此，於隨後各步驟，獲得抑制絕緣層103或整片佈線板之翹曲程度的優點。特別地，比較相關方法，可更加有效抑制因溫度的升/降所造成的應力變化、及因鍍覆、除污處理、層合處理等所造成之應力變化而導致的翹曲之程度。結果，可形成平坦度高且高可靠度的佈線板。
此外，於本實施例中，例如於預定製造步驟中，佈線板100係形成於例如由銅所製成之芯板101上。如此，可抑制製造程序中的翹曲之程度。此外，於預定處理程序完成時，去除芯板101。如此可達成佈線板之厚度的減薄。
根據本發明之佈線板非僅限於前述實施例。例如，佈線結構或加強件可以多種方式修改或變化。
例如，圖4示意顯示佈線板200，其為佈線板100之修改例。
參考圖4，於本圖所示之佈線板200中，絕緣層203、終端連接部202和219、半導體晶片209、釦狀凸塊208、連接部207、底填補層210、焊料抗蝕劑層218和220、及加強件212分別係與圖1所示佈線板100之絕緣層103、終端連接部102和119、半導體晶片109、釦狀凸塊108、連接部107、底填補層110、焊料抗蝕劑層118和120、及加強件112相對應。佈線板200具有類似於佈線板100之結構的結構。
以佈線板200為例，連接於半導體晶片209的佈線結構之層數比佈線板100增加。例如，佈線板100共有兩層佈線，其中一層係設置於半導體晶片之底側，而另一層係設置於半導體晶片之頂側。佈線板200共有四層，其中兩層係設置於半導體晶片的底側，而剩下的兩層係設置於半導體晶片的頂側。
以佈線板200為例，通孔插塞205和216係連接至半導體晶片所連接的圖案佈線206。此外，通孔插塞205係連接至圖案佈線223，且圖案佈線223係連接至其上形成有終端連接部202的通孔插塞222。另一方面，圖案佈線217係連接至通孔插塞216。圖案佈線217係經由通孔插塞224而連接於圖案佈線225，於圖案佈線225上形成終端連接部219。
如此，可視需要，改變佈線之層數。
根據半導體晶片的規格和連接的規格，佈線板200可形成為多種形狀和厚度。佈線板之實際厚度的實例說明如後。
例如於半導體晶片209之厚度D5設定為80微米之情況下，從半導體晶片209之上端面至圖案佈線217之距離D4為20微米。從半導體晶片209之下端面至圖案佈線206之上端面之距離D6為45微米。
焊料抗蝕劑層218之厚度d6和焊料抗蝕劑層220之厚度d12為30微米。從焊料抗蝕劑層220之上端面至圖案佈線223之下端面之距離d11為25微米。圖案佈線223之下端面至圖案佈線206之下端面之距離d10微25微米。圖案佈線206之厚度d9為10微米。從圖案佈線206之上端面至圖案佈線217之下端面之距離d8為145微米。從圖案佈線217之下端面至焊料抗蝕劑層218之下端面之距離d7為25微米。
本例中，佈線板200之厚度(焊料凸塊除外)係等於290微米。
圖5為視圖，示意顯示佈線板200A，佈線板200A為佈線板100之另一修改例。附帶地，本圖中，前述各元件係標示以相同的參考號碼。如此，省略此等元件之說明。
參考圖5，本圖所示佈線板200A中，與加強件212相應的加強件212A也形成於半導體晶片209附近。加強件212A之總面積係大於加強件212的總面積。
此種情況下，形成通孔插塞216用之通孔部係形成於加強件212A。
如此，可視需要，對加強件和佈線結構做出多種修改與變化。
於前述實施例中，加強件係安裝於面向下型別(複晶型)佈線板，來抑制佈線板的翹曲。但另外，加強件也可安裝於面向上型別之佈線板。此外，經由安裝加強件於其中嵌置半導體晶片的絕緣層中，可有效抑制面向上佈線板的翹曲，而實際上並未增加面向上型別佈線板的厚度。
雖然係參考特定實施例說明本發明，但熟諳技藝人士未悖離如隨附之申請專利範圍所述之本發明之精髓與範圍可做出多項修改及變化。
根據本發明，能使結合半導體晶片之佈線板之厚度減薄，且此種佈線板之翹曲的抑制是有可能的。
100．．．佈線板
101．．．芯板
102．．．終端連接部
103．．．絕緣層
103A．．．通孔
104．．．晶種層
105．．．通孔插塞
106．．．圖案佈線
107．．．連接部
108．．．釦狀凸塊
109．．．半導體晶片
110．．．底填補層
111．．．絕緣層
112．．．加強件
112A．．．加強件
112B．．．加強件
114．．．通孔
115．．．晶種層
116．．．通孔插塞
117．．．圖案佈線
118．．．焊料抗蝕劑層
119．．．終端連接部
120．．．焊料抗蝕劑層
121．．．焊料凸塊
200．．．佈線板
200A．．．佈線板
201．．．芯板
202．．．終端連接部
203．．．絕緣層
204．．．晶種層
205．．．通孔插塞
206．．．圖案佈線
207．．．連接部
208．．．釦狀凸塊
209．．．半導體晶片
210．．．底填補層
211．．．絕緣層
212．．．加強件
212A．．．加強件
214．．．通孔
215．．．晶種層
216．．．通孔插塞
217．．．圖案佈線
218．．．焊料抗蝕劑層
219．．．終端連接部
220．．．焊料抗蝕劑層
221．．．焊料凸塊
222．．．通孔插塞
223．．．圖案佈線
224．．．通孔插塞
225．．．圖案佈線
圖1為剖面圖，示意顯示根據本發明之第一實施例之佈線板。
圖2A為第一視圖，顯示根據第一實施例之加強件設置方法。
圖2B為第二視圖，顯示根據第一實施例之加強件設置方法。
圖2C為第三視圖，顯示根據第一實施例之加強件設置方法。
圖3A為第一視圖，顯示根據第一實施例之佈線板之製造方法。
圖3B為第二視圖，顯示根據第一實施例之佈線板之製造方法。
圖3C為第三視圖，顯示根據第一實施例之佈線板之製造方法。
圖3D為第四視圖，顯示根據第一實施例之佈線板之製造方法。
圖3E為第五視圖，顯示根據第一實施例之佈線板之製造方法。
圖3F為第六視圖，顯示根據第一實施例之佈線板之製造方法。
圖3G為第七視圖，顯示根據第一實施例之佈線板之製造方法。
圖3H為第八視圖，顯示根據第一實施例之佈線板之製造方法。
圖3I為第九視圖，顯示根據第一實施例之佈線板之製造方法。
圖3J為第十視圖，顯示根據第一實施例之佈線板之製造方法。
圖3K為第十一視圖，顯示根據第一實施例之佈線板之製造方法。
圖3L為第十二視圖，顯示根據第一實施例之佈線板之製造方法。
圖3M為第十三視圖，顯示根據第一實施例之佈線板之製造方法。
圖3N為第十四視圖，顯示根據第一實施例之佈線板之製造方法。
圖30為第十五視圖，顯示根據第一實施例之佈線板之製造方法。
圖4為顯示圖1所示佈線板之第一修改例之視圖。
圖5為顯示圖1所示佈線板之第二修改例之視圖。
100．．．佈線板
102．．．終端連接部
103．．．絕緣層
105．．．通孔插塞
106．．．圖案佈線
107．．．連接部
108．．．釦狀凸塊
109．．．半導體晶片
110．．．底填補層
112．．．加強件
116．．．通孔插塞
117．．．圖案佈線
118．．．焊料抗蝕劑層
119．．．終端連接部
120．．．焊料抗蝕劑層
121．．．焊料凸塊

Claims (8)

  1. 一種佈線板之製造方法，該方法包含：形成一下層佈線結構於一芯板上；安裝至少一個半導體晶片於該下層佈線結構上，且將該半導體晶片連接至該下層佈線結構；形成至少一個加強件；形成一絕緣層，係該半導體晶片和加強件嵌置於絕緣層，該加強件加強該絕緣層；以及完全地移除該芯板。
  2. 如申請專利範圍第1項之佈線板之製造方法，其中該加強件和該半導體晶片係實質上安裝於一相同平面上。
  3. 如申請專利範圍第1項之佈線板之製造方法，進一步包含：形成一通孔插塞於該絕緣層，且連接該通孔插塞至該下層佈線結構；以及形成一上層佈線結構，係該半導體晶片安裝於該下層佈線結構與該上層佈線結構間，以及連接該上層佈線結構至該通孔插塞。
  4. 如申請專利範圍第1項之佈線板之製造方法，其中該芯板係由導電材料所製成，以及下層佈線結構之形成步驟包括經由使用芯板作為電極，藉電解鍍覆來形成該下層佈線結構。
  5. 如申請專利範圍第1項之佈線板之製造方法，其中該半導體晶片係經由形成於該半導體晶片上之釦狀凸塊而 電性連接至該下層佈線結構。
  6. 如申請專利範圍第5項之佈線板之製造方法，進一步包含：於該釦狀凸塊與該下層佈線結構間形成由焊料所製造之一連接部。
  7. 如申請專利範圍第1項之佈線板之製造方法，其中該絕緣層之形成步驟包括：形成一第一絕緣層而覆蓋該半導體晶片和該下層佈線結構；以及形成一第二絕緣層而覆蓋該半導體晶片和該加強件，該加強件係形成於第一絕緣層上。
  8. 如申請專利範圍第7項之佈線板之製造方法，進一步包含：藉加熱而固化該第一絕緣層和該第二絕緣層，其中該第一絕緣層和該第二絕緣層係由熱硬化樹脂材料所製成。
TW095108709A 2005-03-15 2006-03-15 佈線板及其製造方法 TWI394503B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005073946A JP3914239B2 (ja) 2005-03-15 2005-03-15 配線基板および配線基板の製造方法

Publications (2)

Publication Number Publication Date
TW200640326A TW200640326A (en) 2006-11-16
TWI394503B true TWI394503B (zh) 2013-04-21

Family

ID=36581823

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095108709A TWI394503B (zh) 2005-03-15 2006-03-15 佈線板及其製造方法

Country Status (6)

Country Link
US (1) US7884484B2 (zh)
EP (1) EP1703558A3 (zh)
JP (1) JP3914239B2 (zh)
KR (1) KR20060101286A (zh)
CN (1) CN1835654B (zh)
TW (1) TWI394503B (zh)

Families Citing this family (60)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4526983B2 (ja) 2005-03-15 2010-08-18 新光電気工業株式会社 配線基板の製造方法
JP2008084959A (ja) 2006-09-26 2008-04-10 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
JP4906462B2 (ja) * 2006-10-11 2012-03-28 新光電気工業株式会社 電子部品内蔵基板および電子部品内蔵基板の製造方法
JP2008235550A (ja) * 2007-03-20 2008-10-02 Mitsubishi Electric Corp プリント配線板、プリント配線板の製造方法、及びそれを用いた電子機器
US7498198B2 (en) * 2007-04-30 2009-03-03 International Business Machines Corporation Structure and method for stress reduction in flip chip microelectronic packages using underfill materials with spatially varying properties
US20080284047A1 (en) * 2007-05-15 2008-11-20 Eric Tosaya Chip Package with Stiffener Ring
DE102007022959B4 (de) * 2007-05-16 2012-04-19 Infineon Technologies Ag Verfahren zur Herstellung von Halbleitervorrichtungen
US7863088B2 (en) * 2007-05-16 2011-01-04 Infineon Technologies Ag Semiconductor device including covering a semiconductor with a molding compound and forming a through hole in the molding compound
JP4518114B2 (ja) * 2007-07-25 2010-08-04 Ｔｄｋ株式会社 電子部品内蔵基板及びその製造方法
JP4518113B2 (ja) * 2007-07-25 2010-08-04 Ｔｄｋ株式会社 電子部品内蔵基板及びその製造方法
JP5025399B2 (ja) * 2007-09-27 2012-09-12 新光電気工業株式会社 配線基板及びその製造方法
US7790576B2 (en) * 2007-11-29 2010-09-07 Stats Chippac, Ltd. Semiconductor device and method of forming through hole vias in die extension region around periphery of die
US20090170241A1 (en) * 2007-12-26 2009-07-02 Stats Chippac, Ltd. Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier
US8008133B2 (en) * 2008-02-11 2011-08-30 Globalfoundries Inc. Chip package with channel stiffener frame
TWI356479B (en) * 2008-03-04 2012-01-11 Advanced Semiconductor Eng Package structure with embedded die and method of
US8313984B2 (en) * 2008-03-19 2012-11-20 Ati Technologies Ulc Die substrate with reinforcement structure
JP2010010644A (ja) * 2008-05-27 2010-01-14 Toshiba Corp 半導体装置の製造方法
KR100965339B1 (ko) * 2008-06-04 2010-06-22 삼성전기주식회사 전자부품 내장형 인쇄회로기판 및 그 제조방법
JP2009302427A (ja) * 2008-06-17 2009-12-24 Shinko Electric Ind Co Ltd 半導体装置および半導体装置の製造方法
US7888184B2 (en) * 2008-06-20 2011-02-15 Stats Chippac Ltd. Integrated circuit packaging system with embedded circuitry and post, and method of manufacture thereof
JP2010021423A (ja) * 2008-07-11 2010-01-28 Tdk Corp Ｉｃ内蔵基板及びその製造方法
US7923850B2 (en) * 2008-08-26 2011-04-12 Advanced Micro Devices, Inc. Semiconductor chip with solder joint protection ring
JP5505307B2 (ja) * 2008-10-06 2014-05-28 日本電気株式会社 機能素子内蔵基板及びその製造方法、並びに電子機器
TWI458400B (zh) * 2008-10-31 2014-10-21 Taiyo Yuden Kk Printed circuit board and manufacturing method thereof
US8354304B2 (en) * 2008-12-05 2013-01-15 Stats Chippac, Ltd. Semiconductor device and method of forming conductive posts embedded in photosensitive encapsulant
JP4924955B2 (ja) * 2009-01-30 2012-04-25 Ｔｄｋ株式会社 電子部品内蔵基板、その製造方法、及びその検査方法
JP5477372B2 (ja) * 2009-03-11 2014-04-23 日本電気株式会社 機能素子内蔵基板、及びその製造方法、並びに電子機器
US8026608B2 (en) * 2009-03-24 2011-09-27 General Electric Company Stackable electronic package
US8216887B2 (en) * 2009-05-04 2012-07-10 Advanced Micro Devices, Inc. Semiconductor chip package with stiffener frame and configured lid
JPWO2011016555A1 (ja) 2009-08-07 2013-01-17 日本電気株式会社 半導体装置とその製造方法
US8410376B2 (en) * 2009-08-28 2013-04-02 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same
DE102009029201B4 (de) 2009-09-04 2019-05-09 Robert Bosch Gmbh Verfahren zur Herstellung eines ein mikro- oder nanostrukuriertes Bauelement umfassenden Bauteils
US8796561B1 (en) * 2009-10-05 2014-08-05 Amkor Technology, Inc. Fan out build up substrate stackable package and method
US20110100692A1 (en) * 2009-11-02 2011-05-05 Roden Topacio Circuit Board with Variable Topography Solder Interconnects
US8937381B1 (en) 2009-12-03 2015-01-20 Amkor Technology, Inc. Thin stackable package and method
JPWO2011089936A1 (ja) 2010-01-22 2013-05-23 日本電気株式会社 機能素子内蔵基板及び配線基板
WO2011118572A1 (ja) 2010-03-23 2011-09-29 日本電気株式会社 半導体装置の製造方法
US8338231B2 (en) * 2010-03-29 2012-12-25 Infineon Technologies Ag Encapsulated semiconductor chip with external contact pads and manufacturing method thereof
US8232138B2 (en) 2010-04-14 2012-07-31 Advanced Micro Devices, Inc. Circuit board with notched stiffener frame
US9735113B2 (en) * 2010-05-24 2017-08-15 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming ultra thin multi-die face-to-face WLCSP
US8105872B2 (en) * 2010-06-02 2012-01-31 Stats Chippac, Ltd. Semiconductor device and method of forming prefabricated EMI shielding frame with cavities containing penetrable material over semiconductor die
US8097490B1 (en) 2010-08-27 2012-01-17 Stats Chippac, Ltd. Semiconductor device and method of forming stepped interconnect layer for stacked semiconductor die
JP2012069734A (ja) * 2010-09-24 2012-04-05 Toshiba Corp 半導体装置の製造方法
US8976529B2 (en) * 2011-01-14 2015-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. Lid design for reliability enhancement in flip chip package
AT13055U1 (de) * 2011-01-26 2013-05-15 Austria Tech & System Tech Verfahren zur integration eines elektronischen bauteils in eine leiterplatte oder ein leiterplatten-zwischenprodukt sowie leiterplatte oder leiterplatten-zwischenprodukt
JP5540276B2 (ja) * 2011-03-31 2014-07-02 Ｔｄｋ株式会社 電子部品内蔵基板及びその製造方法
US20130105975A1 (en) * 2011-10-26 2013-05-02 Rafiqul Hussain Semiconductor chip device with thermal interface material frame
CN103779290B (zh) * 2012-10-26 2016-12-21 碁鼎科技秦皇岛有限公司 连接基板及层叠封装结构
US9867282B2 (en) 2013-08-16 2018-01-09 Ati Technologies Ulc Circuit board with corner hollows
TWI514530B (zh) * 2013-08-28 2015-12-21 Via Tech Inc 線路基板、半導體封裝結構及線路基板製程
JP6761224B2 (ja) * 2014-02-19 2020-09-23 味の素株式会社 プリント配線板、半導体装置及び樹脂シートセット
FR3018953B1 (fr) 2014-03-19 2017-09-15 St Microelectronics Crolles 2 Sas Puce de circuit integre montee sur un interposeur
JP6358431B2 (ja) * 2014-08-25 2018-07-18 新光電気工業株式会社 電子部品装置及びその製造方法
TWI582861B (zh) * 2014-09-12 2017-05-11 矽品精密工業股份有限公司 嵌埋元件之封裝結構及其製法
KR102412612B1 (ko) 2015-08-28 2022-06-23 삼성전자주식회사 패키지 기판 및 프리프레그
KR101787832B1 (ko) * 2015-10-22 2017-10-19 앰코 테크놀로지 코리아 주식회사 반도체 패키지 제조 방법 및 이를 이용한 반도체 패키지
US9853011B2 (en) 2016-03-29 2017-12-26 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same
US10629519B2 (en) * 2016-11-29 2020-04-21 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
DE102018200597A1 (de) * 2018-01-15 2019-07-18 Siemens Healthcare Gmbh Trägersubstrat für eine Röntgendetektoranordnung, Röntgendetektoranordnung und Röntgengerät
US11848280B2 (en) * 2020-11-25 2023-12-19 ADVANCED SEMlCONDUCTOR ENGINEERING, INC. Method for manufacturing assembly structure by using frame structure on substrate

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003347459A (ja) * 2002-05-27 2003-12-05 Nec Corp 半導体装置搭載基板とその製造方法およびその基板検査法、並びに半導体パッケージ
JP2003347741A (ja) * 2002-05-30 2003-12-05 Taiyo Yuden Co Ltd 複合多層基板およびそれを用いたモジュール
US20040188136A1 (en) * 2003-03-26 2004-09-30 Shinko Electric Industries Co., Ltd. Method of production of multilayer circuit board with built-in semiconductor chip

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60116191A (ja) 1983-11-29 1985-06-22 イビデン株式会社 電子部品搭載用基板の製造方法
JPH0566973U (ja) * 1992-02-04 1993-09-03 株式会社富士通ゼネラル バンプ形成構造
SG76530A1 (en) 1997-03-03 2000-11-21 Hitachi Chemical Co Ltd Circuit boards using heat resistant resin for adhesive layers
JP3481444B2 (ja) 1998-01-14 2003-12-22 シャープ株式会社 半導体装置及びその製造方法
JP2001015638A (ja) 1999-06-30 2001-01-19 Mitsumi Electric Co Ltd Ｉｃパッケージの基板
JP4251421B2 (ja) 2000-01-13 2009-04-08 新光電気工業株式会社 半導体装置の製造方法
US6348728B1 (en) 2000-01-28 2002-02-19 Fujitsu Limited Semiconductor device having a plurality of semiconductor elements interconnected by a redistribution layer
EP1259103B1 (en) * 2000-02-25 2007-05-30 Ibiden Co., Ltd. Multilayer printed wiring board and method for producing multilayer printed wiring board
CN1498417A (zh) 2000-09-19 2004-05-19 纳诺皮尔斯技术公司 用于在无线频率识别装置中装配元件和天线的方法
JP2002100696A (ja) 2000-09-20 2002-04-05 Hitachi Cable Ltd 半導体装置及びその製造方法
TW511415B (en) 2001-01-19 2002-11-21 Matsushita Electric Ind Co Ltd Component built-in module and its manufacturing method
JP4248761B2 (ja) * 2001-04-27 2009-04-02 新光電気工業株式会社 半導体パッケージ及びその製造方法並びに半導体装置
US6903278B2 (en) 2001-06-29 2005-06-07 Intel Corporation Arrangements to provide mechanical stiffening elements to a thin-core or coreless substrate
TW550997B (en) 2001-10-18 2003-09-01 Matsushita Electric Ind Co Ltd Module with built-in components and the manufacturing method thereof
US7474538B2 (en) * 2002-05-27 2009-01-06 Nec Corporation Semiconductor device mounting board, method of manufacturing the same, method of inspecting the same, and semiconductor package
FI20030293A (fi) 2003-02-26 2004-08-27 Imbera Electronics Oy Menetelmä elektroniikkamoduulin valmistamiseksi ja elektroniikkamoduuli
JP2004335641A (ja) * 2003-05-06 2004-11-25 Canon Inc 半導体素子内蔵基板の製造方法
US6928726B2 (en) * 2003-07-24 2005-08-16 Motorola, Inc. Circuit board with embedded components and method of manufacture
US6864165B1 (en) 2003-09-15 2005-03-08 International Business Machines Corporation Method of fabricating integrated electronic chip with an interconnect device
DE102004022884B4 (de) 2004-05-06 2007-07-19 Infineon Technologies Ag Halbleiterbauteil mit einem Umverdrahtungssubstrat und Verfahren zur Herstellung desselben
TWI245388B (en) * 2005-01-06 2005-12-11 Phoenix Prec Technology Corp Three dimensional package structure of semiconductor chip embedded in substrate and method for fabricating the same
JP4526983B2 (ja) 2005-03-15 2010-08-18 新光電気工業株式会社 配線基板の製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003347459A (ja) * 2002-05-27 2003-12-05 Nec Corp 半導体装置搭載基板とその製造方法およびその基板検査法、並びに半導体パッケージ
JP2003347741A (ja) * 2002-05-30 2003-12-05 Taiyo Yuden Co Ltd 複合多層基板およびそれを用いたモジュール
US20040188136A1 (en) * 2003-03-26 2004-09-30 Shinko Electric Industries Co., Ltd. Method of production of multilayer circuit board with built-in semiconductor chip

Also Published As

Publication number Publication date
EP1703558A2 (en) 2006-09-20
KR20060101286A (ko) 2006-09-22
CN1835654A (zh) 2006-09-20
EP1703558A3 (en) 2010-01-20
TW200640326A (en) 2006-11-16
CN1835654B (zh) 2011-06-29
US20060208356A1 (en) 2006-09-21
JP3914239B2 (ja) 2007-05-16
JP2006261246A (ja) 2006-09-28
US7884484B2 (en) 2011-02-08

Similar Documents

Publication Publication Date Title
TWI394503B (zh) 佈線板及其製造方法
US7370411B2 (en) Wiring board manufacturing method
JP5339928B2 (ja) 配線基板及びその製造方法
US7420128B2 (en) Electronic component embedded substrate and method for manufacturing the same
JP4361826B2 (ja) 半導体装置
US8797757B2 (en) Wiring substrate and manufacturing method thereof
JP4541753B2 (ja) 電子部品実装構造の製造方法
JP4551321B2 (ja) 電子部品実装構造及びその製造方法
TWI436717B (zh) 可內設功能元件之電路板及其製造方法
KR20070024374A (ko) 배선 기판의 제조 방법
JP2013030593A (ja) 半導体装置、該半導体装置を垂直に積層した半導体モジュール構造及びその製造方法
JP2006196865A (ja) 電子部品実装構造体及びその製造方法
JPWO2007043639A1 (ja) プリント配線基板及びプリント配線基板の製造方法
JP5357239B2 (ja) 配線基板、半導体装置、及び配線基板の製造方法
JP7202785B2 (ja) 配線基板及び配線基板の製造方法
JP5280032B2 (ja) 配線基板
JP2009081356A (ja) 配線基板の製造方法及び配線基板
JP4070470B2 (ja) 半導体装置用多層回路基板及びその製造方法並びに半導体装置
JP2008124247A (ja) 部品内蔵基板及びその製造方法
JP2009252942A (ja) 部品内蔵配線板、部品内蔵配線板の製造方法
JP6417142B2 (ja) 半導体装置及びその製造方法
JP2009267149A (ja) 部品内蔵配線板、部品内蔵配線板の製造方法
JP2006222257A (ja) 配線基板とその製造方法、およびそれを用いた半導体装置
JP2005340355A (ja) 配線基板
JP2002164475A (ja) 半導体装置

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees