JPWO2011016555A1 - 半導体装置とその製造方法 - Google Patents
半導体装置とその製造方法 Download PDFInfo
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- JPWO2011016555A1 JPWO2011016555A1 JP2011525952A JP2011525952A JPWO2011016555A1 JP WO2011016555 A1 JPWO2011016555 A1 JP WO2011016555A1 JP 2011525952 A JP2011525952 A JP 2011525952A JP 2011525952 A JP2011525952 A JP 2011525952A JP WO2011016555 A1 JPWO2011016555 A1 JP WO2011016555A1
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/14—Related to the order of processing steps
- H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
- H05K2203/1469—Circuit made after mounting or encapsulation of the components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
本発明は、日本国特許出願:特願2009−184997号(2009年8月7日出願)の優先権主張に基づくものであり、同出願の全記載内容は引用をもって本書に組み込み記載されているものとする。
本発明は、半導体装置に関し、特に配線基板の内部に半導体素子を内蔵した半導体装置に関する。
以下の分析は、本願発明の観点からなされたものである。
電子機器の小型化に伴い半導体装置自体の薄型化や小型化が求められている。この薄型化・小型化を実現する手段として半導体素子内蔵が検討されている。半導体素子はシリコンなどの無機材料から構成され、配線基板などに用いられる有機材料よりも小さい熱膨張係数となり、これら半導体素子を内蔵する半導体装置では反りが発生するおそれがある。さらに小型薄型とすると、配線基板部分の厚みが減少することによる剛性の低下によって、半導体素子との熱膨張率差による反りがより顕著となるばかりか、ハンドリング性が劣化することで他の部品の搭載や別基板への半導体装置の搭載が困難となる。
なお、上記の特許文献の各開示を、本書に引用をもって繰り込むものとする。本発明の全開示(請求の範囲を含む)の枠内において、さらにその基本的技術思想に基づいて、実施形態ないし実施例の変更・調整が可能である。また、本発明の請求の範囲の枠内において種々の開示要素の多様な組み合わせないし選択が可能である。
11:半導体素子
12:第2ビア
13a,13b:絶縁層
14:織布含有絶縁層
15,22:織布
16a,16b:配線層
17:ビア
18:第1ビア
19:第1電極
20:第2電極
21:ソルダーレジスト
23:電子部品
24,25:接続部
26:支持体
27:補強繊維
27a,27b:繊維
28:開口部
Claims (24)
- 1以上の半導体素子を内蔵する内蔵層と、該内蔵層の片面又は両面に1以上の配線層と絶縁層を有する半導体装置であって、
前記内蔵層が補強用繊維からなる織布を含み、
該織布が該半導体素子を内蔵する部位に開口部を有しており、
該開口部は、該補強用繊維の繊維方向が、該開口部の少なくとも一部の辺方向又は接線方向に対して、直角又は平行でない、所定の角度を有するように配置されていることを特徴とする、半導体装置。 - 前記開口部の少なくとも一辺において、前記補強用繊維の一方向の隣接する2つの露出する繊維束の間隔内に、略直交している他の方向の繊維束の露出する数が5以下であることを特徴とする、請求項1に記載の半導体装置。
- 前記開口部の少なくとも一辺において、該開口部端面と前記補強用繊維とがなす角度が、18度から72度であることを特徴とする、請求項1または2に記載の半導体装置。
- 前記開口部は、矩形状であることを特徴とする、請求項1乃至3のいずれか一に記載の半導体装置。
- 前記開口部は、辺の方向が同一である矩形を複数組み合わせた形状、又は多角形であることを特徴とする、請求項1乃至3のいずれか一に記載の半導体装置。
- 前記開口部は、円形又は楕円形であることを特徴とする、請求項1に記載の半導体装置。
- 前記補強用繊維がガラスクロスであることを特徴とする、請求項1乃至6のいずれか一に記載の半導体装置。
- 前記内蔵層の両側に形成される前記配線層をつなぐ第1ビアが、該内蔵層を貫通することを特徴とする、請求項1乃至7のいずれか一に記載の半導体装置。
- 前記内蔵層の両面に形成される前記配線層のいずれか1が、前記半導体素子と該半導体素子上に配設された第2ビアを介して電気的に接続されていることを特徴とする、請求項1乃至8のいずれか一に記載の半導体装置。
- 前記内蔵層の両面に設けられる前記絶縁層の少なくとも1つの該絶縁層に補強用繊維を有していることを特徴とする、請求項1乃至9のいずれか一に記載の半導体装置。
- 前記絶縁層が有する前記補強用繊維が織布であることを特徴とする請求項10に記載の半導体装置。
- 前記絶縁層が有する前記補強用繊維がガラスクロスであることを特徴とする請求項10に記載の半導体装置。
- 前記絶縁層と前記内蔵層のそれぞれが有する前記補強用繊維の方向が、互いに異なっていることを特徴とする請求項10乃至12のいずれか一に記載の半導体装置。
- 前記第1ビアの直径が前記第2ビアの直径より大きいことを特徴とする請求項9乃至13のいずれか一に記載の半導体装置。
- 表面に電子部品がさらに搭載されていることを特徴とする、請求項1乃至14のいずれか一に記載の半導体装置。
- 請求項1乃至14のいずれか一に記載の半導体装置が複数、積層されて構成されていることを特徴とする半導体装置。
- 1以上の半導体素子を内蔵する半導体装置の製造方法であって、
半導体素子の周囲の領域に、開口部を有する補強用織布であって、繊維方向が該開口部の少なくとも一部の辺方向又は接線方向に対して、直角又は平行でない、所定の角度を有するように配置されている補強用織布を含む内蔵層を形成する工程と、
前記半導体素子と前記内蔵層を覆うように半導体装置の両側に少なくとも1以上の配線層と絶縁層を形成する工程と、
を有することを特徴とする半導体装置の製造方法。 - 1以上の半導体素子を内蔵する半導体装置の製造方法であって、
支持体上に少なくとも1以上の配線層と絶縁層を形成する工程と、
該絶縁層上に半導体素子を設置する工程と、
該半導体素子の周囲の領域に、開口部を有する補強用織布であって、繊維方向が該開口部の少なくとも一部の辺方向又は接線方向に対して、直角又は平行でない、所定の角度を有するように配置されている補強用織布を含む内蔵層を形成する工程と、
該半導体素子と該内蔵層を覆うように少なくとも1以上の配線層と絶縁層をさらに形成する工程と、
該支持体を除去する工程と、
を有することを特徴とする半導体装置の製造方法。 - 前記支持体を除去する工程の後に、少なくとも1以上の配線層と絶縁層を形成する工程を有することを特徴とする、請求項18に記載の半導体装置の製造方法。
- 前記半導体素子の周囲の領域に補強用織布を含む内蔵層を形成する工程において、前記内蔵層に第1ビアを形成することを特徴とする、請求項17乃至19のいずれか一に記載の半導体装置の製造方法。
- 前記半導体素子と前記内蔵層を覆うように少なくとも1以上の配線層と絶縁層をさらに形成する工程において、前記内蔵層を貫通するように第1ビアを形成することを特徴とする請求項17乃至20のいずれか一に記載の半導体装置の製造方法。
- 前記半導体素子と前記内蔵層を覆うように少なくとも1以上の配線層と絶縁層をさらに形成する工程において、該配線層と前記半導体素子とを接続する第2ビアを形成する工程を含むことを特徴とする請求項17乃至21のいずれか一に記載の半導体装置の製造方法。
- 他の電子部品を搭載する工程をさらに含むことを特徴とする、請求項17乃至22のいずれか一に記載の半導体装置の製造方法。
- 請求項1乃至15のいずれか一に記載の半導体装置を複数、積層する工程を含むことを特徴とする半導体装置の製造方法。
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PCT/JP2010/063386 WO2011016555A1 (ja) | 2009-08-07 | 2010-08-06 | 半導体装置とその製造方法 |
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