JP5262188B2 - 基板 - Google Patents
基板 Download PDFInfo
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- JP5262188B2 JP5262188B2 JP2008050955A JP2008050955A JP5262188B2 JP 5262188 B2 JP5262188 B2 JP 5262188B2 JP 2008050955 A JP2008050955 A JP 2008050955A JP 2008050955 A JP2008050955 A JP 2008050955A JP 5262188 B2 JP5262188 B2 JP 5262188B2
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- H—ELECTRICITY
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- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
- H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/73201—Location after the connecting process on the same surface
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- H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
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Description
まず、本発明の第1の実施の形態に係る部品内蔵基板の構造について説明し、次いで、本発明の第1の実施の形態に係る部品内蔵基板の製造方法及び本出願の発明者による当該方法の実施例について説明する。
有機絶縁膜13が形成されていない箇所には、導電部14が複数形成されている。導電部14上には、スタッドバンプ(Stud bump)と称される凸状の外部接続端子7が形成されている。外部接続端子7は、例えば金(Au)等から構成される。半導体素子2の外部接続端子7は、コア基板1に形成された接続端子部6に接続している。
次に、本発明の第2の実施の形態について説明する。まず、本発明の第2の実施の形態に係る部品内蔵基板の構造について説明し、次いで、本発明の第2の実施の形態に係る部品内蔵基板の製造方法及び本出願の発明者による当該方法の実施例について説明する。
次に、本発明の第3の実施の形態について説明する。
有機絶縁膜13が形成されていない箇所には、導電部14が複数形成されている。導電部14上には、スタッドバンプ(Stud bump)と称される凸状の外部接続端子7が形成されている。
(付記1) 電子部品を含む基板であって、
コア基板上に配置された電子部品を囲む炭素繊維を含む樹脂を含む中間層を備えたことを特徴する基板。
(付記2) 付記1記載の基板であって、
前記電子部品の周囲には、前記コア基板を貫通する複数のスルーホールが形成されていることを特徴とする基板。
(付記3) 付記2記載の基板であって、
前記スルーホールの内壁面には絶縁性樹脂が形成されており、
前記スルーホール内において、前記絶縁性樹脂上には、配線部が形成されていることを特徴とする基板。
(付記4) 付記1記載の基板であって、
前記中間層は、前記電子部品の周囲に設けられた前記炭素繊維を含む樹脂から成る第1の部分と、
前記第1の部分の外側に設けられた絶縁材料から成る第2の部分とを含むことを特徴とする基板。
(付記5) 付記4記載の基板であって、
前記電子部品の周囲には、前記第2の部分と前記コア基板とを貫通する複数のスルーホールが形成されていることを特徴とする基板。
(付記6) 付記4又は5記載の基板であって、
前記絶縁材料は、ガラス繊維を含む樹脂であることを特徴とする基板。
(付記7) 付記6記載の基板であって、
前記ガラス繊維を含む樹脂の熱膨張率は、前記炭素繊維を含む樹脂の熱膨張率よりも大きいことを特徴とする基板。
(付記8) 付記6又は7記載の基板であって、
前記ガラス繊維を含む樹脂は、ガラス繊維材に樹脂材料を含浸させてなることを特徴する基板。
(付記9) 付記1乃至8いずれか一項記載の基板であって、
前記電子部品と前記中間層との間には、樹脂層が形成されてなることを特徴とする基板。
(付記10) 付記1乃至9に記載の基板であって、
前記炭素繊維を含む樹脂の熱膨張率は、約1乃至10ppm/℃であることを特徴とする基板。
(付記11) 付記1乃至10いずれか一項記載の基板であって、
前記炭素繊維を含む樹脂は、炭素繊維材に樹脂材料を含浸させてなることを特徴とする基板。
(付記12) 付記1乃至11いずれか一項記載の基板であって、
前記電子部品は半導体素子であることを特徴とする基板。
(付記13) 付記1乃至12いずれか一項記載の基板であって、
前記電子部品の熱膨張率は、約1乃至10ppm/℃であることを特徴する基板。
(付記14) 電子部品を含む基板の製造方法であって、
コア基板上に電子部品を実装する工程と、
前記コア基板上であって、前記電子部品の周囲に、前記電子部品の実装領域を開口したBステージ状態の炭素繊維を含む樹脂を配置及び硬化することによって中間層を形成する工程と、
前記中間層及び前記電子部品の上面と、前記コア基板の裏面とに、絶縁層を積層形成する工程と、
前記中間層と前記コア基板とにスルーホールを形成する工程と、
前記スルーホールに絶縁処理を施す工程と、
前記スルーホール内及び前記絶縁層上に配線部を形成する工程と、を含むことを特徴とする基板の製造方法。
(付記15) 電子部品を含む基板の製造方法であって、
コア基板上に電子部品を実装する工程と、
前記コア基板上であって、前記電子部品の周囲に、前記電子部品の実装領域を開口した炭素繊維を含む樹脂を配置し、前記炭素繊維を含む樹脂が設けられた箇所の外側に、中間層絶縁部を形成することによって中間層を形成する工程と、
前記中間層及び前記電子部品の上面と、前記コア基板の裏面とに、絶縁層を積層形成する工程と、
前記中間層絶縁部と、前記コア基板と、前記絶縁層とにスルーホールを形成する工程と、
前記スルーホール内及び前記絶縁層上に配線部を形成する工程と、を含むことを特徴とする基板の製造方法。
(付記16) 付記15記載の基板の製造方法であって、
前記中間層を形成する工程は、硬化状態の前記炭素繊維を含む樹脂を接着固定した後で、前記中間層絶縁部を形成することを特徴とする基板の製造方法。
(付記17) 付記15記載の基板の製造方法であって、
前記中間層を形成する工程は、
Bステージ状態の前記炭素繊維を含む樹脂を配置し、前記炭素繊維を含む樹脂の外側に前記中間層絶縁部を積層し硬化することによって中間層を形成することを特徴とする基板の製造方法。
(付記18) 付記15乃至17記載の基板の製造方法であって、
前記中間層絶縁部は、ガラス繊維を含む樹脂であることを特徴とする基板。
(付記19) 付記14乃至18いずれか一項記載の基板の製造方法であって、
前記炭素繊維を含む樹脂は、炭素繊維材に樹脂材料を含浸させてなることを特徴とする基板の製造方法。
(付記20) 付記14乃至19いずれか一項記載の基板の製造方法であって、
前記電子部品は半導体素子であることを特徴とする基板の製造方法。
2 半導体素子
3、33 中間層
4、4a、4b プリプレグ
5 配線部
9 スルーホール
10、30、300 部品内蔵基板
11 絶縁性樹脂
Claims (3)
- 電子部品を含む基板であって、
コア基板上に配置された電子部品を囲む炭素繊維を含む樹脂を含む中間層と、
前記電子部品の周囲に形成された前記コア基板を貫通する複数のスルーホールと、
前記スルーホールの内壁面に形成された絶縁性樹脂と、
前記スルーホール内において、前記絶縁性樹脂上に形成された配線部と、を備え、
前記中間層は、前記電子部品の周囲に設けられた前記炭素繊維を含む樹脂から成る第1の部分と、
前記第1の部分の外側に設けられた絶縁材料から成る第2の部分と、を含み、
前記炭素繊維を含む樹脂の熱膨張率は、1乃至10ppm/℃であることを特徴する基板。 - 請求項1記載の基板であって、
前記電子部品の周囲には、前記第2の部分と前記コア基板とを貫通する複数のスルーホールが形成されていることを特徴とする基板。 - 請求項1又は2記載の基板であって、
前記電子部品は半導体素子であることを特徴とする基板。
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JP5982760B2 (ja) * | 2011-09-07 | 2016-08-31 | 富士通株式会社 | 電子デバイス及びその製造方法 |
JP6152254B2 (ja) * | 2012-09-12 | 2017-06-21 | 新光電気工業株式会社 | 半導体パッケージ、半導体装置及び半導体パッケージの製造方法 |
JP2015028986A (ja) * | 2013-07-30 | 2015-02-12 | イビデン株式会社 | プリント配線板及びプリント配線板の製造方法 |
KR102356810B1 (ko) * | 2015-01-22 | 2022-01-28 | 삼성전기주식회사 | 전자부품내장형 인쇄회로기판 및 그 제조방법 |
US9984979B2 (en) * | 2015-05-11 | 2018-05-29 | Samsung Electro-Mechanics Co., Ltd. | Fan-out semiconductor package and method of manufacturing the same |
US10199337B2 (en) | 2015-05-11 | 2019-02-05 | Samsung Electro-Mechanics Co., Ltd. | Electronic component package and method of manufacturing the same |
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