CN101546740B - 嵌入式印刷电路板及其制造方法 - Google Patents

嵌入式印刷电路板及其制造方法 Download PDF

Info

Publication number
CN101546740B
CN101546740B CN2008101330323A CN200810133032A CN101546740B CN 101546740 B CN101546740 B CN 101546740B CN 2008101330323 A CN2008101330323 A CN 2008101330323A CN 200810133032 A CN200810133032 A CN 200810133032A CN 101546740 B CN101546740 B CN 101546740B
Authority
CN
China
Prior art keywords
wiring layer
chip
articulamentum
pad
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2008101330323A
Other languages
English (en)
Other versions
CN101546740A (zh
Inventor
朴珖秀
郑明根
杨德缜
边大亭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electro Mechanics Co Ltd
Original Assignee
Samsung Electro Mechanics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electro Mechanics Co Ltd filed Critical Samsung Electro Mechanics Co Ltd
Publication of CN101546740A publication Critical patent/CN101546740A/zh
Application granted granted Critical
Publication of CN101546740B publication Critical patent/CN101546740B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251—Disposition
    • H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
    • H05K2203/1469—Circuit made after mounting or encapsulation of the components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

本发明涉及一种嵌入式印刷电路板及其制造方法。本发明提供了一种嵌入式印刷电路板，其包括：衬底，其中，在预定部分中形成空腔以及在没有空腔的部分中形成布线层；芯片，插入到空腔中并具有多个焊盘；填料，填充在芯片和空腔之间以固定芯片；以及连接层，形成在布线层和焊盘之间以使布线层和焊盘彼此连接。另外，本发明提供了一种制造嵌入式印刷电路板的方法。

Description

嵌入式印刷电路板及其制造方法
相关申请的交叉参考
本申请要求于2008年3月25日向韩国知识产权局提交的第10-2008-0027371号韩国专利申请的优先权，通过引证其公开的内容结合于此。
技术领域
本发明涉及嵌入式印刷电路板及其制造方法；并且更具体的，涉及通过在布线层和焊盘之间形成连接层来使布线层和焊盘彼此直接连接的嵌入式印刷电路板，及其制造方法。
背景技术
近年来，根据对电子设备高性能和小型化的需求，电子部件表现出了高密度和高性能特性。因此，对其上可高密度安装电子部件的小型化印刷电路板的需求逐渐增加。根据这样的需求，已经开发出了经由过孔使形成在不同层上的导线电连接或使电子部件和导线彼此电连接的多层电路板。
多层电路板具有缩短使多个电子部件彼此连接的导线和实现高密度布线的优点。另外，多层电路板通过安装多个电子部件扩展了印刷电路板的表面积并具有良好的电学特性。
特别的，在嵌入有电子部件的嵌入式印刷电路板中，由于电子部件不是安装于板上，而是嵌入到板的内部，所以可以实现板的小型化、高密度、以及高性能等，由此，对嵌入式印刷电路板的需求逐渐增加。
发明内容
本发明的一个优点在于提供了一种在布线层和焊盘之间形成连接层以使布线层和焊盘彼此直接电连接从而减少电路板层数的嵌入式电路板，及其制造方法。
为实现上述优点，根据本发明的一个方面，嵌入式电路板包括：衬底，在其预定部分中形成空腔并在没有空腔的部分中形成布线层；芯片，嵌入在空腔中并包括多个焊盘；填料，填充在芯片和空腔之间以固定芯片；以及连接层，形成在布线层和焊盘之间以使布线层和焊盘彼此连接。
此处，连接层可连接到位于芯片最外面部分中的焊盘。
连接层可在填料上将布线层和焊盘水平地彼此连接。
连接层可由铜(Cu)或银(Ag)制成。
连接层可形成在衬底的一个表面或两个表面上。
芯片可为选自由有源元件、无源元件、以及IC(集成电路)构成的组中的任意一个。
为实现上述优点，根据本发明的一个方面，制造嵌入式印刷电路板的方法包括以下步骤：(a)在具有布线层的衬底的预定部分形成空腔；(b)在衬底的一个表面上附上黏结片；(c)将具有多个焊盘的芯片插入到空腔中以将插入的芯片固定到黏结片上；(d)在空腔和芯片之间填充填料；以及(e)在布线层和焊盘之间形成连接到布线层和焊盘的连接层。
此处，连接层可连接到位于芯片最外面部分的焊盘。
连接层可在填料上使布线层和焊盘水平地彼此连接。
连接层可由铜(Cu)或银(Ag)制成。
芯片可以是选自由有源元件、无源元件、以及IC(集成电路)构成的组中的任意一个。
为实现上述优点，根据本发明的另一个方面，制造嵌入式印刷电路板的方法包括以下步骤：(a)在具有布线层的衬底的预定部分形成空腔；(b)在衬底的一个表面上附上黏结片；(c)将具有多个焊盘的芯片插入到空腔中以将插入的芯片固定到粘结片上；(d)在空腔和芯片之间填充填料；(e)在布线层和焊盘之间形成连接到布线层和焊盘的连接层；(f)去除黏结片；(g)在通过去除黏结片而露出的衬底和芯片上另外分别形成布线层和焊盘；以及(h)在另外形成的布线层和焊盘之间形成连接到另外形成的布线层和焊盘的第二连接层。
此处，第二连接层可连接到位于芯片最外面部分中的焊盘。
第二连接层在填料上使布线层和焊盘水平地彼此连接。
第二连接层可由铜(Cu)或银(Ag)制成。
附图说明
通过以下结合附图对实施例的描述，本发明的总发明构思的这些和/或其它方面和优点将变得显而易见，并更容易理解，附图中：
图1为示出根据本发明实施例的嵌入式印刷电路板的结构的截面图；
图2为示出根据本发明另一实施例的嵌入式印刷电路板的结构的截面图；
图3到图11为顺序示出用于描述根据本发明实施例的制造嵌入式印刷电路板的方法的工艺截面图；
图12为根据本发明的实施例的嵌入式印刷电路的平面图；以及
图13到图16为顺序示出用于描述根据本发明另一实施例的制造嵌入式印刷电路板的方法的工艺截面图。
具体实施方式
现在将详细参照本发明总的发明构思的实施例，附图中示出了本发明的总的发明构思的实例，其中，通篇中相同的参考标号表示相同的元件。以下通过参照附图描述实施例以解释本发明的总的发明构思。
嵌入式印刷电路板结构的实施例
首先，将参照图1，对根据本发明实施例的嵌入式印刷电路板进行详细描述。
图1为示出根据本发明实施例的嵌入式印刷电路板结构的截面图。
如图1所示，根据本发明实施例的嵌入式印刷电路板包括：衬底10，具有形成在预定部分中的空腔15；芯片20，插入到空腔15中并具有多个焊盘21；以及填料25，填充在芯片20和空腔15之间以固定芯片20。
衬底10可由诸如环氧树脂或玻璃的加强型基底材料制成。
布线层11形成在衬底10上没有形成空腔15的部分中。布线层11可通过堆叠铜箔等形成在衬底10上。
形成衬底10的空腔15的方法可为诸如压制、钻孔、激光处理等多种方法中的一种。在这些方法中，优选的，另外执行去除在通过压制或钻孔形成空腔15时产生的污渍的表面去污处理。
芯片20可以是有源元件、无源元件、或IC(集成电路)。
填料25通常可由树脂、环氧树脂、半固化片等制成。具体的，在本发明的实施例中，用于连接布线层11和焊盘21的连接层30形成于衬底10的布线层11和芯片20的焊盘21之间。连接层30可由铜(Cu)、银(Ag)等制成。
如图所示，连接层30连接到位于芯片20最外面部分中的焊盘21以使最外面的焊盘21和布线层11彼此直接连接。
此时，优选的，连接层30形成在填料25上以使布线层11和焊盘21水平地彼此连接。
设置有过孔40的用于扇出除最外面的焊盘21外的其余焊盘21的第一和第二隔离层35和50，以及内层导线40和导体45的连接线顺序堆叠在包括形成在其上的连接层30的衬底10上。
根据本发明实施例的嵌入式印刷电路板具有这样的结构：其中，连接层30形成在衬底10的布线层11和芯片20的焊盘21之间，以及芯片20的最外面部分中的焊盘21在同一层上扇出。不需要另外形成包括用于扇出最外面的焊盘21的过孔的层。
因此，根据本发明的实施例，可以省略用于扇出最外面的焊盘21的一层的隔离层形成工艺、过孔形成工艺、以及导体形成工艺，通过降低电路板上的总层数，可使电路板变薄。因此，可以减少工艺数量和制造成本。
此处，如图1所示，使布线层11和焊盘21彼此连接的连接层30可形成在衬底10的一个表面上或如图2所示，连接层30可形成在衬底10的两个表面上。
图2为示出根据本发明另一实施例的嵌入式印刷电路板的结构的截面图。
如图2所示，根据本发明另一实施例的嵌入式印刷电路板的大部分结构与嵌入式印刷电路板相同。然而，根据本发明另一实施例的嵌入式印刷电路板与嵌入式印刷电路板不同之处在于布线层11和焊盘21不是只形成在衬底10和芯片20中的每一个的一个表面上，而是布线层11和焊盘21形成在衬底10和芯片20的两个表面(即，上表面和下表面两个表面)上，以及连接层30和连接层31形成在形成于衬底10和芯片20中的每一个的两个表面上的布线层11和焊盘21之间。
如根据本发明另一实施例所述，在连接层30和31形成在衬底10的两个表面上时，可以省略衬底10的上表面和下表面的隔离层形成工艺、过孔形成工艺、以及导体形成工艺。
嵌入式印刷电路板制造方法的实施例
参照图3到图11，将详细描述根据本发明实施例的嵌入式电路板的制造方法。
图3到图11为顺序示出用于描述根据本发明实施例的制造嵌入式印刷电路板的方法的工艺截面图。
如图3所示，首先，在衬底10的预定部分中形成空腔15。在衬底10上设置布线层11。
衬底10可由诸如环氧树脂或玻璃的加强型基底材料制成。布线层11可由铜箔等制成。
空腔15可通过诸如压制、钻孔、激光处理等各种方法形成。此时，另外执行去除在通过压制或钻孔方法形成空腔15时产生的污渍的表面去污处理。
接下来，如图4所示，将黏结片1附到衬底10的一个表面上。此后，具有多个焊盘21的芯片20被插入到空腔15中并固定到黏结片1上。
黏结片1用于固定插入到空腔15中的芯片20。可将传统的双面胶带用作黏结片1。
芯片20可以是有源元件、无源元件、或IC(集成电路)。
此后，如图5所示，将填料25填充到空腔15和芯片20之间。填料25通常可由树脂、环氧树脂、半固化片等制成。
如图6所示，用于连接布线层11和焊盘21的连接层30形成在布线层11和芯片20的焊盘21之间。连接层30可由铜(Cu)、银(Ag)等制成。连接层30可通过镀或丝网印刷形成。
如图所示，连接层30连接到位于芯片20中最外面部分中的焊盘21以使最外面的焊盘21和布线层11彼此直接连接。此时，优选的，连接层30形成在填料25上以使布线层11和焊盘21水平地彼此连接。
在根据本发明的实施例中，芯片20的最外面的焊盘21通过连接层30在同一层上直接扇出。所以，不需要另外形成具有用于扇出最外面的焊盘21的过孔的隔离层。
接下来，如图7所示，第一隔离层35形成在连接层30上。
此后，如图8所示，去除黏结片1并且甚至在没有黏结片1的衬底10上形成第一隔离层35。
如图9所示，通过去除第一隔离层35的一部分形成过孔40。此处，可形成过孔40用于除最外面的焊盘21之外的其它焊盘21的扇出以及内层导线的连接。
接下来，如图10所示，导电层45形成在具有过孔40的第一隔离层35上。
此后，如图11所示，第二隔离层50形成在具有导电层45的第一隔离层35上。此时，尽管图中未示出，但是过孔和导体可形成在第二隔离层50上。
图12为根据本发明实施例的嵌入式印刷电路的平面图。
在根据本发明的实施例中，如图12所示，芯片20的最外面的焊盘21可通过连接层30直接在同一层上扇出，以及除最外面的焊盘21之外的其它焊盘21可通过导电层45扇出。
因此，通过根据本发明实施例的嵌入式印刷电路板的制造方法，由于可以省略用于扇出最外的焊盘21的一层的隔离层形成工艺、过孔形成工艺、以及导体形成工艺，所以通过减少板上的总层数来使电路板变薄以及减少工艺数量和制造成本成为可能。
接下来，将参照图13到图16，对根据本发明的另一实施例的嵌入式印刷电路的制造方法进行详细描述。
图13到图16为顺序示出用于描述根据本发明另一实施例的制造嵌入式印刷电路板的方法的工艺截面图。在下文中，将省略与上述实施例重叠的内容(即，从在衬底10中形成空腔15的步骤(见图3)到形成第一隔离层35的步骤(见图7))的描述。
在如图7所示形成第一隔离层35后，如图13所示，去除形成在衬底10的一个表面上的黏结片1。
此后，如图14所示，在通过去除黏结片1而露出的衬底10上和芯片20上另外形成布线层11和焊盘21，然后在另外形成的布线层11和焊盘21之间形成连接到另外形成的布线层11和焊盘21的第二连接层31。
第二连接层31可连接到位于芯片20的最外面部分中的焊盘21。优选的，第二连接层31形成在填料25上以使布线层11和焊盘21水平地彼此连接。
第二连接层31可由铜(Cu)、银(Ag)等制成。
接下来，如图15所示，在第一隔离层35形成在具有第二连接层31的衬底10上之后，通过去除第一隔离层35的一部分形成过孔40。
此后，导电层45和第二隔离层50顺序位于其中形成有过孔40的第一隔离层35上。此时，尽管在图中未示出，但过孔和导体甚至可形成在第一隔离层50上。
通过根据本发明另一实施例的嵌入式印刷电路板的制造方法，通过在衬底10的上部和下部形成连接层30和31，使得可能省略用于形成在芯片20的上部和下部的最外面的焊盘21的扇出的上表面和下表面两者的隔离层形成工艺、过孔形成工艺、以及导体形成工艺。
如上述，通过根据本发明嵌入式印刷电路板及其制造方法，连接到布线层和最外面的焊盘的连接层形成在布线层和最外面的焊盘之间，以及芯片的最外面的焊盘通过连接层直接在同一层上扇出，从而可以省略用于最外面焊盘的扇出的隔离层形成工艺、过孔形成工艺、以及导体形成工艺。
因此，根据本发明，使得通过减少板的层数量来使电路板变薄以及减少工艺数量和制造成本成为可能。
所披露的本发明的上述优选实施例用于示例说明的目的，以及本领域技术人员应该理解，在不背离本发明总的构思的原则和精神的条件下，可以对这些实施例进行更改，本发明的总的发明构思的范围由所附的权利要求及其等同物限定。

Claims (14)

1.一种嵌入式印刷电路板，包括：
衬底，其中，在预定部分中形成空腔，以及在没有所述空腔的部分中形成布线层；
芯片，插入到所述空腔中并包括多个焊盘；
填料，填充在所述芯片和所述空腔之间以固定所述芯片；以及
连接层，形成在所述布线层和所述多个焊盘之间，用于在所述填料上使所述布线层和所述多个焊盘水平地彼此连接。
2.根据权利要求1所述的嵌入式印刷电路板，其中，所述连接层连接到位于所述芯片最外面部分中的焊盘。
3.根据权利要求1所述的嵌入式印刷电路板，其中，所述连接层由铜(Cu)或银(Ag)制成。
4.根据权利要求1所述的嵌入式印刷电路板，其中，所述连接层形成在所述衬底的一个表面或两个表面上。
5.根据权利要求1所述的嵌入式印刷电路板，其中，所述芯片为选自由有源元件、无源元件、以及IC(集成电路)构成的组中的任意一个。
6.一种制造嵌入式印刷电路板的方法，所述方法包括以下步骤：
(a)在具有布线层的衬底的预定部分中形成空腔；
(b)在所述衬底的一个表面上附上黏结片；
(c)将具有多个焊盘的芯片插入到所述空腔中以将插入的所述芯片固定到所述黏结片上；
(d)在所述空腔和所述芯片之间填充填料；以及
(e)在所述布线层和所述多个焊盘之间形成连接到所述布线层和所述多个焊盘的连接层。
7.根据权利要求6所述的方法，其中，所述连接层连接到位于所述芯片最外面部分中的焊盘。
8.根据权利要求6所述的方法，其中，所述连接层在所述填料上使所述布线层和所述多个焊盘水平地彼此连接。
9.根据权利要求6所述的方法，其中，所述连接层由铜(Cu)或银(Ag)制成。
10.根据权利要求6所述的方法，其中，所述芯片为选自由有源元件、无源元件、以及IC(集成电路)构成的组中的任意一个。
11.一种制造嵌入式印刷电路板的方法，所述方法包括以下步骤：
(a)在具有布线层的衬底的预定部分中形成空腔；
(b)在所述衬底的一个表面上附上黏结片；
(c)将具有多个焊盘的芯片插入到所述空腔中以将插入的所述芯片固定到所述黏结片上；
(d)在所述空腔和所述芯片之间填充填料；
(e)在所述布线层和所述多个焊盘之间形成连接到所述布线层和所述多个焊盘的连接层；
(f)去除所述黏结片；
(g)在通过去除所述黏结片而露出的所述衬底上和所述芯片上另外分别形成布线层和多个焊盘；以及
(h)在另外形成的所述布线层和所述多个焊盘之间形成连接到另外形成的所述布线层和所述多个焊盘的第二连接层。
12.根据权利要求11所述的方法，其中，所述第二连接层连接到位于所述芯片最外面部分中的焊盘。
13.根据权利要求11所述的方法，其中，所述第二连接层在所述填料上使另外形成的所述布线层和另外形成的所述多个焊盘水平地彼此连接。
14.根据权利要求11所述的方法，其中，所述第二连接层由铜(Cu)或银(Ag)制成。
CN2008101330323A 2008-03-25 2008-07-04 嵌入式印刷电路板及其制造方法 Expired - Fee Related CN101546740B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR1020080027371A KR100972431B1 (ko) 2008-03-25 2008-03-25 임베디드 인쇄회로기판 및 그 제조방법
KR10-2008-0027371 2008-03-25
KR1020080027371 2008-03-25

Publications (2)

Publication Number Publication Date
CN101546740A CN101546740A (zh) 2009-09-30
CN101546740B true CN101546740B (zh) 2011-09-14

Family

ID=41115399

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2008101330323A Expired - Fee Related CN101546740B (zh) 2008-03-25 2008-07-04 嵌入式印刷电路板及其制造方法

Country Status (3)

Country Link
US (1) US8418356B2 (zh)
KR (1) KR100972431B1 (zh)
CN (1) CN101546740B (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102010018499A1 (de) 2010-04-22 2011-10-27 Schweizer Electronic Ag Leiterplatte mit Hohlraum
CN102256450A (zh) * 2010-05-20 2011-11-23 深南电路有限公司 埋入式无源器件的电路板及其制造方法
AT515101B1 (de) * 2013-12-12 2015-06-15 Austria Tech & System Tech Verfahren zum Einbetten einer Komponente in eine Leiterplatte
SG10201400390YA (en) * 2014-03-05 2015-10-29 Delta Electronics Int L Singapore Pte Ltd Package structure

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1494277A2 (en) * 2003-07-03 2005-01-05 Matsushita Electric Industrial Co., Ltd. Module with a built-in semiconductor and method for producing the same
CN1577813A (zh) * 2003-07-22 2005-02-09 松下电器产业株式会社 电路模块及其制造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6309912B1 (en) * 2000-06-20 2001-10-30 Motorola, Inc. Method of interconnecting an embedded integrated circuit
JP2002237683A (ja) 2001-02-08 2002-08-23 Ngk Spark Plug Co Ltd 配線基板の製造方法
TW546800B (en) * 2002-06-27 2003-08-11 Via Tech Inc Integrated moduled board embedded with IC chip and passive device and its manufacturing method
KR100704936B1 (ko) * 2005-06-22 2007-04-09 삼성전기주식회사 전자부품 내장 인쇄회로기판 및 그 제작방법
KR100762758B1 (ko) * 2006-03-09 2007-10-02 삼성전기주식회사 전자소자 내장형 인쇄회로기판 및 그 제조 방법
KR100796523B1 (ko) 2006-08-17 2008-01-21 삼성전기주식회사 전자부품 내장형 다층 인쇄배선기판 및 그 제조방법
KR100827315B1 (ko) * 2006-09-19 2008-05-06 삼성전기주식회사 전자소자 내장 인쇄회로기판 제조방법

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1494277A2 (en) * 2003-07-03 2005-01-05 Matsushita Electric Industrial Co., Ltd. Module with a built-in semiconductor and method for producing the same
CN1577813A (zh) * 2003-07-22 2005-02-09 松下电器产业株式会社 电路模块及其制造方法

Also Published As

Publication number Publication date
KR20090102119A (ko) 2009-09-30
KR100972431B1 (ko) 2010-07-26
CN101546740A (zh) 2009-09-30
US8418356B2 (en) 2013-04-16
US20090242251A1 (en) 2009-10-01

Similar Documents

Publication Publication Date Title
US20180352658A1 (en) Component embedded package carrier and manufacturing method thereof
US9226382B2 (en) Printed wiring board
KR101077410B1 (ko) 방열부재를 구비한 전자부품 내장형 인쇄회로기판 및 그 제조방법
EP0851724B1 (en) Printed circuit board and electric components
EP1864558B1 (en) Multilayer circuit board with embedded components and method of manufacture
US9999141B2 (en) Printed circuit board and method for manufacturing the same
JP5097827B2 (ja) フレックスリジッド配線板及び電子デバイス
US20060284640A1 (en) Structure of circuit board and method for fabricating the same
US9288910B2 (en) Substrate with built-in electronic component and method for manufacturing substrate with built-in electronic component
KR101067199B1 (ko) 인쇄회로기판 및 그 제조방법
KR101516072B1 (ko) 반도체 패키지 및 그 제조 방법
KR20100096274A (ko) 배선판과 그 제조 방법
JP5989814B2 (ja) 埋め込み基板、印刷回路基板及びその製造方法
KR100747022B1 (ko) 임베디드 인쇄회로기판 및 그 제작방법
KR20150064976A (ko) 인쇄회로기판 및 그 제조방법
JP4497548B2 (ja) 配線基板
US10182494B1 (en) Landless via concept
CN101546740B (zh) 嵌入式印刷电路板及其制造方法
JP5599860B2 (ja) 半導体パッケージ基板の製造方法
KR100757907B1 (ko) 인쇄회로기판 및 그 제조방법
KR102052761B1 (ko) 칩 내장 기판 및 그 제조 방법
JP2011222962A (ja) プリント基板およびその製造方法
KR101147343B1 (ko) 복수의 소자가 내장된 집적 인쇄회로기판 및 그 제조 방법
KR101396837B1 (ko) 반도체 칩 내장형 인쇄회로기판 및 그의 제조 방법
US20170339788A1 (en) Split via second drill process and structure

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20110914

Termination date: 20190704