CN101636831A - 用于改善的机械和热机械性能的焊料凸点互连 - Google Patents

用于改善的机械和热机械性能的焊料凸点互连 Download PDF

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CN101636831A
CN101636831A CN200880002933A CN200880002933A CN101636831A CN 101636831 A CN101636831 A CN 101636831A CN 200880002933 A CN200880002933 A CN 200880002933A CN 200880002933 A CN200880002933 A CN 200880002933A CN 101636831 A CN101636831 A CN 101636831A
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ubm
polymer
semiconductor packages
outer peripheral
central authorities
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CN101636831B (zh
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雷南特·阿尔瓦拉多
陆原
理查德·雷德本
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Huatian Technology Kunshan Electronics Co Ltd
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FlipChip International LLC
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Abstract

一种用于包括输入－输出(IO)上凸点结构的半导体封装的设备和方法被披露，其中涉及器件焊盘、凸点下金属焊盘(UBM)、聚合物、及钝化层。从器件焊盘的中央到其外边缘的最短距离与从UBM的中央到其外边缘的最短距离的比值从0.5∶1到0.95∶1。此外，从聚合物的中央到其外边缘的最短距离与从UBM的中央到其外边缘的最短距离的比值从0.35∶1到0.85∶1。此外，从钝化层的中央到其外边缘的最短距离与从UBM的中央到其外边缘的最短距离的比值从0.35∶1到0.80∶1。

Description

用于改善的机械和热机械性能的焊料凸点互连
相关申请
本申请要求2007年4月23日提交的序列号为60/913,337的美国临时申请和2008年4月21日提交的序列号为12/107,009的美国非临时申请的优先权和权益，通过参考的方式将两者全文结合于此。序列号为60/913,337的美国临时申请涉及2005年10月28日提交的序列号为PCT/US05/39008的PCT专利申请，通过参考的方式将其全文结合于此。PCT/U505/39008涉及并要求2004年10月28日提交的序列号为60/623,200的美国临时专利申请的权益，通过参考的方式将其全文结合于此。
本申请包括受到版权保护的资料。当该资料出现在专利和商标局的文件或记录中时，版权所有人不反对任何人对专利公开文件进行传真复制，但是在其他情况中无论如何都将保留所有的版权。
技术领域
本直接公开涉及电子晶片级芯片规模封装和倒装芯片封装以及装配领域，更具体地，提供了具有改善的机械强度和抗冲击性的焊料凸点互连结构。
背景技术
传统上，丝焊用来提供半导体器件和外部电路之间的电连接。从晶片将半导体器件切成小方块，在晶片上加工半导体器件并在封装中将半导体器件放置为面朝上。然后，较小的引线(典型地由金或铜制成)被焊接在封装上的外部导线和半导体器件上所存在的焊盘(bond pad)之间。
倒装芯片技术的名字来源于在封装中将半导体器件面朝下放置。封装的外部导线和半导体器件之间的电连接是通过在半导体器件的表面上回流导电焊料凸点制成的。
倒装芯片技术允许制成大量的电连接，这是因为可以使用半导体器件的整个区域来形成焊盘，尽管在引线键合中焊盘被典型地形成在半导体器件的周围。倒装芯片技术还有利于通过消除与丝焊相关联的电容和阻抗来加速半导体器件和外部电路之间的电连接。
晶片级芯片规模封装(“WLCSP”)或晶片级封装(“WLP”)通过在加工半导体器件期间直接在半导体器件上形成电连接而推进了倒装芯片的概念。这允许半导体器件被直接安装到印刷电路板(“PCB”)上，从而消除了单独封装的需要。所得到的被封装器件大小类似于裸的半导体器件。WLCSP的实现还得益于电性能的提高以及更小的封装大小。该工业中从利用铅冶金学的焊接到WLCSP的无铅冶金学的转变已导致了用于高可靠性芯片封装的对热循环和突然机械冲击效应的更高敏感性。
再分布层(“RDL”)技术允许其中焊盘被定位于器件周围的较早的半导体器件设计使用WLCSP。RDL建立了焊料凸点和半导体器件上的焊盘之间的电路径，允许焊料凸点被均匀地分布在半导体器件的整个区域上。
图1示出了在形成焊料凸点之前器件焊盘(device pad)上的现有技术的IO上凸点(bump on IO)结构，以及图2a示出了在应用了焊料凸点106之后图1的现有技术IO上凸点结构。该器件由衬底101、器件焊盘102、以及钝化层103构成。器件焊盘102是金属材料，典型地包括铝、铜、或这两者的合成物。器件焊盘102可以利用工业中已知的多种方法中的任意方法来形成。衬底101可以包括诸如硅、砷化镓、钽酸锂、锗化硅等的材料。为了简化，在本文中衬底材料一般被称作硅，但是其使用不应当被解释为旨在仅将本公开文件限制为基于硅的衬底。
器件钝化层103典型地包括氮化硅、氧化物氮化物等。钝化层103在器件焊盘上不是连续的，而是具有限定的开口，在开口处没有钝化材料，多个开口单独地被称作钝化开口。在图2中更详细地示出了钝化开口，其提供了图1的IO上凸点结构的俯视图。钝化开口一般为圆形并且位于器件焊盘102中部。钝化开口限定了一个区域，在该区域中将在WLCSP处理或倒装芯片封装处理中沉积随后的金属以制作连接并粘附到器件焊盘上。
用于放置下层IO上凸点结构的现有技术(如图1和图2所示的)由以下步骤构成：使用标准的金属沉积方法(诸如金属电镀、金属喷涂等)形成凸点下金属焊盘(“UMB”)105。UMB 105可以包括多种已知材料中的任意种，包括Ti(W)/Cu、Al/无电镀Ni/浸Au、Al/无电镀Ni/PdlAu、AlCu/无电镀Ni/浸Au、AlCuSi/无电镀Ni/浸Au、以及AlSi/无电镀Ni/浸Au。由于所使用的技术和材料，UMB 105可以粘附于钝化材料103和器件焊盘102，并且典型地形成约1.0微米或更厚的层。UBM 105的上表面提供了焊料凸点放置位置并有利于其粘附。在图1和图2中，UBM焊料凸点位置被聚合体104中的开口所限定。
传统的现有技术处理利用了由聚酰亚胺、苯环丁烯(“BCB”)等构成的聚合物材料。聚合物104的厚度典型地为10微米或更小。聚合物104典型地被光限定以建立开口，开口一般为圆形并且位于UBM 105中部。在该实例中以及在大多数的传统现有技术焊料凸点结构中，器件焊盘102的直径大于或等于UBM 105的直径，导致1∶1或更大的比值。在这种传统现有技术焊料凸点结构中，聚合物204中的开口的直径典型地小于UBM 105的直径，具有0.86∶1或更小的比值。
图3和图4分别示出了可选的现有技术IO上凸点结构的截面图和俯视图。在该现有技术版本中，器件焊盘302的直径小于UBM305的直径，具有典型的比值0.43∶1。该聚合物开口直径小于UBM305的直径，具有典型的比值0.32∶1。用于放置诸如图3和图4所示的下层结构的现有技术由以下步骤构成：将聚合物304放置在器件钝化层303中的开口之上以及器件焊盘302之上，其中，聚合物诸如聚酰亚胺、苯并环丁烯、聚苯并噁唑、聚苯并噁唑的衍生物等。聚合物304的厚度典型地为10微米或更小。然后聚合物304被光限定以建立开口，该开口一般为圆形并且位于器件钝化开口中部上，并且开口到器件焊盘302的表面。
在该处理的该点处，聚合物304已经限定了一个连接到器件钝化层303并且落在器件钝化层303的开口内的区域。聚合物304中的该开口区域被称为聚合物开口。一旦限定了聚合物开口，将经由诸如金属电镀、金属喷涂等的标准方法来沉积UBM 305。该工艺形成了UBM 305，使得UBM 305的底部粘附于聚合物304、器件钝化层303在聚合物304和器件焊盘302之间的任何暴露的钝化部分、以及器件焊盘302本身。UBM 305的顶部是被限定用于焊料凸点放置和粘附的表面。
在该结构中以及在大多数下层焊料凸点结构中，器件焊盘302的直径小于UBM 305的直径，并且典型地具有0.43∶1的比值。这导致UBM 305在器件焊盘302之上的显著重叠。此外，聚合物304中开口的直径典型地小于UBM 305的直径，并且典型地具有0.32∶1的比值。
图5和图6是示出在形成焊料凸点之前的示例性现有技术再分布层(“RDL”)下层结构的截面图。图6a是示出在已经应用了焊料凸点507之后的示例性现有技术RDL下层结构的截面图。图7是图5和图6中所示的结构的俯视图。RDL轨迹(trace)505是使用该工业中已知的标准金属沉积方法形成的。RDL轨迹可以是单一的金属层或是堆叠的金属层(诸如钛/铝/钛或铜或铝或镍铜或铬/铜/铬等)。在RDL轨迹505的末端，该金属典型地被形成为圆形图案以变成连接焊盘(landing pad)505a。连接焊盘505a为随后的WLCSP或倒装芯片封装处理提供连接点。连接焊盘可以是单一的金属层或堆叠的金属层(诸如铝、铝/镍/铜、钛/铝/钛或铜或镍/金/铜等)。一旦已形成了轨迹505和连接焊盘505a，则光限定的聚合物2材料506被沉积在轨迹505和连接焊盘505a之上。然后开口被限定在聚合物2材料506中，其中开口位于连接焊盘505a的中央区域中并暴露连接焊盘505a的一部分。连接焊盘的中部之外的所有聚合物2材料506保持接触，覆盖轨迹505。聚合物2材料506的厚度典型地为20微米或更小。UBM 507被形成在聚合物2材料506之上并被形成在连接焊盘505a上，以建立UBM 507和连接焊盘505a之间的电连接。
典型地，连接焊盘505a的直径大于或等于UBM 507的直径。传统连接焊盘直径与UBM直径的比值是1∶1或更大。聚合物2开口直径与UBM直径的比值典型地是0.9∶1或更大。图6a示出了典型的RDL上焊料凸点。
半导体工业中的盛行趋势是转变到这样的处理技术，该处理技术采用了更小的部件大小，允许半导体器件展现更多的功能性。片上系统(“SoC”)器件是可能通过更小的部件大小制作的这类半导体器件的实例，并且通过图3和图4所示的结构示出。集合了更大功能性的更小的部件大小已经导致减小的输入-输出(“IO”)盘大小，如通过将图1和图2与图3和图4进行比较所示的。WLCSP应用中最终IO盘几何结构已变得显著小于所需的焊料凸点，从而在焊料凸点和最终的IO盘几何结构之间建立窄颈结构。该窄颈将不稳定性和不一致性引入到焊料凸点中，还提高了它们对温度周期变化和突然的机械震击冲击的敏感性。
发明内容
因此，期望能有一种改进的半导体封装，该封装在稳定性测试(诸如机械跌落测试、机械撞击或震动测试、机械剪切测试、温度周期变化、温度骤变测试或在测试半导体封装中使用的其他测试)中提供改善的机械和热-机械性能，尤其当刚性焊料组合物而非铅焊料组合物被用于焊料凸点时。本直接公开涉及一种焊料凸点互连结构，该结构基本上消除了由于相关技术的限制和缺点引起的一个或多个问题。
本发明的其他特征和优点将在以下的描述中给出，并且部分地将通过这些共开内容而变得显而易见，或通过实践本发明来获得。本发明的目的和其他优点将通过叙述的描述(包括本文所包含的任意权利要求和附图)中所具体指出的结构和实现和达到。
在一些实施例中，提供了一种再分布芯片规模封装，该封装具有衬底和最终的金属焊盘，该金属焊盘具有最终的金属焊盘大小。沉积在最终金属焊盘之上的器件钝化层具有钝化开口，其中，钝化层被局部移除以暴露下面的最终金属焊盘。沉积在钝化层之上的聚合物层具有聚合物开口，其中，聚合物层被局部移除以暴露下面的最终金属焊盘。导体层沉积在聚合物层之上，其中，导体层被图案化以提供轨迹和连接焊盘，连接焊盘具有连接焊盘长度。沉积在导体层之上的聚合物层具有聚合物层开口，其中，聚合物层被局部移除以包括下面的连接焊盘。沉积在聚合物层之上的凸点下金属层具有最终的凸点下金属大小和凸点下金属突出。聚合物开口直径与最终凸点下金属直径的比值范围从约0.35∶1到约0.85∶1。连接焊盘直径与最终凸点下金属直径的比值范围从约0.5∶1到约0.95∶1。在凸点下金属和其他区域具有近似圆形几何结构的实施例中，上述限定的长度对应于其直径。
在一些实施例中，提供了一种焊料IO上凸点芯片规模封装，该封装具有衬底和最终金属焊盘，最终金属焊盘具有最终金属焊盘大小。沉积在最终金属焊盘之上的器件钝化层具有钝化开口，其中，钝化层被局部移除以暴露下面的最终金属焊盘。沉积在钝化层之上的聚合物层具有聚合物开口，其中，聚合物层被局部移除以暴露下面的最终金属焊盘。沉积在聚合物层之上的凸点下金属层具有最终的凸点下金属大小。聚合物开口与最终的凸点下金属大小的比值范围从约0.35∶1到约0.85∶1。最终金属焊盘大小到最终凸点下金属大小的比值范围在约0.5∶1到约0.95∶1。钝化开口到最终凸点下金属大小的比值范围在约0.35∶1到约0.80∶1。在凸点下金属和其他区域具有近似圆形几何结构的实施例中，上述限定的长度对应于其直径。
应当理解的是，前述总体描述和以下详细描述两者都是示例性的和阐述性的，并且旨在提供对所披露的具有改进的热-机械强度和跌落测试性能的焊料凸点互连结构的进一步阐述。
附图说明
被包括以提供对所披露的具有改善的热机械强度和跌落试验性能的焊料凸点互连结构的进一步理解并且被结合于此并构成本说明书的一部分的附图，示出了示例性实施例，并连同说明书一起用于阐述所披露的具有改善的热机械强度和跌落试验性能的焊料凸点互连结构的至少一个实施例的原理。
在附图中：
图1示出了在形成焊料凸点之前器件焊盘上的现有技术IO上凸点结构。
图2示出了图1的IO上凸点结构的俯视图。
图2a示出了用于在器件焊盘上创建IO上凸点结构(包括创建焊料凸点)的典型现有技术处理。
图3示出了在形成焊料凸点之前器件焊盘上的可选现有技术的IO上凸点结构。
图4示出了图3的IO上凸点结构的俯视图。
图5是示例性现有技术再分布层结构的截面图。
图6是图5中所示的再分布层结构的一部分的详细视图。
图6a是示例性现有技术的RDL上凸点结构(包括焊料凸点)的截面图。
图7是图5中所示的再分布层结构的俯视图。
图8是根据一个实施例的示例性IO上凸点结构的截面图。
图9是图8中所示的示例性IO上凸点结构的俯视图。
图10是根据一个实施例的示例性再分布层结构的截面图。
图11是图10中所示的再分布层的一部分的详细视图。
图12是图10中所示的示例性再分布层结构的俯视图。
具体实施方式
以下描述和附图示出了特定实施例，这些实施例足以使本领域技术人员能够实现本文所描述的这些系统和方法。其他实施例可以结合结构上的、逻辑上的处理及其他变化，并且也旨于落在本公开的范围之内。实例仅代表可能的变化。
以下描述实现本系统和方法的各种实施例的元件。许多元件是可以利用已知结构来配置的。还应当理解到的是，本系统和方法的技术可以利用各种技术来实现。
具有改进的热机械强度和跌落试验性能的焊料凸点互连结构的特定实施例的公开内容将在下面呈现。半导体器件封装典型地被实现为芯片规模封装或晶片级封装，例如，被用于板上芯片装配应用，或被实现为用在倒装芯片封装应用中的标准的倒装芯片封装。这些实现方式的实例在以下专利中有所描述：美国专利第6,441,487号(Elenius等人在2002年8月27日发布，标题为Chip Scale PackageUsing Large Ductile Solder Balls)、美国专利第5,844,304号(Kata等人在1998年12月1日发布，标题为Process for ManufacturingSemiconductor Device and Semiconductor Wafer)、美国专利第5,547,740号(Higdon等人在1996年8月20日发布，标题为SolderableContacts for Flip Chip Intergrated Circuit Devices)、美国专利第6,251,501号(Higdon等人在2001年6月26日发布，标题为SurfaceMount Circuit Device and Solder Bumping Method Therefor)、以及PCT专利申请第PCT/U505/39008号(Vrtis等人在2005年10月28日发布，标题为Semiconductor Device Package with Bump Overlyinga Polymer Layer)，通过至少引证它们关于封装应用、结构、及加工方法的教导将它们结合于此。
所披露的互连结构的一个优点在于，其可以利用现有技术制造技术的优点来达到期望的热机械强度和跌落试验性能上的提高。披露了其中限定了UBM的直径、聚合物开口的直径、器件钝化开口的直径、以及器件焊盘的直径的最适宜的下层结构。尽管在本文中被描述为采用了圆形几何结构，但是在不背离本公开文件的范围或精神的情况下，可以针对UBM、聚合物开口、器件钝化开口、和/或器件焊盘而替换可选的几何结构。通过实例的方式(而不是限制的方式)，在一个实施例中，利用方形几何结构可以限定一个或多个结构。在这样的实施例中，结构的边长可以替换相应的直径。
图8和图9示出了采用本文所描述的比值的示例性IO上凸点结构。在图8和图9中，器件焊盘802的直径与UBM 805的直径的比值范围在0.5∶1到0.95∶1。聚合物804中的开口的直径与UBM805的直径的比值范围在0.35∶1到0.85∶1。器件钝化层803中的开口的直径与UBM 805的直径的比值范围在0.35∶1到0.80∶1。通过采用这些大小比值，直接的IO上凸点结构允许与热和机械应力相关联的力在IO上凸点结构上被分布得更加均匀，从而改善了该结构在不利状况下的整体性能，这在下面进一步描述。
图10、11和12示出了示例性RDL下层结构。在图10至12中，连接焊盘1005a的直径与UBM 1007的直径的比值范围在0.5∶1到0.95∶1。聚合物2层1006中的开口的直径与UBM 1007的直径的比值范围在0.35∶1到0.85∶1。通过采用这些大小比值，RDL下层结构允许与热和机械应用相关联的力在RDL下层结构上被分布得更加均匀，从而改善了该结构在不利状况下的整体性能，这在下面进一步描述。
电子工程设计发展联合协会(JEDEC)JESD22-B111标准提供了一种方法，该方法评估倒装芯片或WLCSP经受机械撞击(该机械撞击为如果半导体器件位于跌落的便携器件中时其将要经历的机械撞击)的能力。现有的WLCSP在100次跌落之前呈现失败。本文描述的本发明各实施例将WLCSP跌落测试性能提高了约超过200％，其中，它们现在能够经受100次或更多次的跌落。
尽管在本文中描述了部件几何结构的实现方式，但是新的凸点结构提供了提高的热机械稳定性并增强了整体结构吸收来自突然跌落的冲击的能力。通过实例的方式，相对于热机械稳定性，处于95％中的5％的失败率的温度循环测试(TCT)可以被改善多于100％(在一些情况下超过600个循环)。JEDEC跌落测试性能可以被改善多于100％。在利用IO上凸点实现的JESDA104B的TCT第二级测试中，该新的结构总地呈现了在超过600个循环后的一次失败。类似地，利用JESD22-B111标准的IO跌落测试的凸点在高达800次跌落后没有失败。再分布凸点结构已经经过了高达1000次循环的利用JESDA104B的TCT第二级测试结果，并且再分布的凸点结构已经经过了高达800次跌落的JESD22-B111标准跌落测试。
尽管以上描述了特定的示例性设备和方法，但是本领域技术人员将认识到在其他实现方式中上述步骤中的许多步骤可以重新安排和/或省略。特定实施例的前述描述披露了本公开文件的总体实质，在不背离总体构思的情况下其他人可以通过应用现有知识来容易地修改和/或调整它用于各种应用。例如，附加的聚合物层和再分布轨迹可以被用于在半导体晶片上形成多个金属层(例如，高达五个层)。因此，这些调整和修改落在所披露实施例的等价物的含义和范围之内。本文所采用的措辞和术语用于描述的目的而非构成限制。

Claims (18)

1.一种包含输入-输出(IO)上凸点结构的半导体封装，包括：
器件焊盘；
凸点下金属焊盘(UBM)；
聚合物；以及
钝化层，
其中，从所述器件焊盘的中央到所述器件焊盘的外边缘的最短距离与从所述UBM的中央到所述UBM的外边缘的最短距离的比值范围在0.5∶1到0.95∶1。
2.根据权利要求1所述的半导体封装，其中，从所述聚合物的中央到所述聚合物的外边缘的最短距离与从所述UBM的中央到所述UBM的外边缘的最短距离的比值范围在0.35∶1到0.85∶1。
3.根据权利要求1所述的半导体封装，其中，从所述钝化层的中央到所述钝化层的外边缘的最短距离与从所述UBM的中央到所述UBM的外边缘的最短距离的比值范围在0.35∶1到0.80∶1。
4.根据权利要求1所述的半导体封装，其中，从所述聚合物的中央到所述聚合物的外边缘的最短距离与从所述UBM的中央到所述UBM的外边缘的最短距离的比值范围在0.35∶1到0.85∶1；以及
其中，从所述钝化层的中央到所述钝化层的外边缘的最短距离与从所述UBM的中央到所述UBM的外边缘的最短距离的比值范围在0.35∶1到0.80∶1。
5.根据权利要求1所述的半导体封装，其中，与热应力和机械应力相关联的力在所述IO上凸点结构上被更加均匀地分布。
6.根据权利要求1所述的半导体封装，其中，所述器件焊盘、所述UBM、所述聚合物、及所述钝化层采用圆形几何结构。
7.根据权利要求1所述半导体封装，其中，所述器件焊盘、所述UBM、所述聚合物、及所述钝化层采用方形几何结构。
8.根据权利要求1所述的半导体封装，其中，所述聚合物是聚酰亚胺。
9.根据权利要求1所述的半导体封装，其中，所述聚合物是苯环丁烯(BCB)。
10.根据权利要求1所述的半导体封装，其中，所述聚合物是聚苯并恶唑。
11.一种包含再分布层(RDL)下层结构的半导体封装，包括：
连接焊盘；
凸点下金属焊盘(UBM)；以及
聚合物，
其中，从所述连接焊盘的中央到所述连接焊盘的外边缘的最短距离与从所述UBM的中央到所述UBM的外边缘的最短距离的比值范围在0.5∶1到0.95∶1。
12.根据权利要求11所述的半导体封装，其中，从所述聚合物的中央到所述聚合物的外边缘的最短距离与从所述UBM的中央到所述UBM的外边缘的最短距离的比值范围在0.35∶1到0.85∶1。
13.根据权利要求11所述半导体封装，其中，与热应力和机械应力相关联的力在所述RDL下层结构上被更加均匀地分布。
14.根据权利要求11所述的半导体封装，其中，所述连接焊盘、所述UBM、及所述聚合物采用圆形几何结构。
15.根据权利要求11所述的半导体封装，其中，所述连接焊盘、所述UBM、及所述聚合物采用方形几何结构。
16.根据权利要求11所述的半导体封装，其中，所述聚合物是聚酰亚胺。
17.根据权利要求11所述的半导体封装，其中，所述聚合物是苯环丁烯(BCB)。
18.根据权利要求11所述的半导体封装，其中，所述聚合物是聚苯并恶唑。
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