CN103199027B - 用于集成电路的ubm的形成 - Google Patents

用于集成电路的ubm的形成 Download PDF

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Publication number
CN103199027B
CN103199027B CN201210102112.9A CN201210102112A CN103199027B CN 103199027 B CN103199027 B CN 103199027B CN 201210102112 A CN201210102112 A CN 201210102112A CN 103199027 B CN103199027 B CN 103199027B
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layer
underbump metallization
polymeric layer
pad
passivation
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CN103199027A (zh
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吴逸文
林正怡
何明哲
刘重希
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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  • Engineering & Computer Science (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一种方法包括在金属焊盘上方形成聚合物层；在聚合物层中形成开口从而暴露出金属焊盘的一部分；以及形成凸块下金属化层(UBM)。该UBM包含延伸至开口内的电连接至金属焊盘的部分。本发明提供了用于集成电路的UBM的形成。

Description

用于集成电路的UBM的形成
技术领域
本发明涉及半导体制造，具体而言，涉及UBM器件的形成方法。
背景技术
在半导体晶圆的形成中，首先在半导体衬底的表面形成集成电路器件，诸如，晶体管。然后在集成电路器件上方形成互连结构。在半导体芯片的表面上形成互连件(诸如，金属凸块)，从而可以评估集成电路器件。
在典型的金属-凸块形成工艺中，首先采用溅射形成电连接至金属焊盘的凸块下金属化(UBM)层。该UBM层可以包括钛层、以及位于钛层上方的铜种子层。然后，例如通过电镀在UBM层上形成金属凸块。形成工艺包括形成用来覆盖UBM层的第一部分并且使UBM层的第二部分未被覆盖的掩模。在UBM层的第二部分上形成金属凸块。在形成金属凸块之后，去除掩模，并且通过湿法蚀刻去除UBM层的第一部分。
发明内容
一方面，本发明提供了一种方法，包括：在金属焊盘上方形成聚合物层；在所述聚合物层中形成开口从而暴露出所述金属焊盘的一部分；以及采用化学镀形成凸块下金属化层(UBM)，其中，所述UBM包括延伸至所述开口内的电连接至所述金属焊盘的部分，以及位于所述聚合物层的上方并且与所述聚合物层重叠的部分。
在所述的方法中，实施形成所述UBM的步骤直到所述UBM的厚度大于所述聚合物层的厚度。
在所述的方法中，在形成所述UBM的步骤之前，通过所述开口暴露出所述金属焊盘的边缘。
在所述的方法中，所述UBM还包括接触所述金属焊盘的所述边缘的第二部分。
在所述的方法中，形成所述UBM的步骤包括无电镀。
在所述的方法中，形成所述UBM的步骤包括浸镀。
在所述的方法中，所述金属焊盘是形成在钝化层上方的钝化后互连件(PPI)的一部分。
在所述的方法中，所述金属焊盘包括与第一钝化层齐平的第一部分、位于所述第一钝化层上方的第二部分，并且其中，所述金属焊盘的所述第二部分位于第二钝化层的一部分的下面，所述第二钝化层位于所述第一钝化层的上方。
另一方面，本发明还提供了一种方法，包括：形成第一钝化层；形成金属焊盘，其中，将所述金属焊盘的至少一部分设置在所述第一钝化层中；在所述金属焊盘上方形成聚合物层；在所述聚合物层中形成开口从而暴露出所述金属焊盘的一部分；以及在所述金属焊盘的暴露表面上形成凸块下金属化层(UBM)，其中，与所述开口对准的所述UBM的顶面高于所述聚合物层的顶面，并且其中，所述UBM的底面接触所述聚合物层的所述顶面。
所述的方法还包括：在所述第一钝化层的上方且在所述聚合物层的下方形成另一聚合物层；以及在所述另一聚合物层的上方形成钝化后互连件(PPI)，其中，所述PPI延伸到所述另一聚合物层中的开口内从而电连接至下面的焊盘，并且其中，所述金属焊盘是所述PPI的一部分。
在所述的方法中，所述金属焊盘包含边部，所述边部环绕所述金属焊盘的通过所述开口暴露出来的部分，并且其中，所述边部位于部分所述聚合物层的下方并且与部分所述聚合物层重叠。
在所述的方法中，在形成所述UBM的步骤之前，通过所述开口暴露出所述金属焊盘的边缘，并且其中，所述UBM包括：第一部分，所述第一部分位于所述聚合物层的一部分的上方并且与所述聚合物层的所述一部分重叠；以及第二部分，所述第二部分接触所述金属焊盘的所述边缘。
所述的方法还包括：在所述第一钝化层上方形成第二钝化层，其中，所述第二钝化层的一部分覆盖所述金属焊盘的边部。
在所述的方法中，与所述金属焊盘的通过所述开口暴露出来的所述部分重叠的所述UBM的一部分具有的顶面高于所述聚合物层的顶面。
在所述的方法中，在所述金属焊盘的暴露表面上形成UBM的步骤包括无电镀。
又一方面，本发明提供了一种器件，包括：第一钝化层；金属焊盘，至少一部分设置在所述第一钝化层中；聚合物层，位于所述金属焊盘的上方；开口，位于所述聚合层中，用于暴露出所述金属焊盘的一部分；以及凸块下金属化层(UBM)，延伸至所述开口内并且电连接至所述金属焊盘，其中，所述UBM的顶面包含第一部分和第二部分，其中，所述第一部分与部分所述金属焊盘重叠并且与所述聚合物层不重叠，以及所述第二部分与所述聚合物层的一部分重叠，并且其中，所述UBM的所述顶面的所述第一部分高于所述UBM的所述顶面的所述第二部分。
所述的器件还包括焊料区，所述焊料区位于所述UBM的上方并且与所述UBM接触。
在所述的器件中，所述UBM的所述顶面的所述第一部分基本上是平坦的，并且其中，所述UBM的所述顶面的所述第二部分不是平坦的，并且其中，所述顶面的所述第二部分的外部低于所述顶面的所述第二部分的内部。
在所述的器件中，所述UBM还包括接触所述金属焊盘的侧边并且设置在所述聚合物层的所述开口中的部分。
所述的器件还包括：焊球，所述焊球位于所述UBM的上方并且与所述UBM物理接触。
附图说明
为了更充分地理解实施例及其优点，现在将结合附图所进行的以下描述作为参考，其中：
图1至图11是根据各个实施例的制造凸块下金属化层(UBM)和连接件的中间阶段的剖视图和俯视图。
具体实施方式
在下面详细地论述了本发明实施例的制造和使用。然而，应当理解，实施例提供了许多可以在各种具体环境中实现的可应用的发明概念。所论述的具体实施例仅仅是说明性的，而不用于限制本发明的范围。
根据各个实施例提供了一种用于形成凸块下金属化层(UBM)和上覆的电连接件的方法。示出了根据实施例的制造UBM和电连接件的中间阶段。论述了实施例的变化。在所有各个视图和说明性实施例中，相似的参考标号用于表示相似的元件。
参考图1，提供了晶圆100，该晶圆100包括半导体衬底20。半导体衬底20可以是体硅衬底或者绝缘体上硅衬底，然而也可以使用包括III族、IV族、和V族元素的其他半导体材料。在半导体衬底20的表面形成集成电路器件，诸如晶体管(示意性地示出为21)。晶圆100还可以包括位于半导体衬底20上方的层间电介质(ILD)22、以及位于ILD22上方的金属层24。在介电层25中形成金属线26和通孔28。处于同一水平的金属线的组合在下文中被称为金属层。因此，通过通孔28使多个金属层24互连。在实施例中，介电层25由低-k介电材料形成。低-k介电材料的介电常数(k值)可以例如小于约3.0，或者小于约2.5。金属线26和通孔28可以由铜或者铜合金形成，然而它们也可以由其他金属形成。本领域技术人员将了解金属层的形成细节。
在金属层24上方形成金属焊盘30，并且可以将金属焊盘30电连接至金属线26和通孔28。金属焊盘30可以是铝焊盘或者铝-铜焊盘，因而其在下文中被可选地称为铝焊盘30，然而可以使用其他金属材料。在金属层24上方形成钝化层32。部分钝化层32可以覆盖铝焊盘30的边部。通过钝化层32中的开口暴露出铝焊盘30的一部分。钝化层32可以是单层或者复合层，并且可以由无孔材料形成。在实施例中，钝化层32是复合层，该复合层包含氧化硅层(未示出)、以及位于氧化硅层上方的氮化硅层(未示出)。钝化层32也可以由其他无孔介电材料(诸如未掺杂的硅酸盐玻璃(USG)、氮氧化硅等等)形成。
在钝化层32上方形成聚合物层36。聚合物层36可以包含聚合物，诸如环氧树脂、聚酰亚胺、苯并环丁烯(BCB)、聚苯并恶唑(PBO)等等。形成方法可以包括例如旋转涂布。使聚合物层36图案化以形成开口，通过该开口暴露出铝焊盘30。可以采用光刻技术来实施聚合物层36的图案化。可以以液体形式分配聚合物层36，然后使其固化。可选地，聚合物层36可以是层压在钝化层32上的层压膜。
形成通过聚合物层36中的开口电连接至铝焊盘30的钝化后互连件(PPI)38。因为在钝化层32形成之后形成PPI38，所以命名为PPI38。PPI38可以由纯铜、基本上纯的铜、或者铜合金形成。PPI38还可以包括含镍层。形成方法包括电镀、无电镀、溅射、化学汽相沉积方法等等。
图2示出了聚合物层42的形成和图案化。聚合物层42可以包含聚酰亚胺或者其他基于聚合物的材料(诸如PBO、BCB、环氧树脂等等)。在实施例中，聚合物层42通过旋转涂布形成，或者由层压膜形成，该层压膜层压在PPI38和聚合物层36上。在使聚合物层42图案化之后，通过开口44暴露出PPI38的一部分(其在下文中被称为PPI焊盘38A)。
参考图3A，实施了化学镀步骤以形成凸块下金属化层(UBM)46。UBM46可以具有单层结构或者包括由不同材料形成的多个子层的复合结构，并且可以包含选自基本上由镍层、钯层、金层及其组合组成的组的层。化学镀可以包括无电(E-less)镀、浸镀等等。在实施例中，UBM46由无电镀镍无电镀钯浸金(ENEPIG)形成，其包括镍层、位于镍层上的钯层、以及位于钯层上的金层。可以采用浸镀形成金层。在其他实施例中，UBM46可以由其他材料和其他方法(包括但不限于无电镀镍浸金(ENIG)、无电镀镍无电镀钯(ENEP)、直接浸金(DIG)等等)形成。
图3B示意性地示出了如图3A中的PPI38和UBM46的俯视图。PPI38包括PPI焊盘38A和连接至PPI焊盘38A的PPI线38B。UBM46的俯视尺寸(诸如，尺寸D1)大于聚合物层42中的开口44(也参考图2)的俯视尺寸(诸如，尺寸D2)。PPI焊盘38A的俯视尺寸(诸如，尺寸D3)可以等于、大于、或者小于UBM46的俯视尺寸D1。
返回参考图3A，UBM46的厚度T1大于聚合物层42的厚度T2。因为无电镀是各向同性的，所以当在开口44(图2)中时，UBM46的生长是基本上无水平生长的向上生长，直到UBM46的顶面与聚合物层42的顶面42A齐平。在该水平的上方，因为没有限制UBM46水平生长的聚合物层42，当向上延伸时，UBM46还横向生长，并且向上生长速率基本上接近于横向生长速率。结果是，生长的部分UBM46与部分聚合物层42重叠。该重叠部分具有宽度W1，该宽度W1可以例如是介于约0.5μm至约10μm之间。然而，应当了解，整个说明书中列举的尺寸仅仅是实例，并且可以变化为不同值。UBM46的顶面46A高于聚合物层42的顶面42A，其中顶面46A与顶面42A之间的高度差ΔT也可以是介于约0.6μm至约13μm之间。顶面46A包括与金属焊盘38A的通过聚合物层42暴露出来的部分重叠并且不与聚合物层42重叠的第一部分(内部)46A1，以及与聚合物层42重叠的第二部分(外部)46A2。第二部分46A2环绕第一部分46A1。顶面46A的第一部分46A1可以是基本上平坦的顶面，其不低于顶面46A的第二部分46A2，并且可以高于第二部分46A2。第二部分46A2可以是非平坦的表面。此外，可以将第二部分46A2分成内部和外部，内部比外部更接近于第一部分46A1。可以观察到，从内部到外部，高度逐渐降低。
参考图4，形成了连接件48。在实施例中，连接件48是焊球，其设置在UBM46上。然后可以对图4中示出的结构实施回流工艺，并且回流焊球48。在可选的实施例中，连接件48可以包含金属柱，其可以是铜柱。也可以在金属柱上形成另外的层(诸如，镍层、焊料盖顶(soldercap)、钯层等等)。
图5至图7示出了根据可选实施例的形成UBM和连接件的中间阶段的剖视图。除非另外说明，这些实施例中的元件的材料及形成方法与图1至图4中示出的实施例中通过相似的参考标号表示的相似元件基本上相同。因而可以从图1至图4中示出的实施例的论述中找到图5至图7中示出的实施例的形成细节。
这些实施例的初始步骤与图1中所示的基本上相同。接下来，如图5中所示，形成了聚合物层42并且使其图案化。得到的开口44具有的尺寸大于PPI焊盘38A的暴露部分(还请参考图6B)的尺寸。PPI焊盘38A的边缘38A1可以暴露于开口44。位于聚合物层42下面的层(诸如，聚合物层36)也可以具有通过开口44暴露出来的部分。
参考图6A，形成了UBM46，其中UBM46的材料可以选自如图1至图4中示出的实施例中的相同可用材料。此外，UBM46的形成方法可以选自如图1至图4中示出的实施例中的相同可用方法，并且可以包括无电镀。得到的UBM46的厚度T1大于聚合物层42的厚度T2。因此，UBM46的顶面46A具有高于聚合物层42的顶面42A的中心部分。此外，在开口44的一侧(图6A中的右侧)上，UBM46的一部分位于聚合物层42的上方并且与聚合物层42垂直重叠。在另一侧上，从PPI焊盘38A的边缘38A1开始水平地且垂直地形成了UBM46。UBM46也可以包含与聚合物层36的顶面36A物理接触的部分，该部分也与PPI38齐平。在该实施例中，因为UBM46可以从UBM电镀工艺开始时开始水平生长，所以可以增加UBM46的横向尺寸。
图6B示意性地示出了如图6A中的PPI38和UBM46的俯视图。PPI38包含PPI焊盘38A和连接至PPI焊盘38A的PPI线38B。PPI焊盘38A的暴露部分的俯视尺寸(诸如，尺寸D3)可以小于聚合物层42中的开口44(还参考图2)的俯视尺寸(诸如，尺寸D2)。图7示出了连接件48的形成，该连接件48可以填充开口44(图5和图6)的未被UBM46填充的剩余间隔。
图4和图7中所示出的结构可以用于形成晶圆级芯片尺寸封装件(WLCSP)。图8至图11示出了根据可选实施例的形成连接件和UBM的中间阶段的剖视图。这些实施例与图1至图7中示出的实施例相似，除了没有形成PPI，以及UBM46直接形成在金属焊盘上方。
参考图8，形成了金属焊盘30。金属焊盘可以是铝铜焊盘或者铜焊盘，然而可以使用其他导电材料。在形成金属焊盘30之前，可以在顶部金属52的上方形成钝化层54，该顶部金属可以位于顶部金属化层中，并且可以形成在低-k介电层51中。顶部金属52可以由铜或者铜合金形成，并且可以采用镶嵌工艺形成。在钝化层54中形成开口(被金属焊盘30占据)，接着形成金属焊盘30。在实施例中，金属焊盘30的边部可以位于部分钝化层54的上方并且与部分钝化层54重叠。钝化层54也被称为钝化-1。
接下来，如图9中所示，形成了钝化层56(可选地被称为钝化-2)和聚合物层42。钝化层54和钝化层56中的每一个可以由包括氧化硅层及位于氧化硅层上方的氮化硅层的复合层、USG层、氮氧化硅层等等形成。在聚合物层42中形成开口44，其中部分聚合物层42覆盖金属焊盘30的边部。
接下来，参考图10，形成了UBM46。UBM46的厚度T1大于聚合物层42的厚度T2。此外，UBM46横向地扩展到超过开口44的边缘，并且与部分聚合物层42重叠。类似地，也采用无电镀形成了UBM46。关于UBM46的材料、形成方法、以及相应尺寸可以参考图1至图4中示出的实施例，并且在此不作论述。在图11中，形成了连接件48，其可以是焊球或者另一类型的连接件。
在实施例中，通过采用无电镀形成UBM，简化了制造工艺，并且降低了制造成本。而且，使UBM46(图4、图7和图11)的厚度大于顶部聚合物层的厚度可以增加任何湿气到达PPI38或者金属焊盘30的行径(travelingpath)，该行径(如图4中的箭头60所示)包括UBM46和聚合物层42之间的界面。因此，实现了更好地防潮。
根据实施例，一种方法包括在金属焊盘上方形成聚合物层；在聚合物层中形成开口从而暴露出金属焊盘的一部分；以及采用无电镀形成UBM。该UBM包括延伸至开口内的电连接至金属焊盘的部分。
根据其他实施例，一种方法包括形成第一钝化层，以及形成金属焊盘，其中将金属焊盘的至少一部分设置在第一钝化层中。在金属焊盘上方形成聚合物层。在聚合物层中形成开口从而暴露出金属焊盘的一部分。采用化学镀在金属焊盘的暴露表面上形成UBM，直到UBM的顶面高于聚合物层的顶面。
根据又一些实施例，一种器件包括钝化层；至少一部分被设置在钝化层中的金属焊盘；位于金属焊盘上方的聚合物层；位于聚合物层中的开口；以及延伸至开口内并且电连接至金属焊盘的UBM。UBM的顶面包括第一部分和第二部分。第一部分与部分金属焊盘重叠并且与聚合物层不重叠。第二部分与部分聚合物层重叠。第一部分不低于第二部分。
尽管已经详细地描述了实施例及其优势，但应该理解，可以在不背离所附权利要求限定的实施例的精神和范围的情况下，在其中进行各种改变、替换和更改。而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员根据本发明将很容易理解，根据本发明可以利用现有的或今后开发的用于执行与本文所述相应实施例基本上相同的功能或者获得基本上相同的结果的工艺、机器、制造、材料组分、装置、方法或步骤。因此，所附权利要求预期在其范围内包括这样的工艺、机器、制造、材料组分、装置、方法或步骤。此外，每条权利要求构成单独的实施例，并且多个权利要求和实施例的组合在本发明的范围内。

Claims (14)

1.一种形成凸块下金属化层(UBM)的方法，包括：
在金属焊盘上方形成聚合物层，其中，所述金属焊盘是形成在钝化层上方的钝化后互连件(PPI)的一部分；
在所述聚合物层中形成开口从而暴露出所述金属焊盘的一部分，并且所述开口暴露出所述金属焊盘的一个侧边；以及
采用化学镀形成凸块下金属化层，其中，所述凸块下金属化层包括延伸至所述开口内的电连接至所述金属焊盘的部分，以及位于所述聚合物层的上方并且与所述聚合物层重叠的部分。
2.根据权利要求1所述的方法，其中，实施形成所述凸块下金属化层的步骤直到所述凸块下金属化层的厚度大于所述聚合物层的厚度。
3.根据权利要求1所述的方法，其中，所述凸块下金属化层还包括接触所述金属焊盘的所述侧边的部分。
4.根据权利要求1所述的方法，其中，形成所述凸块下金属化层的步骤包括无电镀。
5.根据权利要求1所述的方法，其中，形成所述凸块下金属化层的步骤包括浸镀。
6.一种形成凸块下金属化层(UBM)的方法，包括：
形成第一钝化层；
形成金属焊盘，其中，将所述金属焊盘的至少一部分设置在所述第一钝化层中；
在所述金属焊盘上方形成聚合物层；
在所述第一钝化层的上方且在所述聚合物层的下方形成另一聚合物层；
在所述另一聚合物层的上方形成钝化后互连件(PPI)，其中，所述钝化后互连件延伸到所述另一聚合物层中的开口内从而电连接至下面的金属焊盘，并且其中，所述钝化后互连件焊盘是所述钝化后互连件的一部分；
在所述聚合物层中形成开口从而暴露出所述钝化后互连件焊盘的一部分，并且所述开口暴露出所述钝化后互连件焊盘的一个侧边；以及
在所述钝化后互连件焊盘的暴露表面上形成凸块下金属化层，其中，与所述开口对准的所述凸块下金属化层的顶面高于所述聚合物层的顶面，并且其中，所述凸块下金属化层的底面接触所述聚合物层的所述顶面。
7.根据权利要求6所述的方法，其中，所述钝化后互连件焊盘包含边部，所述边部位于部分所述聚合物层的下方并且与部分所述聚合物层重叠。
8.根据权利要求6所述的方法，其中，所述凸块下金属化层包括：第一部分，所述第一部分位于所述聚合物层的一部分的上方并且与所述聚合物层的所述一部分重叠；以及第二部分，所述第二部分接触所述钝化后互连件焊盘的所述侧边。
9.根据权利要求6所述的方法，其中，与所述钝化后互连件焊盘的通过所述开口暴露出来的所述部分重叠的所述凸块下金属化层的一部分具有的顶面高于所述聚合物层的顶面。
10.根据权利要求6所述的方法，其中，在所述钝化后互连件焊盘的暴露表面上形成凸块下金属化层的步骤包括无电镀。
11.一种集成电路器件，包括：
第一钝化层；
金属焊盘，至少一部分设置在所述第一钝化层中；
聚合物层，位于所述金属焊盘的上方；
开口，位于所述聚合层中，用于暴露出所述金属焊盘的一部分；以及
凸块下金属化层(UBM)，延伸至所述开口内并且电连接至所述金属焊盘，其中，所述凸块下金属化层的顶面包含第一部分和第二部分，其中，所述第一部分与部分所述金属焊盘重叠并且与所述聚合物层不重叠，以及所述第二部分与所述聚合物层的一部分重叠，并且其中，所述凸块下金属化层的所述顶面的所述第一部分高于所述凸块下金属化层的所述顶面的所述第二部分，所述凸块下金属化层还包括接触所述金属焊盘的侧边并且设置在所述聚合物层的所述开口中的部分。
12.根据权利要求11所述的器件，还包括焊料区，所述焊料区位于所述凸块下金属化层的上方并且与所述凸块下金属化层接触。
13.根据权利要求11所述的器件，其中，所述凸块下金属化层的所述顶面的所述第一部分基本上是平坦的，并且其中，所述凸块下金属化层的所述顶面的所述第二部分不是平坦的，并且其中，所述顶面的所述第二部分的外部低于所述顶面的所述第二部分的内部。
14.根据权利要求11所述的器件，还包括：焊球，所述焊球位于所述凸块下金属化层的上方并且与所述凸块下金属化层物理接触。
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Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9978656B2 (en) * 2011-11-22 2018-05-22 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming fine-pitch copper bump structures
CN104485295A (zh) * 2014-12-16 2015-04-01 南通富士通微电子股份有限公司 晶圆级封装方法
US10340258B2 (en) * 2015-04-30 2019-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices
US9748212B2 (en) * 2015-04-30 2017-08-29 Taiwan Semiconductor Manufacturing Company, Ltd. Shadow pad for post-passivation interconnect structures
JP2017112225A (ja) * 2015-12-16 2017-06-22 シャープ株式会社 半導体装置
CN109920739A (zh) * 2016-08-19 2019-06-21 华为技术有限公司 一种半导体封装结构及其制造方法
US20180226372A1 (en) * 2017-02-08 2018-08-09 Nanya Technology Corporation Package structure and manufacturing method thereof
US10985124B2 (en) * 2018-04-23 2021-04-20 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
CN112310036A (zh) * 2020-11-03 2021-02-02 日月光半导体制造股份有限公司 半导体基板及其制造方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101636831A (zh) * 2007-04-23 2010-01-27 弗利普芯片国际有限公司 用于改善的机械和热机械性能的焊料凸点互连

Family Cites Families (7)

* Cited by examiner, † Cited by third party
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KR20020094472A (ko) 2001-06-12 2002-12-18 삼성전자 주식회사 반도체 패키지용 솔더 범프 형성방법
US7566650B2 (en) * 2005-09-23 2009-07-28 Stats Chippac Ltd. Integrated circuit solder bumping system
US20080136019A1 (en) * 2006-12-11 2008-06-12 Johnson Michael E Solder Bump/Under Bump Metallurgy Structure for High Temperature Applications
KR101406223B1 (ko) * 2007-10-25 2014-06-30 삼성전자주식회사 칩 온 칩 반도체 소자의 제조방법
TW200941601A (en) * 2008-03-19 2009-10-01 Chipmos Technologies Inc Conductive structure of a chip
US8736050B2 (en) 2009-09-03 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. Front side copper post joint structure for temporary bond in TSV application
KR101121827B1 (ko) 2010-04-13 2012-03-21 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101636831A (zh) * 2007-04-23 2010-01-27 弗利普芯片国际有限公司 用于改善的机械和热机械性能的焊料凸点互连

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