CN108630598A - 具有分层柱的半导体装置及其制造方法 - Google Patents

具有分层柱的半导体装置及其制造方法 Download PDF

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Publication number
CN108630598A
CN108630598A CN201810244200.XA CN201810244200A CN108630598A CN 108630598 A CN108630598 A CN 108630598A CN 201810244200 A CN201810244200 A CN 201810244200A CN 108630598 A CN108630598 A CN 108630598A
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China
Prior art keywords
layer
layering
hole
conductive
width
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CN201810244200.XA
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Inventor
罗纳·派翠克·休莫勒
麦克·G·凯利
可陆提斯·史温格
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Imark Technology Co
Amkor Technology Inc
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Imark Technology Co
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Publication of CN108630598A publication Critical patent/CN108630598A/zh
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Abstract

具有分层柱的半导体装置及其制造方法。本文揭示一种具有一个或多个分层柱的半导体装置及制造这种半导体装置的方法。所述半导体装置可包括重新分布层、半导体晶粒以及操作性地耦接所述半导体晶粒的底表面到所述重新分布层的多个互连结构。所述半导体装置可进一步包括在所述半导体晶粒的周围附近的一个或多个传导柱。所述一个或多个传导柱可被电性连接到所述重新分布层并且每个传导柱可包括多个堆叠的分层。

Description

具有分层柱的半导体装置及其制造方法
技术领域
本发明是关于具有传导柱的半导体装置及其制造方法。
背景技术
目前的半导体封装和用于形成半导体封装的方法是不足的，存在例如造成过多的成本、可靠度下降或是封装尺寸过大的问题。举例来说，现有的技术可形成铜柱，其藉由在光阻层中蚀刻出孔洞并且以铜填充所述孔洞而形成所述铜柱。这样的现有技术通常受限于大约2:1的高宽比(aspect ratio)(高度对宽度的比值)。限制这种现有技术获得更大高宽比的一个因素是，随着蚀刻孔洞的深度增加，用铜完全填充孔洞会变得越困难。
通过将现有和传统方法与参照附图在本公开内容的其余部分中所提出的本发明进行比较，对于本领域技术人员而言，现有和传统方法的其他限制和缺点将变得显而易见。
发明内容
本公开的各种态样提供一种用于制造半导体装置的方法及所产生的半导体装置。例如但不限于，本公开的各个态样针对包括分层柱的半导体装置和用于制造这种半导体装置的方法。
本发明的一态样是一种制造半导体装置的方法，所述方法包括：将半导体晶粒电性连接到插入物，所述半导体晶粒具有顶表面、底表面及将所述顶表面邻接到所述底表面的一个或多个侧表面；形成传导柱的第一分层，使得所述第一分层是在所述半导体晶粒的所述一个或多个侧表面的远处外围地设置并且所述第一分层被电性连接到所述插入物；以及形成所述传导柱的第二分层，使得所述第二分层是在所述传导柱的所述第一分层上并且电性连接到所述传导柱的所述第一分层。
所述方法进一步包括形成另一插入物于所述传导柱的所述第二分层上并且电性连接到所述传导柱的所述第二分层。
所述方法进一步包括电性附接另一半导体装置到所述另一插入物。
所述方法进一步包括形成传导互连结构于所述插入物上。
在所述方法中，将所述半导体晶粒电性连接到所述插入物包括附接所述半导体晶粒的微凸块到所述插入物的微衬垫。
所述方法进一步包括藉由底部填充材料将所述半导体晶粒的所述底表面与所述插入物之间的区域填充。
在所述方法中，形成所述第一分层包含：形成第一层于所述插入物上方；形成穿透所述第一层的第一孔洞以曝露所述插入物；以及藉由传导材料填充所述第一孔洞以形成电性连接至所述插入物的所述第一分层。
在所述方法中，形成所述第二分层包含：形成第二层于所述第一层和所述第一分层上方；形成穿透所述第二层并且在所述第一分层上方的第二孔洞以曝露所述第一分层；以及藉由传导材料填充所述第二孔洞以形成电性连接至所述第一分层的所述第二分层。
在所述方法中，形成所述第一孔洞包括形成具有第一宽度的所述第一孔洞；以及形成所述第二孔洞包括形成具有第二宽度的所述第二孔洞，所述第二宽度是小于所述第一宽度。
本发明的另一态样为一种制造半导体装置的方法，所述方法包括：电性连接半导体晶粒到一个或多个第一重新分布层，所述半导体晶粒具有顶表面、底表面及将所述顶表面邻接到所述底表面的一个或多个侧表面；形成传导柱的第一分层，使得所述第一分层是在所述半导体晶粒的所述一个或多个侧表面的远处外围地设置并且所述第一分层被电性连接到所述一个或多个第一重新分布层；以及形成所述传导柱的第二分层，使得所述第二分层是在所述传导柱的所述第一分层上并且电性连接到所述传导柱的所述第一分层。
所述方法进一步包括形成一个或多个第二重新分布层于所述半导体晶粒的所述顶表面上方并且电性连接到所述传导柱的所述第二分层。
所述方法进一步包括形成多个传导互连结构，所述多个传导互连结构被电性连接到所述一个或多个第一重新分布层。
在所述方法中，形成所述第一分层包括：形成第一层于所述一个或多个第一重新分布层上方；形成穿透所述第一层的第一孔洞以曝露所述一个或多个第一重新分布层；以及藉由传导材料填充所述第一孔洞以形成电性地连接到所述一个或多个第一重新分布层的所述第一分层。
在所述方法中，形成所述第二分层包括：形成第二层于所述第一层和所述第一分层上方；形成穿透所述第二层并且在所述第一分层上方的第二孔洞以曝露所述第一分层；以及藉由传导材料填充所述第二孔洞以形成电性连接到所述第一分层的所述第二分层。
在所述方法中，形成所述第一孔洞包括形成具有第一宽度的所述第一孔洞；以及形成所述第二孔洞包括形成具有第二宽度的所述第二孔洞，所述第二宽度是小于所述第一宽度。
一种半导体装置，其包括：一个或多个第一重新分布层；半导体晶粒，其包括顶表面、相对于所述顶表面的底表面以及邻接所述顶表面到所述底表面的一个或多个侧壁；多个互连结构，其操作性地耦接所述半导体晶粒的所述底表面到所述一个或多个第一重新分布层；以及一个或多个传导柱，其在所述半导体晶粒的周围附近并且电性连接到所述一个或多个第一重新分布层，每个传导柱包括多个堆叠的分层。
在所述半导体装置中，所述多个堆叠的分层包括：第一分层，其直接地连接到所述一个或多个第一重新分布层；以及第二分层，其直接地堆叠在所述第一分层上。
在所述半导体装置中，所述第一分层具有第一宽度并且所述第二分层具有第二宽度，所述第二宽度是小于所述第一宽度。
在所述半导体装置中，所述一个或多个传导柱中的每个柱具有高宽比，所述高宽比是大于或等于2。
所述半导体装置进一步包括一个或多个第二重新分布层，其于所述半导体晶粒的所述顶表面上方并且通过所述一个或多个传导柱而电性连接到所述一个或多个第一重新分布层。
附图说明
图1显示根据本揭示的各种态样的具有分层柱的第一半导体装置以及操作性地堆叠在所述第一半导体装置上的第二半导体装置的横截面示图。
图2显示根据本揭示的各种态样的图1的所述分层柱的立体图。
图3A至3M显示说明根据本揭示的各种态样的制造所述第一半导体装置以及附接所述第二半导体装置于其上的方法的横截面示图。
主要组件符号说明：
100 第一半导体装置
105 载体
110 第一半导体晶粒
111 顶表面
112 积体电路组件
113 底表面
115 侧表面/侧壁
116 凸块/传导凸块/附接结构/柱
117 焊料
118 底部填充
120 下插入物/第一插入物/插入物
122 微凸块衬垫/晶粒附接结构/衬垫
124 第一传导层/重新分布层
125 凸块下金属
127 第一介电层
127a 开口/孔
128 柱衬垫/凸块下金属/衬垫
129 第二介电层
129a 开口/孔
130 上插入物/第二插入物
132 第一介电层
132a 开口
134 衬垫/焊盘/传导层
136 上表面/第二介电层
136a 开口/孔
140 互连结构/传导互连结构
150 分层柱/柱
152 第一分层
153 第一光阻层
154 第二分层
155 第一孔洞
157 第二光阻层
159 第二孔洞
160 模制材料
200 第二半导体装置
210 第二半导体晶粒
212 积体电路组件
214 微凸块
220 插入物
240 互连结构/
具体实施方式
以下论述通过提供范例来呈现本发明的各种态样。此类范例是非限制性的，并且因此本揭示的各种态样的范围应不必受所提供的范例的任何特定特性所限制。在以下论述中，用语“举例来说”、“例如”和“范例性”是非限制性的且通常与“藉由范例而非限制”、“例如且不加限制”和类似者同义。
如本文中所使用的，“及/或”意指通过“及/或”接合的列表中的项目中的任何一或多者。作为范例，用语“x及/或y”意指三元素集合{(x),(y),(x,y)}中的任何元素。换句话说，用语“x及/或y”意指“x及y中的一或两者”。作为另一范例，用语“x、y及/或z”意指七元素集合{(x),(y),(z),(x,y),(x,z),(y,z),(x,y,z)}中的任何元素。换句话说，“x、y及/或z”意指“x、y和z中的一或多者”。
在此所用的辞汇只是为了描述特殊的范例，并且不意图限制本揭示。如在此所用，单数形式也意图包括复数形式，除非上下文明确另有所指。将进一步了解“包括”、“包含”、“含有”、“具有”、“拥有”、“有”和类似的词用于本说明书指定存在了所述的特色、事物、步骤、操作、元素及/或元件时，不排除存在或添加了一或多个其他的特色、事物、步骤、操作、元素、元件及/或其群组。
应当理解的是，虽然本文中可使用术语第一、第二等来描述各种部件，但是这些部件不应受这些术语所限制。这些术语仅用于将一个部件与另一部件区分开。因此，举例而言，在不脱离本揭示的教示的情况下，下面讨论的第一部件、第一组件或第一区段可被称为第二部件、第二组件或第二区段。类似地，诸如“上部”、“下部”、“侧边”和类似者的空间相关术语会在本文中使用，以利于描述所附图式中的一元件或特征与另一元件或特征的关系。然而应理解的是，部件可以不同的方式被定向，举例而言，在不脱离本揭示的教示的情况下，半导体装置被侧转，以使得半导体装置的“顶部”表面是水平面向，并且半导体装置的“侧边”表面是垂直面向。此外，范例性术语“在…上”可意味着“在…上”和“直接在…上(即，没有一个或多个中间层)”。
在附图中，为了清楚起见，各种尺寸(例如，层厚度、宽度…等等)可能被夸大。另外，在附图中，相同的附图标记可以在所讨论的各种范例中用来代表相同的元件。
现在将参考提供的各种范例说明来讨论以增强对本公开的各种态样的理解。应该理解的是，本公开的范围不受在此提供和讨论的范例的具体特征的限制。
图1中所示的是描绘第一半导体装置100以及第二半导体装置200的横截面示图。更具体地说，图1描绘所述第二半导体装置200堆叠在所述第一半导体装置100上。所述第一半导体装置100可包括第一半导体晶粒110、下或第一插入物120、上或第二插入物130、互连结构140以及分层柱150。所述第一半导体晶粒110可包含一个或多个积体电路组件112，其电性耦接到所述第一半导体晶粒110的一个或多个传导凸块116。再者，所述第一半导体晶粒110可具有顶表面111、平行于所述顶表面111的底表面113以及邻接所述顶表面111到所述底表面113的一个或多个侧表面或侧壁115。
所述下插入物120可包含一个或多个重新分布层124，其操作性地耦接所述第一半导体晶粒110的凸块116到所述一个或多个互连结构140。在此方式中，所述第一半导体晶粒110的所述积体电路组件112可通过所述下插入物120被操作性地耦接到一个或多个互连结构140。
所述上插入物130可被放置在半导体晶粒110的顶表面111上或上方使得所述半导体晶粒110被设置在所述下插入物120和所述上插入物130之间。所述上插入物130可通过在所述半导体晶粒110的侧壁115的一个或多个分层柱150的远处(beyond)外围地放置而被操作性地耦接到所述下插入物120。所述下插入物120的所述重新分布层124可进一步通过分层柱150而操作性地耦接所述上插入物130到所述一个或多个互连结构140。
所述上插入物130可进一步包含在所述上插入物130的上表面136上的一个或多个衬垫或焊盘134。此衬垫134可提供电连接以用于操作性地耦接额外电性组件，例如通过所述上插入物130和所述分层柱150将所述第二半导体装置200电连接到所述互连结构140。
如所示的，所述第二半导体装置200可包含第二半导体晶粒210、插入物220以及互连结构240。所述第二半导体晶粒210可包含一个或多个积体电路组件212，其通过所述第二半导体晶粒210的一个或多个微凸块214而被操作性地耦接到所述插入物220。所述插入物220可包含一个或多个重新分布层224，其被操作性地耦接所述微凸块214到所述一个或多个互连结构240。在此方式中，所述第二半导体晶粒210的积体电路组件212可通过插入物220而被操作性地耦接到所述一个或多个互连结构240。
再者，所述第二半导体装置200可被堆叠到所述第一半导体装置100上，使得所述一个或多个互连结构240被附加到在第一半导体装置100的上表面136上的所述一个或多个衬垫或焊盘134。在此方式中，第二半导体装置200的所述积体电路组件212可通过第一半导体装置100的所述上插入物130和所述分层柱150而被操作性地耦接到第一半导体装置100的互连结构140。
所述半导体晶粒110、210可包含任何各种形式的半导体晶粒，提供于此的是非限制性的范例。举例来说，所述半导体晶粒110、210可包含数位讯号处理器(DSP)、微控制器、微处理器、网路处理器、电源管理处理器、音频处理器、视频处理器、RF电路、无线基带晶片上系统(SoC)处理器、感测器、记忆体控制器、记忆体装置、特殊应用积体电路…等等。一个或多个被动电性组件也可以取代及/或额外被安装到所述半导体晶粒110、210。
如图1以及图2中的更细节所示，在一个实施例中的每个柱150包含两个分层152、154。然而，可设想在实施例中所述柱150包含更多分层(例如3个、4个…等等)。如所示的，每个柱150包含第一分层152和堆叠在所述第一分层152上的第二分层154。再者，所述第一分层152具有第一宽度W1，所述第一宽度W1大于所述第二分层154的第二宽度。所述第一分层152和所述第二分层154在宽度上的差异可在制造过程中提供较大的允许误差(tolerance)。
在一个实施例中，所述第一分层152是通过蚀刻或图案化第一光阻层而被形成以包含第一孔洞，并且接着藉由传导材料(例如Cu、Ni、Al、Au、Ag、Pd…等等)填充所述第一孔洞以形成所述柱150的第一分层152。特别是，所述第一孔洞可通过镀铜制程而被填充。在形成所述第一分层152之后，第二光阻层可被形成在所述第一光阻层和第一孔洞上方。所述第二光阻层可被蚀刻或图案化以形成第二孔洞于所述经填充的第一孔洞上方。所述第二孔洞可接着藉由传导材料(例如Cu、Ni、Al、Au、Ag、Pd…等等)所填充以形成所述柱150的第二分层154。特别是，可以使用以第一分层152作为基底的镀铜制程来填充第二孔洞。
在制造过程中，可能会有所述第二孔洞相对于所述第一孔洞之间位置的一些错位。将所述第一孔洞的宽度W1形成大于所述第二孔洞的宽度W2对于这样的错位可提供较大的允许误差。特别是，尽管所述第二分层154有一些错位，其依然可以完全地在所述第一分层152上。
当所述第一分层152被显示具有宽度W1，所述宽度W1是大于第二分层152的所述宽度W2，在某些实施例中，所述宽度也可以是相反的，也就是所述第一分层152具有小于第二分层152的宽度。在又另外的实施例中，所述第一分层152和第二分层154可被形成以具有相同的宽度。最后，图2描绘所述分层152、154是正圆柱体。在某些实施例中，所述分层152、154可被形成是正截头锥(frustum)，其中所述截头锥的底表面或顶表面是较大的。虽然以圆形横截面显示，所述分层152、154在某些实施例中可具有非圆形的横截面(例如长方形、正方形、椭圆形…等等)。再者，所述第一分层152可具有横截面(例如正方形)，其不同于所述第二分层154的横截面(例如圆形)。
参照图3A至3M，根据本揭示的各种态样图示出制造第一半导体装置100以及在其上堆叠第二半导体装置200的方法的横截面示图。如图3A中所示，载体105可提供平坦顶表面和平坦底表面。所述载体105可包含任何各种不同类型的载体材料。例如，所述载体105可包含半导体材料(例如硅、GaAs…等等)、玻璃材料、陶瓷材料、金属材料…等等。所述载体105也可以包含任何各种不同类型的组态。举例而言，所述载体105可以是块体的形式(例如晶圆形式、长方形面板形式…等等)。又例如，所述载体105可以是单一化形式(例如，从晶圆或面板所单一化、原本就以单一化所形成的…等等)。
如图3B中所示，多重重新分布层124可被建立在所述载体105上。举例而言，至少一层的凸块下金属(UBM)125可被直接地形成在所述载体105上。在一个范例性实施例中，所述凸块下金属125可由任何各种不同的材料所形成，而不由本发明所出现的材料所限制。举例来说，所述凸块下金属125可有由铬、镍、钯、金、银、前述材料的合金、前述材料的合成物、前述材料的等同物…等等中的至少一个所形成。举例而言，所述凸块下金属125可包含Ni和Au。举例而言，所述凸块下金属125也可以包含Cu、Ni和Au。所述凸块下金属125也可以利用任何各种制程而被形成，而不由本发明所出现的制程所限制。举例来说，所述凸块下金属125可利用无电电镀制程、电镀制程、溅镀制程…等等而被形成于所述载体105上。举例来说，所述凸块下金属125可避免或禁止在传导互连结构140和第一传导层124之间的界面处形成介金属化合物(intermetallic compound)，从而改善所述传导互连结构140的连结的可靠度。所述凸块下金属125可包含在所述载体105上的多层。举例来说，所述凸块下金属125可包含Ni的第一层以及Au的第二层。
所述凸块下金属125可接着被像是有机层(例如高分子聚合物，像是聚酰亚胺、苯环丁烯(Benzocyclobutene，BCB)、聚苯恶唑(Polybenzoxazole，PBO)、前述材料的等同物、前述材料的组合物…等等)的第一介电层127所覆盖，所述第一介电层127也可以被称为钝化层。举例来说，所述第一介电层127可被形成在所述凸块下金属125和所述载体105的所述顶表面上。可利用旋转涂布、喷洒涂布、浸沾式涂布、棒式涂布、前述涂布的等同方式、前述涂布的组合…等等中的一个或多个来形成所述第一介电层127，但是本发明的范围不局限于上述的涂布方式。例如，可通过层压干膜来形成所述第一介电层127。
举例来说，开口127a(或孔)可被形成在所述第一介电层127中，并且所述凸块下金属125的特定面积(例如，整个顶表面、所述顶表面的一部分、所述顶表面的中央区域...等等)可通过所述开口127a而被曝露。所述开口127a可以任何各种方式被形成(例如，机械及/或雷射烧蚀、化学蚀刻、光学微影…等等)。所述第一介电层127(或本文中所讨论的任何介电层)也可以最初就被形成具有开口127a，例如通过遮罩或是其他选择性介电层形成制程。
所述第一传导层或重新分布层124可被形成在所述凸块下金属125和所述第一介电层127上。举例来说，所述第一传导层124可被耦接到所述凸块下金属125。在范例性实施例中，种子层可被形成在所述凸块下金属125和所述第一介电层127上。本发明中所讨论的所述种子层及/或任何种子层可由任何各种材料所形成，包含但不限于钨、钛、前述材料的等同物、前述材料的组合、前述材料的合金…等等。所述种子层可利用任何各种制程而被形成。举例来说，可利用无电电镀制程、电解电镀制程、溅镀制程…等等中的一个或多个来形成所述种子层。举例来说，所述种子层可以由具有Cu靶的TiW所形成。又，本发明中所讨论的任何种子层可利用相同或相似的材料及/或制程所形成，或者是可利用个别不同的材料及/或制程所形成。此外，本文中所讨论的所述种子层及/或任何种子层可包含多层。例如，所述种子层可包含第一TiW层以及第二Cu层。
所述第一传导层124可接着被形成在所述种子层上。举例来说，所述第一传导层124及/或其形成可以与本文中所讨论的任何各种传导层及/或其形成共享任何或全部特性。举例来说，所述第一传导层124可以由铜、铝、金、银、钯、前述材料的等同物、前述材料的组合、前述材料合金、其他传导材料…等等所形成。
所述第一传导层124可使用任何各种制程所形成。举例来说，可利用无电电镀制程、电解电镀制程、溅镀制程…等等中的一个或多个来形成所述第一传导层124。所述第一传导层124的图案化或布线例如可利用任何各种制程来完成。举例来说，所述第一传导层124可使用光阻利用光学蚀刻制程…等等而被图案化或布线。举例来说，光阻可被旋转涂布(或是以其他方式施加，例如干膜…等等)于种子层上。所述光阻可接着例如被用来作为遮罩和照光制程。接着所述光阻的部分可被蚀刻掉，残留的光阻可在除渣制程(descumprocess)中被移除，并且干燥(例如，旋转冲洗干燥)可被执行以形成光阻模板。在形成所述第一传导层124之后，所述光阻模板可被剥除(例如，化学地剥除…等等)并且从所述第一传导层124而被曝露的所述种子层可被蚀刻。
所述第一传导层124及/或本文中所讨论的任何传导层也可被称作是重新分布层。又，本文中所讨论的任何传导层可利用相同或相似的材料及/或制程所形成，或者是可利用个别不同的材料及/或制程所形成。此外，所述第一传导层124及/或其形成可以与本文中所讨论的任何其他传导层及/或其形成共享任何或全部特性。
所述第一传导层124可接着被第二介电层129所覆盖。所述第二介电层129也可被称作是钝化层。所述第二介电层129可由任何各种材料所形成。举例来说，所述第二介电层129可由有机材料(例如高分子聚合物，像是聚酰亚胺、苯环丁烯(Benzocyclobutene，BCB)、聚苯恶唑(Polybenzoxazole，PBO)、前述材料的等同物、前述材料的组合物…等等)所形成。又举例来说，所述第二介电层129可由无机材料所形成。可利用任何各种制程来形成所述第二介电层129。举例来说，可利用旋转涂布、喷洒涂布、浸沾式涂布、棒式涂布、前述涂布的等同方式、前述涂布的组合…等等中的一个或多个来形成所述第二介电层129。所述第二介电层129及/或本文中所讨论的任何介电层也可被称作是钝化层。又，本文中所讨论的任何介电层可利用相同或相似的材料及/或制程所形成，或者是可利用个别不同的材料及/或制程所形成。此外，所述第二介电层129及/或其形成可以与本文中所讨论的其他介电层及/或其形成共享任何或全部特性。
具有或不具有种子层的所述第一传导层124和所述第二介电层129的形成可利用相同或相似的材料及/或制程或者是可利用个别不同的材料及/或制程被重复任何次数。图3B和图3C中所示的范例显示这些层的两个形成。因此，在所述图中用相似的标记来提供所述层(例如，重复所述第一传导层124和所述第二介电层129)。
开口或孔129a可被形成在所述第二介电层129中的特定面积处以曝露底下第一传导层124。所述开口129a可以任何各种方式被形成(例如，机械及/或雷射烧蚀、化学蚀刻、光学微影…等等)。所述第二介电层129(或本文中所讨论的任何介电层)也可以最初就被形成具有开口129a，例如通过遮罩或是其他选择性介电层形成制程。
此处为了讨论目的，所述重新分布层124和所述介电层127、129可被认为是插入物120的组件。再者，本文中所描述的所述凸块下金属125和所述衬垫122、128也可被认为是所述插入物120的组件。所述用语“插入物”在本文中被用来称作是一般重新分布结构(例如，介电和导体分层结构)，其被介置于其他结构之间。
再者，描绘于图3A至3M中的制造方法描述插入物120在所述载体105上的建构或组装。然而，在某些实施例中，所述插入物120可被实施作为层压基板(例如，通过第三方所提供的预制印刷电路板(PCB))或是不借助载体105而被制造。因此，所述制造方法的一些实施例可能缺少载体105或是可能从预制插入物120开始，而有效地消除图3A和3B中所显示的制程。
如图3C中所示，微凸块衬垫、其他衬垫、焊盘、附接结构或晶粒附接结构122可被形成，使得每个衬垫122被电性连接到底下重新分布层124。相似地，每个柱衬垫或凸块下金属128可被形成，使得所述衬垫128被电性连接到底下重新分布层124。所述底下重新分布层124可提供传导路径，所述传导路径电性耦接衬垫128和其柱150到个别的互连结构140或半导体晶粒110的附接结构116(见图1)。在范例性实施例中，每个微凸块衬垫122具有15μm到45μm之间的直径。再者，所述微凸块衬垫122被配置有50μm到150μm之间的线宽。所述柱衬垫128可被形成以具有一直径，所述直径是大于形成在所述柱衬垫128上的第一分层152的直径的10％。因此，在一个实施例中，每个柱衬垫128具有55μm到165μm之间的直径。再者，在范例性实施例中，种子层可被形成在所述底下重新分布层124的经曝露的部分上方。所述种子层及/或其形成可以与本文中所讨论的任何其他种子层(例如，微凸块种子层…等等)及/或其形成共享任何或全部特性。
每个衬垫122、128可包含任何各种材料而不局限于本文中所提供的范例中的材料。举例来说，每个衬垫122、128可包含铜、铝、金、银、钯、一般传导材料、传导材料、前述材料的等同物、前述材料的组合、前述材料合金、任何本文中所讨论的传导材料…等等。在范例性实施例中，每个衬垫122、128可包含Ni和Au。在另一范例性实施例中，每个衬垫122、128可包含Ni、Au和Cu。每个衬垫122、128可利用任何各种制程形成，而不局限于本文中所提供的范例中的制程。举例来说，可利用无电电镀制程、电解电镀制程、溅镀制程…等等中的一个或多个来形成每个衬垫122、128。
图3C中所显示的所述衬垫122、128延伸超出(或突出于)所述第一介电层111的顶表面，但是并不局限于本文所揭示的范围。举例来说，所述衬垫122、128可包含与最上方的介电层129的顶表面共平面的顶表面，或者是可包含在第一介电层111的所述顶表面下方的顶表面。虽然通常显示包含圆柱形状，但是所述衬垫122、128可包含任何各种几合组态(例如，正方形、矩形、椭圆形…等等)。
现在参照图3D，分层柱150的第一分层152可以沿着周边形成，以在柱150之间提供空间给随后安装的半导体晶粒110。所述第一分层152可被形成使得所述第一分层152中的每一个被电性连接到一个或多个底下衬垫128。
第一光阻层153可被形成于微凸块衬垫122和柱衬垫128上方。第一孔洞155可接着以任何各种方式(例如，机械及/或雷射烧蚀、化学蚀刻、光学微影…等等)穿透所述第一光阻层153而形成。每个第一孔洞155可被形成在个别的衬垫128上方，以曝露此衬垫128。所述第一孔洞155可接着藉由传导材料(例如，Cu、Ni、Al、Au、Ag、Pd…等等)填充以形成所述柱150的所述第一分层152。特别是，所述第一分层152可被形成为正圆柱体。如上文中所解释的，所述第一分层152在某些实施例中可具有非圆形的横截面。再者，在某些实施例中，所述第一分层152可被形成是正截头锥(frustum)，其中所述截头锥的底表面或顶表面是较大的。在某些实施例中，所述第一分层152可具有大于或等于1的高宽比。再者，所述第一分层152可具有基底直径或宽度W1在50μm到150μm之间以及高度H1在50μm到150μm之间。
现在参照图3E，分层柱150的第二分层154可被形成在第一分层152上。特别是，所述第二分层154可被形成，使得第二分层154中的每一个是通过个别第一分层152而电性连接到一个或多个底下重新分布层124。为此，第二光阻层157可被形成于所述第一光阻层153和第一分层152上方。第二孔洞159可接着以任何各种方式(例如，机械及/或雷射烧蚀、化学蚀刻、光学微影…等等)穿透所述第二光阻层157而形成。每个第二孔洞159可被形成在个别第一孔洞155和第一分层152上方，以曝露此第一分层152。所述第二孔洞159可接着被传导材料(例如，Cu、Ni、Al、Au、Ag、Pd…等等)所填充以形成所述柱150的第二分层154。特别是，所述第二分层154可被形成为正圆柱体。如上文中所解释的，所述第二分层154在某些实施例中可具有非圆形的横截面。再者，在某些实施例中，所述第二分层154可被形成是正截头锥(frustum)，其中所述截头锥的底表面或顶表面是较大的。
在某些实施例中，所述第二分层154可具有大于或等于1的高宽比。再者，所述第二分层154可具有基底直径或宽度W2是所述第一分层152的上直径或宽度的90％或小于所述第一分层152的上直径或宽度。这样较小的宽度W2可造成第二分层154被完全地由所述第一分层152所支撑，即使所述第一分层152和所述第二分层154之间存在有一些错位。再者，所述第二分层154可具有高度H2在50μm到150μm之间。
上述柱150的分层形成可有效地获得高宽比，所述高宽比是现有单一分层制程的高宽比的两倍。举例来说，如果现有制程可以形成具有高宽比为1的柱，而相似的制程可被用来形成柱150的每个分层152、154，从而有效地获得高宽比为2。在此方式中，比现有柱较高的柱150可被达到而不需要增加所述柱150的宽度及/或使用更昂贵的制程以确保所述较长的孔洞是被传导材料(例如，Cu、Ni、Al、Au、Ag、Pd…等等)完全地填充。
如图3F中所示，所述层153、157可被移除并且所述半导体晶粒110可被电性连接到衬垫122。举例来说，所述半导体晶粒110的每个传导凸块116(或其他传导附接结构)可经由焊料117而被电性连接到个别的衬垫122。所述半导体晶粒110的所述传导凸块116可以任何各种方式但不局限于本文所述的方式被附接到所述衬垫122。
举例来说，所述半导体晶粒110的所述传导凸块116(或其他传导附接结构，例如传导柱…等等)可经由焊料117而被电性连接到所述衬垫122。在某些实施例中，所述用语“凸块”可共同地代表传导凸块或柱116以及在所述柱116上的焊料117。所述半导体晶粒110的所述传导凸块116可以任何各种方式但不局限于本文所述的方式被附接到所述衬垫122。举例来说，所述传导凸块116可利用任何各种焊接制程(例如，块材回焊制程、热压缩制程、雷射焊接制程…等等)而被焊接到所述衬垫122。又举例来说，所述传导凸块116可利用传导黏着剂、膏…等等而被耦接到所述衬垫122。此外，举例来说，所述传导凸块116可利用直接金属对金属(例如，无焊料)接合而被耦接到所述衬垫122。在范例性的情况中，焊料膏可利用模板和刮刀被施加到所述衬垫122，所述半导体晶粒110的所述传导凸块116可被放置在所述焊料膏中或上(例如，利用取放制程)，并且所述焊料膏可接着被回焊。在所述半导体晶粒110的附接之后，所述组合件可被清洗(例如，利用热DI水…等等)、经历助焊剂清洁和烘烤制程、经历电将处理制程…等等。
如图3F中所近一步描绘的，所述第一分层152可具有高度H1，其高于衬垫122、焊料117和连接结构116的组合高度。因此，第一分层152的上表面可高于半导体晶粒110的下表面113。因此，所述第一分层152和所述第二分层154之间的接合处可落在半导体晶粒110的侧壁115的高度中。
现在参照图3G，底部填充118可被形成在所述半导体晶粒110和所述插入物120之间。所述底部填充118可围绕且囊封所述传导凸块116和衬垫122的部分，所述部份被曝露于底部填充118。所述底部填充118可包含任何各种底部填充材料。又，所述底部填充118可利用任何各种制程(例如毛细管底部填充制程、使用预先施加的底部填充材料…等等)而被形成。在所述半导体晶粒110和所述第一插入物120之间的所述底部填充118可避免或减少例如由所述半导体晶粒110和所述第一插入物120之间不同的热膨胀系数所造成的翘曲。
接着，如图3H中所示，所述半导体晶粒110及/或插入物120可由模制材料(moldmaterial)160所囊封。所述模制材料160可例如包含囊封剂、模制树脂或是其他非传导材料。再者，所述模制材料160可被固化以硬化所述模制材料160并且近一步保护所述经囊封的半导体晶粒110。在范例性实施例中，其显示所述模制材料160覆盖所述柱150和所述半导体晶粒100。
可用任何各种方式(例如，压缩模制、转移模制(transfer molding)、泛模制(flood molding)…等等)形成所述模制材料160。所述模制材料160可包含任何各种类型的模制材料。举例来说，所述模制材料160可包含树脂、环氧树脂、热固性环氧树脂模制化合物、室温固化型…等等。
当所述模制材料160的填充物(例如无机填充物或是其他颗粒成分)的尺寸是小于(或实质上小于)所述第一插入物120和所述半导体晶粒110之间的空间或间隙时，所述底部填充118可能不会被利用，并且所述模制材料160可以替代地填充所述第一插入物120和所述半导体晶粒110之间的空间或间隙。在这样的范例性情况中，所述底部填充制程和模制制程可被结合成为具有经模制的底部填充(molded underfill)的单一模制制程。
现在参照图3I，所述模制材料160、柱150以及半导体晶粒100可通过模制研磨制程(mold-grinding process)而被平坦化。特别是，化学/机械研磨制程可被用来移除过多的模制材料160。特别是，所述模制研磨制程可形成经平坦化的上表面，其中所述模制材料160的上表面、所述柱150的上表面以及所述半导体晶粒110的上表面是共平面。在另外的范例性实施例中，所述模制研磨制程可保留所述模制材料160于所述半导体晶粒110的所述上表面上方。特别是，所述模制研磨制程可形成平坦化的上表面，其中所述模制材料160的所述上表面和所述柱150的所述上表面是共平面。在这样的实施例中，所述柱150可具有较高的高度以确保延伸超过所述半导体晶粒110的上表面的上末端通过所述模制研磨制程而被曝露。
如图3J中所示，所述模制材料160的上表面、半导体晶粒110及/或所述传导柱150可被所述第二插入物130的第一介电层132所覆盖。又，开口132a可被形成在所述第一介电层132中以曝露分层柱150。在范例性实施例中，种子层(未显示)可被形成在所述开口132a的内侧，例如像是在形成于所述第一介电层132中的所述开口132a的侧壁上及/或通过所述开口132a所曝露的所述分层柱150上。此外，又或者是，所述种子层可被形成在所述开口132a的外侧，例如像是在所述第一介电层132的所述顶表面上。如本文中所讨论的，所述种子层可使用与用于形成其他种子层相同的材料及/或制程来形成，或者可以使用不同的个别材料及/或制程来形成。
接续所述范例性实施例，所述第二插入物130的传导层134被形成在所述种子层上。举例来说，所述传导层134可被形成以充满或至少部分覆盖在所述第一介电层132中的所述开口132a的侧表面。所述传导层134可使用与用于形成其他传导或重新分布层相同的材料及/或制程来形成，或者可以使用不同的个别材料及/或制程来形成。所述传导层134在本文中也可以被称作是重新分布层。
所述传导层134可接着被第二插入物130的第二介电层136所覆盖。所述第二介电层136及/或其形成可以与本文中所讨论的其他介电层及/或其形成共享任何或全部特性。开口或孔136a可被形成在所述第二介电层136中以通过所述开口136a来曝露所述传导层134的特定面积。所述开口136a可以任何各种方式被形成，例如像是机械及/或雷射烧蚀、化学蚀刻…等等。或者是，举例来说，所述第二介电层136可以最初就被形成于其中具有所述开口136a。种子层可被形成在所述开口136a的内侧及/或所述开口136a的外侧。所述种子层及/或其形成可以与本文中所讨论的任何其他种子层及/或其形成共享任何或全部特性。
如图3K中所示，所述载体105可从所述凸块下金属125和所述第一介电层127移除。举例来说，大部份或是所有的所述载体105可通过机械研磨制程而被移除。任何残留的载体105可通过化学蚀刻制程而被移除。所述载体105的移除例如可以与本文中所讨论的任何载体的移除共享任何或全部特性。在范例性实施例中，所述载体105的移除之后，所述凸块下金属125可通过在所述第一介电层127中的所述开口127a而被曝露。所述凸块下金属125的所述底表面可以与所述第一介电层127的所述底表面共平面。
在某些实施例中，所述载体105可使用暂时黏着剂而被附接到所述第一介电层127及/或附接到所述凸块下金属125，当所述暂时黏着剂曝露于热能、雷射或光能、化学药剂…等等时，所述暂时黏着剂丧失其黏性或是大部份的黏性。执行将所述载体105从所述第一介电层127及/或凸块下金属125的分离可通过将所述暂时黏着剂曝露于能量及/或化学物质，其导致所述黏着剂松开。
如图3L中所进一步显示的，所述传导互连结构140可被电性连接到所述经曝露的凸块下金属125。所述传导互连结构140可包含任何各种特性，其非限制的范例以呈现于本文中。举例来说，所述传导互连结构140可由共晶焊料(Sn37Pb)、高铅焊料(Sn95Pb)、无铅焊料(SnAg、SnAu、SnCu、SnZn、SnZnBi、SnAgCu及SnAgBi)、前述材料的组合、前述材料的等同物…等等中的一个所形成。所述传导互连结构140及/或本文中所讨论的任何传导互连结构可包含传导球(例如，焊料球、铜芯焊料球…等等)、传导凸块、传导柱或杆(例如，铜柱、焊料封端的铜柱、导线…等等)…等等。
所述传导互连结构140可利用任何各种回焊及/或电镀制程而被连接到所述凸块下金属125。举例来说，挥发性助焊剂可被沉积(例如，被点、被印刷…等等)到所述凸块下金属125上，所述传导互连结构140可被沉积(例如，滴落…等等)到所述挥发性助焊剂上，并且接着提供大约150℃到250℃的回焊温度。在此时，所述挥发性助焊剂可被挥发并且完全地被移除。
如上文中所述的传导互连结构140可被认为是传导凸块、传导球、传导柱、传导杆、传导线…等等，并且可例如被安装在刚性印刷电路板、可挠性印刷电路板、引线框架..等等上。举例来说，包含所述第一插入物120的所述第一半导体晶粒110可接着被电性连接(例如以覆晶形式或是与覆晶相似的形式…等等)到任何各种基板(例如，主机板基板、封装基板、引线框架基板…等等)。
最后，如图3M中所示，所述第二半导体装置200被操作性地耦接到所述第一半导体装置100。特别是，所述第二半导体装置200的传导互连结构240可通过在所述第一介电层132中的开口132a而被电性连接到所述第二插入物130的所述传导层134。
尽管已经参照某些态样和范例描述了前述内容，但是本领域技术人员应该理解，在不脱离本公开的范围的情况下可以进行各种改变并且可以替换等同物。另外，在不脱离本公开的范围的情况下，可以作出许多修改以使特定情况或材料适用本公开的教导。因此，所期望的是，本公开不限于所公开的特定范例，而是本公开包括落入所附申请专利范围的范围内的所有范例。

Claims (20)

1.一种制造半导体装置的方法，其特征在于，所述方法包括：
将半导体晶粒电性连接到插入物，所述半导体晶粒具有顶表面、底表面及将所述顶表面邻接到所述底表面的一个或多个侧表面；
形成传导柱的第一分层，使得所述第一分层是在所述半导体晶粒的所述一个或多个侧表面的远处外围地设置并且所述第一分层被电性连接到所述插入物；以及
形成所述传导柱的第二分层，使得所述第二分层是在所述传导柱的所述第一分层上并且电性连接到所述传导柱的所述第一分层。
2.根据权利要求1所述的方法，其特征在于，其进一步包括形成另一插入物于所述传导柱的所述第二分层上并且电性连接到所述传导柱的所述第二分层。
3.根据权利要求2所述的方法，其特征在于，其进一步包括电性附接另一半导体装置到所述另一插入物。
4.根据权利要求1所述的方法，其特征在于，其进一步包括形成传导互连结构于所述插入物上。
5.根据权利要求1所述的方法，其特征在于，其中将所述半导体晶粒电性连接到所述插入物包括附接所述半导体晶粒的微凸块到所述插入物的微衬垫。
6.根据权利要求5所述的方法，其特征在于，其进一步包括藉由底部填充材料将所述半导体晶粒的所述底表面与所述插入物之间的区域填充。
7.根据权利要求1所述的方法，其特征在于，其中形成所述第一分层包含：
形成第一层于所述插入物上方；
形成穿透所述第一层的第一孔洞以曝露所述插入物；以及
藉由传导材料填充所述第一孔洞以形成电性连接至所述插入物的所述第一分层。
8.根据权利要求7所述的方法，其特征在于，其中形成所述第二分层包含：
形成第二层于所述第一层和所述第一分层上方；
形成穿透所述第二层并且在所述第一分层上方的第二孔洞以曝露所述第一分层；以及
藉由传导材料填充所述第二孔洞以形成电性连接至所述第一分层的所述第二分层。
9.根据权利要求8所述的方法，其特征在于，其中：
形成所述第一孔洞包括形成具有第一宽度的所述第一孔洞；以及
形成所述第二孔洞包括形成具有第二宽度的所述第二孔洞，所述第二宽度是小于所述第一宽度。
10.一种制造半导体装置的方法，其特征在于，所述方法包括：
电性连接半导体晶粒到一个或多个第一重新分布层，所述半导体晶粒具有顶表面、底表面及将所述顶表面邻接到所述底表面的一个或多个侧表面；
形成传导柱的第一分层，使得所述第一分层是在所述半导体晶粒的所述一个或多个侧表面的远处外围地设置并且所述第一分层被电性连接到所述一个或多个第一重新分布层；以及
形成所述传导柱的第二分层，使得所述第二分层是在所述传导柱的所述第一分层上并且电性连接到所述传导柱的所述第一分层。
11.根据权利要求10所述的方法，其特征在于，其进一步包括形成一个或多个第二重新分布层于所述半导体晶粒的所述顶表面上方并且电性连接到所述传导柱的所述第二分层。
12.根据权利要求10所述的方法，其特征在于，其进一步包括形成多个传导互连结构，所述多个传导互连结构被电性连接到所述一个或多个第一重新分布层。
13.根据权利要求10所述的方法，其特征在于，其中形成所述第一分层包括：
形成第一层于所述一个或多个第一重新分布层上方；
形成穿透所述第一层的第一孔洞以曝露所述一个或多个第一重新分布层；以及
藉由传导材料填充所述第一孔洞以形成电性地连接到所述一个或多个第一重新分布层的所述第一分层。
14.根据权利要求13所述的方法，其特征在于，其中形成所述第二分层包括：
形成第二层于所述第一层和所述第一分层上方；
形成穿透所述第二层并且在所述第一分层上方的第二孔洞以曝露所述第一分层；以及
藉由传导材料填充所述第二孔洞以形成电性连接到所述第一分层的所述第二分层。
15.根据权利要求14所述的方法，其特征在于：
形成所述第一孔洞包括形成具有第一宽度的所述第一孔洞；以及
形成所述第二孔洞包括形成具有第二宽度的所述第二孔洞，所述第二宽度是小于所述第一宽度。
16.一种半导体装置，其特征在于，其包括：
一个或多个第一重新分布层；
半导体晶粒，其包括顶表面、相对于所述顶表面的底表面以及邻接所述顶表面到所述底表面的一个或多个侧壁；
多个互连结构，其操作性地耦接所述半导体晶粒的所述底表面到所述一个或多个第一重新分布层；以及
一个或多个传导柱，其在所述半导体晶粒的周围附近并且电性连接到所述一个或多个第一重新分布层，每个传导柱包括多个堆叠的分层。
17.根据权利要求16所述的半导体装置，其特征在于，所述多个堆叠的分层包括：
第一分层，其直接地连接到所述一个或多个第一重新分布层；以及
第二分层，其直接地堆叠在所述第一分层上。
18.根据权利要求17所述的半导体装置，其特征在于，所述第一分层具有第一宽度并且所述第二分层具有第二宽度，所述第二宽度是小于所述第一宽度。
19.根据权利要求18所述的半导体装置，其特征在于，所述一个或多个传导柱中的每个柱具有高宽比，所述高宽比是大于或等于2。
20.根据权利要求17所述的半导体装置，其特征在于，其进一步包括一个或多个第二重新分布层，其于所述半导体晶粒的所述顶表面上方并且通过所述一个或多个传导柱而电性连接到所述一个或多个第一重新分布层。
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Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10256114B2 (en) * 2017-03-23 2019-04-09 Amkor Technology, Inc. Semiconductor device with tiered pillar and manufacturing method thereof
US10304697B2 (en) * 2017-10-05 2019-05-28 Amkor Technology, Inc. Electronic device with top side pin array and manufacturing method thereof
US11289373B2 (en) * 2018-07-31 2022-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof
US10910336B2 (en) * 2019-01-29 2021-02-02 Shih-Chi Chen Chip package structure
US11094602B2 (en) * 2019-08-09 2021-08-17 Advanced Semiconductor Engineering, Inc. Semiconductor device package
KR20210087752A (ko) 2020-01-03 2021-07-13 삼성전자주식회사 반도체 패키지
KR20210087751A (ko) 2020-01-03 2021-07-13 삼성전자주식회사 반도체 패키지
US11094649B2 (en) * 2020-01-21 2021-08-17 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110115081A1 (en) * 2008-10-21 2011-05-19 Panasonic Corporation Multilayer semiconductor device and electronic equipment
US20130147041A1 (en) * 2011-12-08 2013-06-13 Unimicron Technology Corporation Stack package structure and fabrication method thereof
US20130161817A1 (en) * 2011-12-27 2013-06-27 Maxim Integrated Products, Inc. Techniques for wafer-level processing of qfn packages
US20130341786A1 (en) * 2012-06-25 2013-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Package on Package Devices and Methods of Packaging Semiconductor Dies
US20150221601A1 (en) * 2014-02-05 2015-08-06 Amkor Technology, Inc. Semiconductor device with redistribution layers formed utilizing dummy substrates
US20160118333A1 (en) * 2014-10-24 2016-04-28 Stats Chippac, Ltd. Semiconductor Device and Method of Fabricating 3D Package with Short Cycle Time and High Yield
US20160343655A1 (en) * 2015-05-22 2016-11-24 Imec Vzw Substrate structure with array of micrometer scale copper pillar based structures and method for manufacturing same
US20170053878A1 (en) * 2015-08-18 2017-02-23 Ibiden Co., Ltd. Printed wiring board and semiconductor package

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8133762B2 (en) * 2009-03-17 2012-03-13 Stats Chippac, Ltd. Semiconductor device and method of providing z-interconnect conductive pillars with inner polymer core
JP2008235401A (ja) * 2007-03-19 2008-10-02 Spansion Llc 半導体装置及びその製造方法
US8115293B2 (en) * 2009-12-08 2012-02-14 Stats Chippac Ltd. Integrated circuit packaging system with interconnect and method of manufacture thereof
US8138014B2 (en) * 2010-01-29 2012-03-20 Stats Chippac, Ltd. Method of forming thin profile WLCSP with vertical interconnect over package footprint
US9842798B2 (en) * 2012-03-23 2017-12-12 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a PoP device with embedded vertical interconnect units
US8922005B2 (en) * 2012-04-11 2014-12-30 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for package on package devices with reversed stud bump through via interconnections
US9425136B2 (en) 2012-04-17 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Conical-shaped or tier-shaped pillar connections
US8901726B2 (en) * 2012-12-07 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package structure and method of manufacturing the same
US8901748B2 (en) * 2013-03-14 2014-12-02 Intel Corporation Direct external interconnect for embedded interconnect bridge package
US11018099B2 (en) * 2014-11-26 2021-05-25 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure having a conductive bump with a plurality of bump segments
US9761534B2 (en) * 2015-09-21 2017-09-12 Mediatek Inc. Semiconductor package, semiconductor device using the same and manufacturing method thereof
US9449953B1 (en) * 2015-10-08 2016-09-20 Inotera Memories, Inc. Package-on-package assembly and method for manufacturing the same
US10483211B2 (en) * 2016-02-22 2019-11-19 Mediatek Inc. Fan-out package structure and method for forming the same
US9960328B2 (en) * 2016-09-06 2018-05-01 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
US9953931B1 (en) * 2016-10-25 2018-04-24 Advanced Semiconductor Engineering, Inc Semiconductor device package and a method of manufacturing the same
US10475770B2 (en) * 2017-02-28 2019-11-12 Amkor Technology, Inc. Semiconductor device having stacked dies and stacked pillars and method of manufacturing thereof
US10256114B2 (en) * 2017-03-23 2019-04-09 Amkor Technology, Inc. Semiconductor device with tiered pillar and manufacturing method thereof
US10546817B2 (en) * 2017-12-28 2020-01-28 Intel IP Corporation Face-up fan-out electronic package with passive components using a support

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110115081A1 (en) * 2008-10-21 2011-05-19 Panasonic Corporation Multilayer semiconductor device and electronic equipment
US20130147041A1 (en) * 2011-12-08 2013-06-13 Unimicron Technology Corporation Stack package structure and fabrication method thereof
US20130161817A1 (en) * 2011-12-27 2013-06-27 Maxim Integrated Products, Inc. Techniques for wafer-level processing of qfn packages
US20130341786A1 (en) * 2012-06-25 2013-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Package on Package Devices and Methods of Packaging Semiconductor Dies
US20150221601A1 (en) * 2014-02-05 2015-08-06 Amkor Technology, Inc. Semiconductor device with redistribution layers formed utilizing dummy substrates
US20160118333A1 (en) * 2014-10-24 2016-04-28 Stats Chippac, Ltd. Semiconductor Device and Method of Fabricating 3D Package with Short Cycle Time and High Yield
US20160343655A1 (en) * 2015-05-22 2016-11-24 Imec Vzw Substrate structure with array of micrometer scale copper pillar based structures and method for manufacturing same
US20170053878A1 (en) * 2015-08-18 2017-02-23 Ibiden Co., Ltd. Printed wiring board and semiconductor package

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US20200294815A1 (en) 2020-09-17
US10256114B2 (en) 2019-04-09
TW202230538A (zh) 2022-08-01
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US20180277394A1 (en) 2018-09-27
US10748786B2 (en) 2020-08-18

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