TW201903907A - 具分層柱的半導體裝置及其製造方法 - Google Patents

具分層柱的半導體裝置及其製造方法 Download PDF

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TW201903907A
TW201903907A TW107110079A TW107110079A TW201903907A TW 201903907 A TW201903907 A TW 201903907A TW 107110079 A TW107110079 A TW 107110079A TW 107110079 A TW107110079 A TW 107110079A TW 201903907 A TW201903907 A TW 201903907A
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layer
forming
conductive
semiconductor die
hole
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TW107110079A
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TWI763808B (zh
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羅納 派翠克 休莫勒
麥克Ｇ 凱利
可陸提斯 史溫格
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美商艾馬克科技公司
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Abstract

本文揭示一種具有一個或多個分層柱的半導體裝置及製造這種半導體裝置的方法。所述半導體裝置可包括重新分布層、半導體晶粒以及操作性地耦接所述半導體晶粒的底表面到所述重新分布層的多個互連結構。所述半導體裝置可進一步包括在所述半導體晶粒的周圍附近的一個或多個傳導柱。所述一個或多個傳導柱可被電性連接到所述重新分布層並且每個傳導柱可包括多個堆疊的分層。

Description

具分層柱的半導體裝置及其製造方法
本發明是關於具有傳導柱的半導體裝置及其製造方法。
目前的半導體封裝和用於形成半導體封裝的方法是不足的，例如造成過多的成本、可靠度下降或是封裝尺寸過大。舉例來說，習知的技術可形成銅柱，其藉由在光阻層中蝕刻出孔洞並且以銅填充所述孔洞而形成所述銅柱。這樣的習知技術通常受限於大約2：1的高寬比(aspect ratio)(高度對寬度的比值)。限制這種習知技術獲得更大高寬比的一個因素是，隨著蝕刻孔洞的深度增加，用銅完全填充孔洞會變得越困難。
通過將習知和傳統方法與參照附圖在本公開內容的其餘部分中所提出的本發明進行比較，對於本領域技術人員而言，習知和傳統方法的其他限制和缺點將變得顯而易見。
本公開的各種態樣提供一種用於製造半導體裝置的方法及所產生的半導體裝置。例如但不限於，本公開的各個態樣針對包括分層柱的半導體裝置和用於製造這種半導體裝置的方法。
100‧‧‧第一半導體裝置
105‧‧‧載體
110‧‧‧第一半導體晶粒
111‧‧‧頂表面
112‧‧‧積體電路組件
113‧‧‧底表面
115‧‧‧側表面/側壁
116‧‧‧凸塊/傳導凸塊/附接結構/柱
117‧‧‧焊料
118‧‧‧底部填充
120‧‧‧下插入物/第一插入物/插入物
122‧‧‧微凸塊襯墊/晶粒附接結構/襯墊
124‧‧‧第一傳導層/重新分布層
125‧‧‧凸塊下金屬
127‧‧‧第一介電層
127a‧‧‧開口/孔
128‧‧‧柱襯墊/凸塊下金屬/襯墊
129‧‧‧第二介電層
129a‧‧‧開口/孔
130‧‧‧上插入物/第二插入物
132‧‧‧第一介電層
132a‧‧‧開口
134‧‧‧襯墊/焊盤/傳導層
136‧‧‧上表面/第二介電層
136a‧‧‧開口/孔
140‧‧‧互連結構/傳導互連結構
150‧‧‧分層柱/柱
152‧‧‧第一分層
153‧‧‧第一光阻層
154‧‧‧第二分層
155‧‧‧第一孔洞
157‧‧‧第二光阻層
159‧‧‧第二孔洞
160‧‧‧模製材料
200‧‧‧第二半導體裝置
210‧‧‧第二半導體晶粒
212‧‧‧積體電路組件
214‧‧‧微凸塊
220‧‧‧插入物
240‧‧‧互連結構/
圖1顯示根據本揭示的各種態樣的具有分層柱的第一半導體裝置以及操作性地堆疊在所述第一半導體裝置上的第二半導體裝置的橫截面示圖。
圖2顯示根據本揭示的各種態樣的圖1的所述分層柱的立體圖。
圖3A至3M顯示說明根據本揭示的各種態樣的製造所述第一半導體裝置以及附接所述第二半導體裝置於其上的方法的橫截面示圖。
以下論述通過提供範例來呈現本發明的各種態樣。此類範例是非限制性的，並且因此本揭示的各種態樣的範圍應不必受所提供的範例的任何特定特性所限制。在以下論述中，用語“舉例來說”、“例如”和“範例性”是非限制性的且通常與“藉由範例而非限制”、“例如且不加限制”和類似者同義。
如本文中所使用的，“及/或”意指通過“及/或”接合的列表中的項目中的任何一或多者。作為範例，用語“x及/或y”意指三元素集合{(x),(y),(x,y)}中的任何元素。換句話說，用語“x及/或y”意指“x及y中的一或兩者”。作為另一範例，用語“x、y及/或z”意指七元素集合{(x),(y),(z),(x,y),(x,z),(y,z),(x,y,z)}中的任何元素。換句話說，“x、y及/或z”意指“x、y和z中的一或多者”。
在此所用的辭彙只是為了描述特殊的範例，並且不意圖限制本揭示。如在此所用，單數形式也意圖包括複數形式，除非上下文明確另有所指。將進一步了解「包括」、「包含」、「含有」、「具有」、「擁有」、「有」和類似的詞用於本說明書指定存在了所述的特色、事物、步驟、操作、 元素及/或元件時，不排除存在或添加了一或多個其他的特色、事物、步驟、操作、元素、元件及/或其群組。
將理解的是，雖然本文中可使用術語第一、第二等來描述各種部件，但是這些部件不應受這些術語所限制。這些術語僅用於將一個部件與另一部件區分開。因此，舉例而言，在不脫離本揭示的教示的情況下，下面討論的第一部件、第一組件或第一區段可被稱為第二部件、第二組件或第二區段。類似地，諸如“上部”、“下部”、“側邊”和類似者的空間相關術語會在本文中使用，以利於描述所附圖式中的一元件或特徵與另一元件或特徵的關係。然而應理解的是，部件可以不同的方式被定向，舉例而言，在不脫離本揭示的教示的情況下，半導體裝置被側轉，以使得半導體裝置的“頂部”表面是水平面向，並且半導體裝置的“側邊”表面是垂直面向。此外，範例性術語“在…上”可意味著“在…上”和“直接在…上(即，沒有一個或多個中間層)”。
在附圖中，為了清楚起見，各種尺寸(例如，層厚度、寬度...等等)可能被誇大。另外，在附圖中，相同的附圖標記可以在所討論的各種範例中用來代表相同的元件。
現在將參考提供的各種範例說明來討論以增強對本公開的各種態樣的理解。應該理解的是，本公開的範圍不受在此提供和討論的範例的具體特徵的限制。
圖1中所示的是描繪第一半導體裝置100以及第二半導體裝置200的橫截面示圖。更具體地說，圖1描繪所述第二半導體裝置200堆疊在所述第一半導體裝置100上。所述第一半導體裝置100可包括第一半導體晶粒110、下或第一插入物120、上或第二插入物130、互連結構140以及分層柱150。所述第一半導體晶粒110可包含一個或多個積體電路組件112，其電性耦接到所述第一半導體晶粒110的一個或多個傳導凸塊116。再者，所述第一半導體晶粒110可具有 頂表面111、平行於所述頂表面111的底表面113以及鄰接所述頂表面111到所述底表面113的一個或多個側表面或側壁115。
所述下插入物120可包含一個或多個重新分布層124，其操作性地耦接所述第一半導體晶粒110的凸塊116到所述一個或多個互連結構140。在此方式中，所述第一半導體晶粒110的所述積體電路組件112可透過所述下插入物120被操作性地耦接到一個或多個互連結構140。
所述上插入物130可被放置在半導體晶粒110的頂表面111上或上方使得所述半導體晶粒110被設置在所述下插入物120和所述上插入物130之間。所述上插入物130可透過在所述半導體晶粒110的側壁115的一個或多個分層柱150的遠處(beyond)外圍地放置而被操作性地耦接到所述下插入物120。所述下插入物120的所述重新分布層124可進一步透過分層柱150而操作性地耦接所述上插入物130到所述一個或多個互連結構140。
所述上插入物130可進一步包含在所述上插入物130的上表面136上的一個或多個襯墊或焊盤134。此襯墊134可提供電連接以用於操作性地耦接額外電性組件，例如透過所述上插入物130和所述分層柱150將所述第二半導體裝置200電連接到所述互連結構140。
如所示的，所述第二半導體裝置200可包含第二半導體晶粒210、插入物220以及互連結構240。所述第二半導體晶粒210可包含一個或多個積體電路組件212，其透過所述第二半導體晶粒210的一個或多個微凸塊214而被操作性地耦接到所述插入物220。所述插入物220可包含一個或多個重新分布層224，其被操作性地耦接所述微凸塊214到所述一個或多個互連結構240。在此方式中，所述第二半導體晶粒210的積體電路組件212可透過插入物220而被操作性地耦接到所述一個或多個互連結構240。
再者，所述第二半導體裝置200可被堆疊到所述第一半導體裝置 100上，使得所述一個或多個互連結構240被附加到在第一半導體裝置100的上表面136上的所述一個或多個襯墊或焊盤134。在此方式中，第二半導體裝置200的所述積體電路組件212可透過第一半導體裝置100的所述上插入物130和所述分層柱150而被操作性地耦接到第一半導體裝置100的互連結構140。
所述半導體晶粒110、210可包含任何各種形式的半導體晶粒，提供於此的是非限制性的範例。舉例來說，所述半導體晶粒110、210可包含數位訊號處理器(DSP)、微控制器、微處理器、網路處理器、電源管理處理器、音頻處理器、視頻處理器、RF電路、無線基帶晶片上系統(SoC)處理器、感測器、記憶體控制器、記憶體裝置、特殊應用積體電路...等等。一個或多個被動電性組件也可以取代及/或額外被安裝到所述半導體晶粒110、210。
如圖1以及圖2中的更細節所示，在一個實施例中的每個柱150包含兩個分層152、154。然而，可設想在實施例中所述柱150包含更多分層(例如3個、4個...等等)。如所示的，每個柱150包含第一分層152和堆疊在所述第一分層152上的第二分層154。再者，所述第一分層152具有第一寬度W1，所述第一寬度W1大於所述第二分層154的第二寬度。所述第一分層152和所述第二分層154在寬度上的差異可在製造過程中提供較大的允許誤差(tolerance)。
在一個實施例中，所述第一分層152是透過蝕刻或圖案化第一光阻層而被形成以包含第一孔洞，並且接著藉由傳導材料(例如Cu、Ni、Al、Au、Ag、Pd...等等)填充所述第一孔洞以形成所述柱150的第一分層152。特別是，所述第一孔洞可透過鍍銅製程而被填充。在形成所述第一分層152之後，第二光阻層可被形成在所述第一光阻層和第一孔洞上方。所述第二光阻層可被蝕刻或圖案化以形成第二孔洞於所述經填充的第一孔洞上方。所述第二孔洞可接著藉由傳導材料(例如Cu、Ni、Al、Au、Ag、Pd...等等)所填充以形成所述柱150的第二分層154。特別是，可以使用以第一分層152作為基底的鍍銅製程來 填充第二孔洞。
在製造過程中，可能會有所述第二孔洞相對於所述第一孔洞之間位置的一些錯位。將所述第一孔洞的寬度W1形成大於所述第二孔洞的寬度W2對於這樣的錯位可提供較大的允許誤差。特別是，儘管所述第二分層154有一些錯位，其依然可以完全地在所述第一分層152上。
當所述第一分層152被顯示具有寬度W1，所述寬度W1是大於第二分層152的所述寬度W2，在某些實施例中，所述寬度也可以是相反的，也就是所述第一分層152具有小於第二分層152的寬度。在又另外的實施例中，所述第一分層152和第二分層154可被形成以具有相同的寬度。最後，圖2描繪所述分層152、154是正圓柱體。在某些實施例中，所述分層152、154可被形成是正截頭錐(frustum)，其中所述截頭錐的底表面或頂表面是較大的。雖然以圓形橫截面顯示，所述分層152、154在某些實施例中可具有非圓形的橫截面(例如長方形、正方形、橢圓形...等等)。再者，所述第一分層152可具有橫截面(例如正方形)，其不同於所述第二分層154的橫截面(例如圓形)。
參照圖3A至3M，根據本揭示的各種態樣圖示出製造第一半導體裝置100以及在其上堆疊第二半導體裝置200的方法的橫截面示圖。如圖3A中所示，載體105可提供平坦頂表面和平坦底表面。所述載體105可包含任何各種不同類型的載體材料。例如，所述載體105可包含半導體材料(例如矽、GaAs...等等)、玻璃材料、陶瓷材料、金屬材料...等等。所述載體105也可以包含任何各種不同類型的組態。舉例而言，所述載體105可以是塊體的形式(例如晶圓形式、長方形面板形式...等等)。又例如，所述載體105可以是單一化形式(例如，從晶圓或面板所單一化、原本就以單一化所形成的...等等)。
如圖3B中所示，多重重新分布層124可被建立在所述載體105上。舉例而言，至少一層的凸塊下金屬(UBM)125可被直接地形成在所述載體 105上。在一個範例性實施例中，所述凸塊下金屬125可由任何各種不同的材料所形成，而不由本發明所出現的材料所限制。舉例來說，所述凸塊下金屬125可有由鉻、鎳、鈀、金、銀、前述材料的合金、前述材料的合成物、前述材料的等同物...等等中的至少一個所形成。舉例而言，所述凸塊下金屬125可包含Ni和Au。舉例而言，所述凸塊下金屬125也可以包含Cu、Ni和Au。所述凸塊下金屬125也可以利用任何各種製程而被形成，而不由本發明所出現的製程所限制。舉例來說，所述凸塊下金屬125可利用無電電鍍製程、電鍍製程、濺鍍製程...等等而被形成於所述載體105上。舉例來說，所述凸塊下金屬125可避免或禁止在傳導互連結構140和第一傳導層124之間的界面處形成介金屬化合物(intermetallic compound)，從而改善所述傳導互連結構140的連結的可靠度。所述凸塊下金屬125可包含在所述載體105上的多層。舉例來說，所述凸塊下金屬125可包含Ni的第一層以及Au的第二層。
所述凸塊下金屬125可接著被像是有機層(例如高分子聚合物，像是聚醯亞胺、苯環丁烯(Benzocyclobutene，BCB)、聚苯噁唑(Polybenzoxazole，PBO)、前述材料的等同物、前述材料的組合物...等等)的第一介電層127所覆蓋，所述第一介電層127也可以被稱為鈍化層。舉例來說，所述第一介電層127可被形成在所述凸塊下金屬125和所述載體105的所述頂表面上。可利用旋轉塗佈、噴灑塗佈、浸沾式塗佈、棒式塗佈、前述塗佈的等同方式、前述塗佈的組合...等等中的一個或多個來形成所述第一介電層127，但是本發明的範圍不侷限於上述的塗佈方式。例如，可透過層壓乾膜來形成所述第一介電層127。
舉例來說，開口127a(或孔)可被形成在所述第一介電層127中，並且所述凸塊下金屬125的特定面積(例如，整個頂表面、所述頂表面的一部分、所述頂表面的中央區域...等等)可透過所述開口127a而被曝露。所述開口 127a可以任何各種方式被形成(例如，機械及/或雷射燒蝕、化學蝕刻、光學微影...等等)。所述第一介電層127(或本文中所討論的任何介電層)也可以最初就被形成具有開口127a，例如透過遮罩或是其他選擇性介電層形成製程。
所述第一傳導層或重新分布層124可被形成在所述凸塊下金屬125和所述第一介電層127上。舉例來說，所述第一傳導層124可被耦接到所述凸塊下金屬125。在範例性實施例中，種子層可被形成在所述凸塊下金屬125和所述第一介電層127上。本發明中所討論的所述種子層及/或任何種子層可由任何各種材料所形成，包含但不限於鎢、鈦、前述材料的等同物、前述材料的組合、前述材料的合金...等等。所述種子層可利用任何各種製程而被形成。舉例來說，可利用無電電鍍製程、電解電鍍製程、濺鍍製程...等等中的一個或多個來形成所述種子層。舉例來說，所述種子層可以由具有Cu靶的TiW所形成。又，本發明中所討論的任何種子層可利用相同或相似的材料及/或製程所形成，或者是可利用個別不同的材料及/或製程所形成。此外，本文中所討論的所述種子層及/或任何種子層可包含多層。例如，所述種子層可包含第一TiW層以及第二Cu層。
所述第一傳導層124可接著被形成在所述種子層上。舉例來說，所述第一傳導層124及/或其形成可以與本文中所討論的任何各種傳導層及/或其形成共享任何或全部特性。舉例來說，所述第一傳導層124可以由銅、鋁、金、銀、鈀、前述材料的等同物、前述材料的組合、前述材料合金、其他傳導材料...等等所形成。
所述第一傳導層124可使用任何各種製程所形成。舉例來說，可利用無電電鍍製程、電解電鍍製程、濺鍍製程...等等中的一個或多個來形成所述第一傳導層124。所述第一傳導層124的圖案化或佈線例如可利用任何各種製程來完成。舉例來說，所述第一傳導層124可使用光阻利用光學蝕刻製程...等 等而被圖案化或佈線。舉例來說，光阻可被旋轉塗佈(或是以其他方式施加，例如乾膜...等等)於種子層上。所述光阻可接著例如被用來作為遮罩和照光製程。接著所述光阻的部分可被蝕刻掉，殘留的光阻可在除渣製程(descum process)中被移除，並且乾燥(例如，旋轉沖洗乾燥)可被執行以形成光阻模板。在形成所述第一傳導層124之後，所述光阻模板可被剝除(例如，化學地剝除...等等)並且從所述第一傳導層124而被曝露的所述種子層可被蝕刻。
所述第一傳導層124及/或本文中所討論的任何傳導層也可被稱作是重新分布層。又，本文中所討論的任何傳導層可利用相同或相似的材料及/或製程所形成，或者是可利用個別不同的材料及/或製程所形成。此外，所述第一傳導層124及/或其形成可以與本文中所討論的任何其他傳導層及/或其形成共享任何或全部特性。
所述第一傳導層124可接著被第二介電層129所覆蓋。所述第二介電層129也可被稱作是鈍化層。所述第二介電層129可由任何各種材料所形成。舉例來說，所述第二介電層129可由有機材料(例如高分子聚合物，像是聚醯亞胺、苯環丁烯(Benzocyclobutene，BCB)、聚苯噁唑(Polybenzoxazole，PBO)、前述材料的等同物、前述材料的組合物...等等)所形成。又舉例來說，所述第二介電層129可由無機材料所形成。可利用任何各種製程來形成所述第二介電層129。舉例來說，可利用旋轉塗佈、噴灑塗佈、浸沾式塗佈、棒式塗佈、前述塗佈的等同方式、前述塗佈的組合...等等中的一個或多個來形成所述第二介電層129。所述第二介電層129及/或本文中所討論的任何介電層也可被稱作是鈍化層。又，本文中所討論的任何介電層可利用相同或相似的材料及/或製程所形成，或者是可利用個別不同的材料及/或製程所形成。此外，所述第二介電層129及/或其形成可以與本文中所討論的其他介電層及/或其形成共享任何或全部特性。
具有或不具有種子層的所述第一傳導層124和所述第二介電層129的形成可利用相同或相似的材料及/或製程或者是可利用個別不同的材料及/或製程被重複任何次數。圖3B和圖3C中所示的範例顯示這些層的兩個形成。因此，在所述圖中用相似的標記來提供所述層(例如，重複所述第一傳導層124和所述第二介電層129)。
開口或孔129a可被形成在所述第二介電層129中的特定面積處以曝露底下第一傳導層124。所述開口129a可以任何各種方式被形成(例如，機械及/或雷射燒蝕、化學蝕刻、光學微影...等等)。所述第二介電層129(或本文中所討論的任何介電層)也可以最初就被形成具有開口129a，例如透過遮罩或是其他選擇性介電層形成製程。
此處為了討論目的，所述重新分布層124和所述介電層127、129可被認為是插入物120的組件。再者，本文中所描述的所述凸塊下金屬125和所述襯墊122、128也可被認為是所述插入物120的組件。所述用語‘插入物，’在本文中被用來稱作是一般重新分布結構(例如，介電和導體分層結構)，其被介置於其他結構之間。
再者，描繪於圖3A至3M中的製造方法描述插入物120在所述載體105上的建構或組裝。然而，在某些實施例中，所述插入物120可被實施作為層壓基板(例如，透過第三方所提供的預製印刷電路板(PCB))或是不借助載體105而被製造。因此，所述製造方法的一些實施例可能缺少載體105或是可能從預製插入物120開始，而有效地消除圖3A和3B中所顯示的製程。
如圖3C中所示，微凸塊襯墊、其他襯墊、焊盤、附接結構或晶粒附接結構122可被形成，使得每個襯墊122被電性連接到底下重新分布層124。相似地，每個柱襯墊或凸塊下金屬128可被形成，使得所述襯墊128被電性連接到底下重新分布層124。所述底下重新分布層124可提供傳導路徑，所述 傳導路徑電性耦接襯墊128和其柱150到個別的互連結構140或半導體晶粒110的附接結構116(見圖1)。在範例性實施例中，每個微凸塊襯墊122具有15μm到45μm之間的直徑。再者，所述微凸塊襯墊122被配置有50μm到150μm之間的線寬。所述柱襯墊128可被形成以具有一直徑，所述直徑是大於形成在所述柱襯墊128上的第一分層152的直徑的10%。因此，在一個實施例中，每個柱襯墊128具有55μm到165μm之間的直徑。再者，在範例性實施例中，種子層可被形成在所述底下重新分布層124的經曝露的部分上方。所述種子層及/或其形成可以與本文中所討論的任何其他種子層(例如，微凸塊種子層...等等)及/或其形成共享任何或全部特性。
每個襯墊122、128可包含任何各種材料而不侷限於本文中所提供的範例中的材料。舉例來說，每個襯墊122、128可包含銅、鋁、金、銀、鈀、一般傳導材料、傳導材料、前述材料的等同物、前述材料的組合、前述材料合金、任何本文中所討論的傳導材料...等等。在範例性實施例中，每個襯墊122、128可包含Ni和Au。在另一範例性實施例中，每個襯墊122、128可包含Ni、Au和Cu。每個襯墊122、128可利用任何各種製程形成，而不侷限於本文中所提供的範例中的製程。舉例來說，可利用無電電鍍製程、電解電鍍製程、濺鍍製程...等等中的一個或多個來形成每個襯墊122、128。
圖3C中所顯示的所述襯墊122、128延伸超出(或突出於)所述第一介電層111的頂表面，但是並不侷限於本文所揭示的範圍。舉例來說，所述襯墊122、128可包含與最上方的介電層129的頂表面共平面的頂表面，或者是可包含在第一介電層111的所述頂表面下方的頂表面。雖然通常顯示包含圓柱形狀，但是所述襯墊122、128可包含任何各種幾合組態(例如，正方形、矩形、橢圓形...等等)。
現在參照圖3D，分層柱150的第一分層152可以沿著周邊形成， 以在柱150之間提供空間給隨後安裝的半導體晶粒110。所述第一分層152可被形成使得所述第一分層152中的每一個被電性連接到一個或多個底下襯墊128。
第一光阻層153可被形成於微凸塊襯墊122和柱襯墊128上方。第一孔洞155可接著以任何各種方式(例如，機械及/或雷射燒蝕、化學蝕刻、光學微影...等等)穿透所述第一光阻層153而形成。每個第一孔洞155可被形成在個別的襯墊128上方，以曝露此襯墊128。所述第一孔洞155可接著藉由傳導材料(例如，Cu、Ni、Al、Au、Ag、Pd...等等)填充以形成所述柱150的所述第一分層152。特別是，所述第一分層152可被形成為正圓柱體。如上文中所解釋的，所述第一分層152在某些實施例中可具有非圓形的橫截面。再者，在某些實施例中，所述第一分層152可被形成是正截頭錐(frustum)，其中所述截頭錐的底表面或頂表面是較大的。在某些實施例中，所述第一分層152可具有大於或等於1的高寬比。再者，所述第一分層152可具有基底直徑或寬度W1在50μm到150μm之間以及高度H1在50μm到150μm之間。
現在參照圖3E，分層柱150的第二分層154可被形成在第一分層152上。特別是，所述第二分層154可被形成，使得第二分層154中的每一個是透過個別第一分層152而電性連接到一個或多個底下重新分布層124。為此，第二光阻層157可被形成於所述第一光阻層153和第一分層152上方。第二孔洞159可接著以任何各種方式(例如，機械及/或雷射燒蝕、化學蝕刻、光學微影...等等)穿透所述第二光阻層157而形成。每個第二孔洞159可被形成在個別第一孔洞155和第一分層152上方，以曝露此第一分層152。所述第二孔洞159可接著被傳導材料(例如，Cu、Ni、Al、Au、Ag、Pd...等等)所填充以形成所述柱150的第二分層154。特別是，所述第二分層154可被形成為正圓柱體。如上文中所解釋的，所述第二分層154在某些實施例中可具有非圓形的橫截面。再者，在某些實施例中，所述第二分層154可被形成是正截頭錐(fustum)，其中所述截頭錐的 底表面或頂表面是較大的。
在某些實施例中，所述第二分層154可具有大於或等於1的高寬比。再者，所述第二分層154可具有基底直徑或寬度W2是所述第一分層152的上直徑或寬度的90%或小於所述第一分層152的上直徑或寬度。這樣較小的寬度W2可造成第二分層154被完全地由所述第一分層152所支撐，即使所述第一分層152和所述第二分層154之間存在有一些錯位。再者，所述第二分層154可具有高度H2在50μm到150μm之間。
上述柱150的分層形成可有效地獲得高寬比，所述高寬比是習知單一分層製程的高寬比的兩倍。舉例來說，如果習知製程可以形成具有高寬比為1的柱，而相似的製程可被用來形成柱150的每個分層152、154，從而有效地獲得高寬比為2。在此方式中，比習知柱較高的柱150可被達到而不需要增加所述柱150的寬度及/或使用更昂貴的製程以確保所述較長的孔洞是被傳導材料(例如，Cu、Ni、Al、Au、Ag、Pd...等等)完全地填充。
如圖3F中所示，所述層153、157可被移除並且所述半導體晶粒110可被電性連接到襯墊122。舉例來說，所述半導體晶粒110的每個傳導凸塊116(或其他傳導附接結構)可經由焊料117而被電性連接到個別的襯墊122。所述半導體晶粒110的所述傳導凸塊116可以任何各種方式但不侷限於本文所述的方式被附接到所述襯墊122。
舉例來說，所述半導體晶粒110的所述傳導凸塊116(或其他傳導附接結構，例如傳導柱...等等)可經由焊料117而被電性連接到所述襯墊122。在某些實施例中，所述用語“凸塊”可共同地代表傳導凸塊或柱116以及在所述柱116上的焊料117。所述半導體晶粒110的所述傳導凸塊116可以任何各種方式但不侷限於本文所述的方式被附接到所述襯墊122。舉例來說，所述傳導凸塊116可利用任何各種焊接製程(例如，塊材回焊製程、熱壓縮製程、雷射焊接製程... 等等)而被焊接到所述襯墊122。又舉例來說，所述傳導凸塊116可利用傳導黏著劑、膏...等等而被耦接到所述襯墊122。此外，舉例來說，所述傳導凸塊116可利用直接金屬對金屬(例如，無焊料)接合而被耦接到所述襯墊122。在範例性的情況中，焊料膏可利用模板和刮刀被施加到所述襯墊122，所述半導體晶粒110的所述傳導凸塊116可被放置在所述焊料膏中或上(例如，利用取放製程)，並且所述焊料膏可接著被回焊。在所述半導體晶粒110的附接之後，所述組合件可被清洗(例如，利用熱DI水...等等)、經歷助焊劑清潔和烘烤製程、經歷電將處理製程...等等。
如圖3F中所近一步描繪的，所述第一分層152可具有高度H1，其高於襯墊122、焊料117和連接結構116的組合高度。因此，第一分層152的上表面可高於半導體晶粒110的下表面113。因此，所述第一分層152和所述第二分層154之間的接合處可落在半導體晶粒110的側壁115的高度中。
現在參照圖3G，底部填充118可被形成在所述半導體晶粒110和所述插入物120之間。所述底部填充118可圍繞且囊封所述傳導凸塊116和襯墊122的部分，所述部份被曝露於底部填充118。所述底部填充118可包含任何各種底部填充材料。又，所述底部填充118可利用任何各種製程(例如毛細管底部填充製程、使用預先施加的底部填充材料...等等)而被形成。在所述半導體晶粒110和所述第一插入物120之間的所述底部填充118可避免或減少例如由所述半導體晶粒110和所述第一插入物120之間不同的熱膨脹係數所造成的翹曲。
接著，如圖3H中所示，所述半導體晶粒110及/或插入物120可由模製材料(mold material)160所囊封。所述模製材料160可例如包含囊封劑、模製樹脂或是其他非傳導材料。再者，所述模製材料160可被固化以硬化所述模製材料160並且近一步保護所述經囊封的半導體晶粒110。在範例性實施例中，其顯示所述模製材料160覆蓋所述柱150和所述半導體晶粒100。
可用任何各種方式(例如，壓縮模製、轉移模製(transfer molding)、泛模製(flood molding)...等等)形成所述模製材料160。所述模製材料160可包含任何各種類型的模製材料。舉例來說，所述模製材料160可包含樹脂、環氧樹脂、熱固性環氧樹脂模製化合物、室溫固化型...等等。
當所述模製材料160的填充物(例如無機填充物或是其他顆粒成分)的尺寸是小於(或實質上小於)所述第一插入物120和所述半導體晶粒110之間的空間或間隙時，所述底部填充118可能不會被利用，並且所述模製材料160可以替代地填充所述第一插入物120和所述半導體晶粒110之間的空間或間隙。在這樣的範例性情況中，所述底部填充製程和模製製程可被結合成為具有經模製的底部填充(molded underfill)的單一模製製程。
現在參照圖3I，所述模製材料160、柱150以及半導體晶粒100可透過模製研磨製程(mold-grinding process)而被平坦化。特別是，化學/機械研磨製程可被用來移除過多的模製材料160。特別是，所述模製研磨製程可形成經平坦化的上表面，其中所述模製材料160的上表面、所述柱150的上表面以及所述半導體晶粒110的上表面是共平面。在另外的範例性實施例中，所述模製研磨製程可保留所述模製材料160於所述半導體晶粒110的所述上表面上方。特別是，所述模製研磨製程可形成平坦化的上表面，其中所述模製材料160的所述上表面和所述柱150的所述上表面是共平面。在這樣的實施例中，所述柱150可具有較高的高度以確保延伸超過所述半導體晶粒110的上表面的上末端透過所述模製研磨製程而被曝露。
如圖3J中所示，所述模製材料160的上表面、半導體晶粒110及/或所述傳導柱150可被所述第二插入物130的第一介電層132所覆蓋。又，開口132a可被形成在所述第一介電層132中以曝露分層柱150。在範例性實施例中，種子層(未顯示)可被形成在所述開口132a的內側，例如像是在形成於所述第一 介電層132中的所述開口132a的側壁上及/或透過所述開口132a所曝露的所述分層柱150上。此外，又或者是，所述種子層可被形成在所述開口132a的外側，例如像是在所述第一介電層132的所述頂表面上。如本文中所討論的，所述種子層可使用與用於形成其他種子層相同的材料及/或製程來形成，或者可以使用不同的個別材料及/或製程來形成。
接續所述範例性實施例，所述第二插入物130的傳導層134被形成在所述種子層上。舉例來說，所述傳導層134可被形成以充滿或至少部分覆蓋在所述第一介電層132中的所述開口132a的側表面。所述傳導層134可使用與用於形成其他傳導或重新分布層相同的材料及/或製程來形成，或者可以使用不同的個別材料及/或製程來形成。所述傳導層134在本文中也可以被稱作是重新分布層。
所述傳導層134可接著被第二插入物130的第二介電層136所覆蓋。所述第二介電層136及/或其形成可以與本文中所討論的其他介電層及/或其形成共享任何或全部特性。開口或孔136a可被形成在所述第二介電層136中以透過所述開口136a來曝露所述傳導層134的特定面積。所述開口136a可以任何各種方式被形成，例如像是機械及/或雷射燒蝕、化學蝕刻...等等。或者是，舉例來說，所述第二介電層136可以最初就被形成於其中具有所述開口136a。種子層可被形成在所述開口136a的內側及/或所述開口136a的外側。所述種子層及/或其形成可以與本文中所討論的任何其他種子層及/或其形成共享任何或全部特性。
如圖3K中所示，所述載體105可從所述凸塊下金屬125和所述第一介電層127移除。舉例來說，大部份或是所有的所述載體105可透過機械研磨製程而被移除。任何殘留的載體105可透過化學蝕刻製程而被移除。所述載體105的移除例如可以與本文中所討論的任何載體的移除共享任何或全部特性。 在範例性實施例中，所述載體105的移除之後，所述凸塊下金屬125可透過在所述第一介電層127中的所述開口127a而被曝露。所述凸塊下金屬125的所述底表面可以與所述第一介電層127的所述底表面共平面。
在某些實施例中，所述載體105可使用暫時黏著劑而被附接到所述第一介電層127及/或附接到所述凸塊下金屬125，當所述暫時黏著劑曝露於熱能、雷射或光能、化學藥劑...等等時，所述暫時黏著劑喪失其黏性或是大部份的黏性。執行將所述載體105從所述第一介電層127及/或凸塊下金屬125的分離可透過將所述暫時黏著劑曝露於能量及/或化學物質，其導致所述黏著劑鬆開。
如圖3L中所進一步顯示的，所述傳導互連結構140可被電性連接到所述經曝露的凸塊下金屬125。所述傳導互連結構140可包含任何各種特性，其非限制的範例以呈現於本文中。舉例來說，所述傳導互連結構140可由共晶焊料(Sn37Pb)、高鉛焊料(Sn95Pb)、無鉛焊料(SnAg、SnAu、SnCu、SnZn、SnZnBi、SnAgCu及SnAgBi)、前述材料的組合、前述材料的等同物...等等中的一個所形成。所述傳導互連結構140及/或本文中所討論的任何傳導互連結構可包含傳導球(例如，焊料球、銅芯焊料球...等等)、傳導凸塊、傳導柱或桿(例如，銅柱、焊料封端的銅柱、導線...等等)...等等。
所述傳導互連結構140可利用任何各種回焊及/或電鍍製程而被連接到所述凸塊下金屬125。舉例來說，揮發性助焊劑可被沉積(例如，被點、被印刷...等等)到所述凸塊下金屬125上，所述傳導互連結構140可被沉積(例如，滴落...等等)到所述揮發性助焊劑上，並且接著提供大約150℃到250℃的回焊溫度。在此時，所述揮發性助焊劑可被揮發並且完全地被移除。
如上文中所述的傳導互連結構140可被認為是傳導凸塊、傳導球、傳導柱、傳導桿、傳導線...等等，並且可例如被安裝在剛性印刷電路板、可撓性印刷電路板、引線框架..等等上。舉例來說，包含所述第一插入物120的 所述第一半導體晶粒110可接著被電性連接(例如以覆晶形式或是與覆晶相似的形式...等等)到任何各種基板(例如，主機板基板、封裝基板、引線框架基板...等等)。
最後，如圖3M中所示，所述第二半導體裝置200被操作性地耦接到所述第一半導體裝置100。特別是，所述第二半導體裝置200的傳導互連結構240可透過在所述第一介電層132中的開口132a而被電性連接到所述第二插入物130的所述傳導層134。
儘管已經參照某些態樣和範例描述了前述內容，但是本領域技術人員應該理解，在不脫離本公開的範圍的情況下可以進行各種改變並且可以替換等同物。另外，在不脫離本公開的範圍的情況下，可以作出許多修改以使特定情況或材料適用本公開的教導。因此，所期望的是，本公開不限於所公開的特定範例，而是本公開包括落入所附申請專利範圍的範圍內的所有範例。

Claims (20)

  1. 一種製造半導體裝置的方法，所述方法包括：將半導體晶粒電性連接到插入物，所述半導體晶粒具有頂表面、底表面及將所述頂表面鄰接到所述底表面的一個或多個側表面；形成傳導柱的第一分層，使得所述第一分層是在所述半導體晶粒的所述一個或多個側表面的遠處外圍地設置並且所述第一分層被電性連接到所述插入物；以及形成所述傳導柱的第二分層，使得所述第二分層是在所述傳導柱的所述第一分層上並且電性連接到所述傳導柱的所述第一分層。
  2. 如請求項1的方法，其進一步包括形成另一插入物於所述傳導柱的所述第二分層上並且電性連接到所述傳導柱的所述第二分層。
  3. 如請求項2的方法，其進一步包括電性附接另一半導體裝置到所述另一插入物。
  4. 如請求項1的方法，其進一步包括形成傳導互連結構於所述插入物上。
  5. 如請求項1的方法，其中將所述半導體晶粒電性連接到所述插入物包括附接所述半導體晶粒的微凸塊到所述插入物的微襯墊。
  6. 如請求項5的方法，其進一步包括藉由底部填充材料將所述半導體晶粒的所述底表面與所述插入物之間的區域填充。
  7. 如請求項1的方法，其中形成所述第一分層包含：形成第一層於所述插入物上方；形成穿透所述第一層的第一孔洞以曝露所述插入物；以及藉由傳導材料填充所述第一孔洞以形成電性連接至所述插入物的所述第一分層。
  8. 如請求項7的方法，其中形成所述第二分層包含：形成第二層於所述第一層和所述第一分層上方；形成穿透所述第二層並且在所述第一分層上方的第二孔洞以曝露所述第一分層；以及藉由傳導材料填充所述第二孔洞以形成電性連接至所述第一分層的所述第二分層。
  9. 如請求項8的方法，其中：形成所述第一孔洞包括形成具有第一寬度的所述第一孔洞；以及形成所述第二孔洞包括形成具有第二寬度的所述第二孔洞，所述第二寬度是小於所述第一寬度。
  10. 一種製造半導體裝置的方法，所述方法包括：電性連接半導體晶粒到一個或多個第一重新分布層，所述半導體晶粒具有頂表面、底表面及將所述頂表面鄰接到所述底表面的一個或多個側表面；形成傳導柱的第一分層，使得所述第一分層是在所述半導體晶粒的所述一個或多個側表面的遠處外圍地設置並且所述第一分層被電性連接到所述一個或多個第一重新分布層；以及形成所述傳導柱的第二分層，使得所述第二分層是在所述傳導柱的所述第一分層上並且電性連接到所述傳導柱的所述第一分層。
  11. 如請求項10的方法，其進一步包括形成一個或多個第二重新分布層於所述半導體晶粒的所述頂表面上方並且電性連接到所述傳導柱的所述第二分層。
  12. 如請求項10的方法，其進一步包括形成多個傳導互連結構，所述多個傳導互連結構被電性連接到所述一個或多個第一重新分布層。
  13. 如請求項10的方法，其中形成所述第一分層包括： 形成第一層於所述一個或多個第一重新分布層上方；形成穿透所述第一層的第一孔洞以曝露所述一個或多個第一重新分布層；以及藉由傳導材料填充所述第一孔洞以形成電性地連接到所述一個或多個第一重新分布層的所述第一分層。
  14. 如請求項13的方法，其中形成所述第二分層包括：形成第二層於所述第一層和所述第一分層上方；形成穿透所述第二層並且在所述第一分層上方的第二孔洞以曝露所述第一分層；以及藉由傳導材料填充所述第二孔洞以形成電性連接到所述第一分層的所述第二分層。
  15. 如請求項14的方法，其中：形成所述第一孔洞包括形成具有第一寬度的所述第一孔洞；以及形成所述第二孔洞包括形成具有第二寬度的所述第二孔洞，所述第二寬度是小於所述第一寬度。
  16. 一種半導體裝置，其包括：一個或多個第一重新分布層；半導體晶粒，其包括頂表面、相對於所述頂表面的底表面以及鄰接所述頂表面到所述底表面的一個或多個側壁；多個互連結構，其操作性地耦接所述半導體晶粒的所述底表面到所述一個或多個第一重新分布層；以及一個或多個傳導柱，其在所述半導體晶粒的周圍附近並且電性連接到所述一個或多個第一重新分布層，每個傳導柱包括多個堆疊的分層。
  17. 如請求項16的半導體裝置，其中所述多個堆疊的分層包括： 第一分層，其直接地連接到所述一個或多個第一重新分布層；以及第二分層，其直接地堆疊在所述第一分層上。
  18. 如請求項17的半導體裝置，其中所述第一分層具有第一寬度並且所述第二分層具有第二寬度，所述第二寬度是小於所述第一寬度。
  19. 如請求項18的半導體裝置，其中所述一個或多個傳導柱中的每個柱具有高寬比，所述高寬比是大於或等於2。
  20. 如請求項17的半導體裝置，其進一步包括一個或多個第二重新分布層，其於所述半導體晶粒的所述頂表面上方並且透過所述一個或多個傳導柱而電性連接到所述一個或多個第一重新分布層。
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