TW200427018A - Face-to-face flip chip package with a dummy chip - Google Patents

Abstract

A face-to-face flip chip package with a dummy chip comprises a substrate and a face-to-face flip-chip module. The face-to-face flip-chip module is flip-chip mounted on the substrate and comprises a dummy chip, a semiconductor chip, a plurality of bumps and a plurality of solder balls. The semiconductor chip is flip-chip mounted on a right surface of the dummy chip by the bumps. A redistribution layer is formed on the right surface of the dummy chip and includes a plurality of flip-chip pads and a plurality of ball pads. The flip-chip pads are fan-in arranged on the right surface of the dummy chip. The ball pads are fan-out arranged on the peripheral of the right surface of the dummy chip for bonding the solder ball with larger diameter for flip-chip mounting of the face-to-face flip-chip module.

Description

200427018

V. Description of the invention (1) [Technical field to which the invention belongs] In particular, the present invention relates to a flip-chip package and a face-to-face flip-chip package with a dummy chip. [Prior art] It is known that the flip-chip packaging structure is a packaging substrate. The wafer is a direct flip-chip material that contains glass fiber reinforced polyimide, so the thermal expansion of the substrate causes the existence of these bumps. No. 4 4 5 61 8 "indicator, in order to eliminate the defects that the bumps are subjected to uniform or shedding stress on the bumps by providing material between the substrate and the wafer, or underfill material. 3 Yes A wafer with bumps and a piece bonded to the substrate, the FR ~ 4, FR-5, or BT resin or the coefficient of the substrate is much larger than the uniform stress of the flip-chip bonding. In the "Flip-Chip Package Structure Manufacturing Method", the problem of thermal strain mismatch caused by the heat revealed, there is an underfilling, which covers the bumps, redistributes them, and eliminates the breakage of the bumps.

However, with the evolution of the semiconductor wafer process, semiconductor wafers are becoming smaller and denser. They are required to provide more high-density micro-pitch bumps on a smaller wafer. At present, the bump pitch of flip-chip wafers can be increased. Up to 150 microns' special design, the chip-to-chip bump pitch can reach 70-90 micron or less, and it is not easy to make micro-pitch flip-chips according to the printed circuit board manufacturing process [fine pi tch fl ip- chip pad], and under the influence of the difference in thermal expansion coefficient, all bumps on the wafer are difficult to accurately flip-chip bond 200427018

The main purpose of the present invention is to provide a face-on-chip flip chip package, and to provide a face-to-face chip with a virtual chip. The front side of the virtual chip includes a virtual redistributiQn laye /; a redistribution circuit. The layer [RDL] is combined, so that the contact of the wafer is a contact of a semiconductor wafer. The stress of the door achieves the fine-pitch and low-stress flip-chip bonding work. The purpose is to provide a face-to-face 1 with dummy wafers; a structure that utilizes the front-side redistribution of the circuit layers of the dummy wafers that cover the chipset. And bonding on the periphery of the front face of the virtual wafer. Ί = ball diameter ball to accommodate a flip-chip bonded semiconductor wafer in the central area of the ^ 7 to protect the wafer, so that the face-to-face wafer, In addition, the chip is directly bonded to a substrate, thereby replacing the conventional wire bonding and molding process. -A face-to-face flip-chip packaging structure with a virtual chip according to the present invention, comprising a substrate and a face-to-face flip-chip chipset, wherein the face-to-face flip-chip chipset is bonded to the substrate and the face-to-face flip-chip chipset The system includes a dummy chip, a semiconductor chip, a plurality of bumps, and a plurality of solder balls, wherein the semiconductor chip is flip-chip bonded and disposed on the front side of the dummy chip. The front side of the dummy chip forms a redistribution. Circuit layer (RDL, redistribution layer). The redistribution circuit layer includes a plurality of flip-chip pads, a plurality of ball-receiving pads, and a plurality of integrated circuits connecting the flip-chip pads and the ball-receiving pads. The flip-chip pads are fan-in [fan-in] arrayed on the front of the virtual chip, and the catch balls are fan-out

Page 7 200427018 V. Description of the invention (3) [fan-out] is arranged on the front periphery of the dummy wafer so that the bumps are bonded to the pads of the semiconductor wafer and the flip-chip pads of the dummy wafer 'Preferably' the exposed area of the catch pads is larger than the exposed area of the flip chip pads for larger ball diameter solder balls to be attached to the catch pads of the dummy wafer and for the face-to-face flip chip Chip-on-chip bonding of the chipset. [Embodiment] With reference to the drawings, the present invention will be described by the following embodiments. Please refer to FIG. 1. The face-to-face flip-chip package structure with a virtual chip of the present invention mainly includes a substrate 300 and a face-to-face flip-chip wafer group 100, wherein the face-to-face flip-chip wafer group 100 is a flip-chip Bonded to the upper surface 310 of the substrate f 300, and a plurality of solder balls 33 0 are formed on the lower surface 320 of the substrate 300. The face-to-face flip-chip wafer group 100 includes a dummy wafer 110 and at least one semiconductor wafer. 120. A plurality of bumps 130 and a plurality of solder balls 140 'The virtual chip 110 is a non-functional silicon substrate, which has a front surface 1U and a corresponding back surface 112' The front side ill of the virtual wafer 11 has at least one flip-chip bonding region 117 [see FIG. 2] and a redistribution circuit layer 113 [RDL, redistributi () n layer] formed by an integrated circuit process is formed. The distribution circuit layer 113 includes a plurality of flip-chip pads 114, a plurality of ball-connecting pads 115, and a plurality of integrated circuits 116 connecting the flip-chip pads 114 and the ball-connecting balls 115, each correspondingly Crystal pad n_4 The 5 series is electrically connected with a integrated circuit 116, where the frost m is fan-in arranged on the virtual chip 11Q = H, the cover is said to cover the crystal junction area 117 ', the ball pads 115 Department fanout [; ^ 11_〇 奴] arranged in 200427018

The periphery of the flip-chip bonding area 117 on the front side ill of the dummy wafer 110 is, therefore, the spacing between the pads 115 is greater than the spacing between the flip-chip pads 114. Preferably, the pads 11 5 The exposed area is larger than the exposed area of the flip-chip pad 11 4. The flip-chip 塾 11 4 is used for the a-to-a bonding of the semiconductor wafer 1 2 0. Since the redistribution circuit layer 113 can be fabricated using integrated circuits Technology, first sputtering a metal layer, and then applying photoresist to form the flip-chip pads using exposure, development, and etching methods, the ball-receivers 115, and the flip-chips 114 and the The connection lines 116 of the contact pads 115 may preferably be covered with a protection layer (passivation layer, not shown in the figure) on the front surface of the virtual chip 110, so as to reveal the exposed chip pads. 114 and the contact pads 115, therefore, the method of forming the flip-chip pads 114 is different from the conventional method of forming flip-chip pads on a printed circuit board, using the same integrated circuit process capability, in the virtual chip n. The distance between the flip chip pads 11 and 4 can perfectly match the semiconductor wafer. 2 The distance between the pads of 〇 is, for example, the distance between the flip-chip pads 11 and 14 is not more than 150 micrometers, or even 30 to 60 micrometers, for micro-pitch flip-chip bonding. At least one semiconductor wafer 120 is a flip-chip bonding region 117 bonded to the front surface 111 of the dummy wafer 110. Each semiconductor wafer 120 has an active surface 121 and a back surface. The active surface 121 of the semiconductor wafer 120 A plurality of solder pads 1 2 3 are formed. The size of the semiconductor wafer 1 20 is smaller than the size of the dummy wafer 110. The bumps i 30 are connected to the glow pads 123 of the semiconductor wafer 12 and The flip-chip pads 114 of the dummy wafer 110 form a chip set of a face-to-face flip-chip bonding type, so that the semiconductor wafer j 2 0 is electrically connected to the redistribution circuit layer of the dummy wafer 11 0. 3 In this embodiment,

Page 9 200427018 V. Description of the invention (5) These bumps 130 are tin bumps, preferably tin-lead bumps with higher flip-chip bonding temperature, such as high lead content tin-lead alloys [Lead 9 5 / tin 5].

The solder balls 1 40 are bonded to the dummy pads 11 5 ′ of the dummy chip 丨 丨 for the face-to-face flip-chip wafer group 100 to be bonded to the substrate 300. Preferably, the The solder ball 140 is a tin mismatch solder ball having a lower bonding temperature than the bumps, such as 6 3/3 7 tin boat alloy. The ball diameter of the solder balls is larger than the bumps. The ball diameter of the block 1 30 is such that the ball diameter of the fresh balls 14 0 is not less than the sum of the bump height of the bumps 1 3 0 and the thickness of the semiconductor wafer 1 2 0, so these The solder balls 丨 40 are arranged around the front face 111 of the virtual wafer 110 to accommodate the semiconductor wafer i 20, and the virtual wafer 110 and the large ball diameter solder balls 14 are used to reach the semiconductor. The wafer 120 is guaranteed, and because the dummy wafer and the semiconductor wafer have equal or similar thermal expansion coefficients, the bumps 130 between the dummy wafer u 0 and the semiconductor wafer 120 will not have residual stress. In order to achieve a better flip-chip bonding, 赖 赖 degree 'saves the conventional use' to disperse stress underfill materials if necessary (un derfilling material].

Therefore, in the above-mentioned face-to-face flip-chip wafer set 100, the semiconductor wafer 120 is carried and protected by the dummy wafer 110, and when the face-to-face flip-chip wafer set 100 is flip-chip bonded to a At the time of the substrate 300, the semiconductor wafer 120 with the main moving element is protected by the dummy wafer 110, the rod ball and the substrate 300, so it can replace and eliminate the conventional wire-bonding ] And moulding [molding] process, no longer need welding wire, molding compound [molding compound]. In a second specific embodiment of the present invention, please refer to FIG. 3 to disclose

200427018 V. Description of the invention (6) There is another face-to-face flip-chip wafer set 200. The face-to-face flip-chip wafer set 200 includes a dummy wafer 2 1 0, at least one semiconductor wafer 2 2 0, a plurality of bumps 230, and a plurality of Solder ball 240. The dummy chip 210 has a front surface 211, a back surface 212, and a redistribution circuit layer 213 formed on the front surface 211. The redistribution circuit layer 2 1 3 includes a plurality of fan-in arrays on the front surface. Chip pads 2 1 4 of 211, a plurality of fan-out pads 215 arranged around the front face 2 11 and a plurality of integrated circuits 21 6 connecting the chip pads 214 and the ball pads 215, and Each of the corresponding flip-chip pads 21 4 and the ball-receiving pads 2 1 5 are electrically connected by a integrated circuit 21 6. Preferably, the exposed areas of the ball-receiving pads 2 1 5 are larger than the flip-chip pads 214. The exposed area, and the ball diameter of the plurality of solder balls 2 40 bonded to the + pad 2 2 5 is larger than the ball diameter of the plurality of bumps 2 3 0 bonded to the flip chip pad 2 1 4, The bumps 2 3 0 are used as flip-chip bonding endpoints of the semiconductor wafer 2 2 0, which are bonded to the semiconductor wafer 2 2 0 actively. The bonding pads 223 of the surface 221 and the flip-chip pads 214 of the dummy chip 210, and the solder balls 240 are used as the flip-chip bonding end points of the face-to-face flip-chip chip set 200 for the face-to-face flip-chip chip set 200 to cover. It is bonded to a substrate or a printed circuit board (not shown in the figure). In this embodiment, the bumps 230 and the solder balls 2 4 0 are tin-lead alloys of the same material. In the semiconductor wafer 2 2 The back surface 222 of 0 is opened> A pad high-layer 224, such as BT resin or polyurethane, is formed. The pad high-layer 224 does not change with the flip-chip bonding temperature. Preferably, these 1 bumps 23 0 The sum of the ball diameter, the thickness of the semiconductor wafer 2 20 and the thickness of the upper layer 224 ^ of the pad is equivalent to two degrees of 'rich chip bonding' after the solder balls 240 are soldered to the substrate 3000. During the process from 200 to a substrate or printed circuit board, the solder balls 240 are re-soldered.

Page 11 200427018, description of the invention (7) The semiconductor wafer 220 is supported on a substrate to prevent the semiconductor wafer 220 from falling off due to the softening of the bumps 23, and further, it is formed on the back of the semiconductor wafer 220 The high layer 224 of the pad 222 can maintain the solder balls 240 to a certain height, to prevent the semiconductor wafer 220 from being damaged due to over-compression, and can support the semiconductor wafer 220 and the acne bump 230. The protection scope of the present invention shall be determined by the scope of the appended patent application. Any changes and modifications made by those skilled in the art without departing from the spirit and scope of the present invention shall fall within the protection scope of the present invention. .

Page 12 200427018 Brief Description of Drawings Figure 1 · A first embodiment of the present invention, a schematic cross-sectional view of a face-to-face flip-chip package structure with a virtual wafer. Fig. 2: A first embodiment of the present invention, a schematic front view of a virtual wafer having a face-to-face overlay structure of the virtual wafer. Fig. 3: A second specific embodiment of the present invention, a schematic cross-sectional view of a face-to-face flip-chip package structure with a dummy wafer. Simple explanation of component symbols • 100 face-to-face flip-chip chipset 110 virtual chip 111 113 redistribution circuit layer 114 116 integrated circuit 117 120 semiconductor wafer 121 123 pad 130 200 face-to-face flip-chip chipset 210 virtual chip 211 213 redistribution circuit layer 214 216 Integrated circuit 220 Semiconductor wafer 221 223 Solder pads 224 230 Bumps 240 300 Substrate 310 330 Solder ball front surface 112 Back surface wafer pad 115 Receiving pad flip chip bonding area active surface 122 Back bump 140 Front surface of the solder ball 212 Back surface wafer塾 215 Active surface of receiving pad 222 Upper surface of back pad High solder ball 320 Lower surface

Page 13

Claims (1)

200427018 6. Scope of patent application [Scope of patent application] 1. A face-to-face flip-chip package structure with a virtual chip, including: a substrate; and a face-to-face flip-chip wafer group, which is bonded to the substrate and the face-to-face flip-chip The chipset system includes: A dummy chip has a front surface and a back surface. The front surface of the dummy chip is formed with a redistribution layer [RDL, redistribution layer]. The redistribution line layer includes a plurality of flip chip and A plurality of ball-connecting pads corresponding to electrical connection, wherein the flip-chip pads are fan-in arranged on the front of the virtual chip, and the ball-connecting pads are fan-out arranged on the virtual At least one semiconductor wafer on the front surface of the wafer is a flip-chip bonding and is disposed on the front surface of the dummy wafer. The semiconductor wafer has an active surface and a back surface. The active surface of the semiconductor wafer is formed with a plurality of bonding pads. Blocks are bonded to the semiconductor wafer's pads and the dummy wafers; and a plurality of solder balls are bonded to the dummy wafer's pads for the face-to-face flip-chip chipset Its flip-chip bonding. That is, the face-to-face coverage with a virtual chip as described in item 1 of the patent application scope Γ = mounting σ structure, in which the exposed area of the contact pads is larger than the exposed area of the corresponding flip-chip pad. The face-to-face covering structure with virtual wafers described in item 1 of the patent scope of 2πΐ, wherein the solder balls have a solder ball diameter, which is not 200427018. 2. The sum of the ball diameter of the f bump and the thickness of the wafer. The face-to-face cover with a virtual wafer as described in item 3 of the patent scope of the patent application: where the back surface of the semiconductor wafer is formed with-padding ancient ja so that the ball diameter of the bumps, the semiconductor wafer The sum of the thickness and the thickness of the pad = stomach is equal to the height after the solder ball is soldered to the substrate. The face-to-face overlying $ sealed structure with virtual wafers, as described in item 丨 of the patent application scope, wherein these welds The flip-chip bonding temperature of the balls is lower than the flip-chip bonding temperature of the bumps of the semiconductor wafer. A face-to-face flip-chip chipset includes: a dummy chip having a front surface and a back surface; the front surface of the dummy chip is formed with a redistribution circuit layer [RDL, f edistributi on layer], and the weight The distribution circuit layer includes a plurality of flip-chip pads and a plurality of ball-connecting pads corresponding to electrical connections, wherein the flip-chip pads are fan-in [f an-i η] arranged on the front side of the virtual chip, and the contacts The ball pads are fan-out arranged on the front periphery of the virtual wafer; at least one semiconductor wafer is flip-chip bonded and disposed on the front side of the virtual wafer. The semiconductor wafer has an active surface and a back surface, and the semiconductor A plurality of bumps are formed on the active surface of the chip; a plurality of bumps are bonded to the pads of the semiconductor wafer and the flip-chip pads of the dummy wafer; and a plurality of solder balls are bonded to the pad. The ball pads of the dummy chip are used for chip-on-chip bonding of the face-to-face chip-on-chip chipset. Page 15 200427018 6. Scope of patent application 7. The face-to-face flip-chip chipset as described in item 6 of the scope of patent application, in which the exposed area of these ball-bearing pads is larger than the exposed area of the corresponding flip-chip pad. 8. The face-to-face flip-chip chipset as described in item 6 of the scope of patent application, wherein the solder balls have a ball diameter, which is not less than the sum of the height of the bumps and the thickness of the wafer . 9. The face-to-face flip-chip wafer set as described in item 8 of the scope of the patent application, wherein the back surface of the wafer is formed with a pad high layer, so that the height after the solder balls are soldered to a substrate is equal to the bumps of the bumps The sum of the ball diameter, the thickness of the wafer, and the thickness of the upper layer of the pad. 10. The face-to-face flip-chip wafer set according to item 6 of the scope of the patent application, wherein the flip-chip bonding temperature of the solder balls is lower than the flip-chip bonding temperature of the wafer. Page 16