CN104008981B - 形成凸块结构的方法 - Google Patents

形成凸块结构的方法 Download PDF

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Publication number
CN104008981B
CN104008981B CN201310199231.5A CN201310199231A CN104008981B CN 104008981 B CN104008981 B CN 104008981B CN 201310199231 A CN201310199231 A CN 201310199231A CN 104008981 B CN104008981 B CN 104008981B
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layer
metal layer
metal
passivation
exposure
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CN104008981A (zh
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于宗源
陈宪伟
陈英儒
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种形成凸块结构的方法，包括：通过化学镀工艺在顶部金属层上形成金属化层；在金属化层上方形成聚合物层；在聚合物层上形成开口以暴露金属化层；以及在暴露的金属化层上方形成焊料凸块，以与顶部金属层电接触。

Description

形成凸块结构的方法
技术领域
本发总的来说涉及集成电路，更具体地，涉及形成凸块结构的方法。
背景技术
现代集成电路由数百万诸如晶体管和电容器的有源器件组成。这些器件最初彼此隔离，但后来互连在一起以形成功能电路。典型的互连结构包括诸如金属线(配线)的横向互连件以及诸如通孔和接触件的垂直互连件。互连件越来越多地决定现代集成电路的性能和密度的限制。在互连结构的顶部上，在各个芯片的表面上形成并暴露焊盘。通过焊盘进行电连接以将芯片连接至封装衬底或另外的管芯。焊盘可用于配线接合或倒装芯片接合。倒装芯片封装利用凸块在芯片的输入/输出(I/O)焊盘与衬底或封装件的引线框架之间建立电接触。在结构上，凸块实际上包括凸块本身和位于凸块和I/O焊盘之间的“凸块下金属层”(UBM)。用于倒装芯片技术的另一结构是铜上直接凸块(DBOC)结构，其中UBM与顶部金属化层的铜金属直接接触。铝焊盘或内钝化层没有用于DBOC结构。在铝焊盘或内钝化层没有作为缓冲的情况下，DBOC结构通常具有较小的机械强度并遭受铜氧化的问题。
发明内容
根据本发明的一个方面，提供了一种形成凸块结构的方法，包括：通过化学镀工艺或浸镀工艺在半导体衬底的顶部金属层上形成第一金属化层；在第一金属化层上方形成钝化层；在钝化层中形成开口，以暴露第一金属化层，其中暴露的第一金属化层包括第一部分和第二部分；在钝化层和第一金属化层上形成保护层；在保护层中形成开口，以暴露第一金属化层的第一部分而覆盖第一金属化层的第二部分；以及在保护层上方形成电连接至第一金属化层的焊料凸块。
优选地，第一金属化层包括镍层、锡层、钛层、钯层和金层中的至少一个。
优选地，顶部金属层是包括铜的焊盘区域。
优选地，该方法进一步包括：在第一金属化层和焊料凸块之间形成第二金属化层。
优选地，第二金属化层包括钛层、铜层和镍层中的至少一个。
优选地，钝化层包括介电层，并且保护层包括聚合物层。
优选地，该方法进一步包括：在形成第一金属化层之前，对顶部金属层执行抛光工艺。
根据本发明的另一方面，提供了一种形成凸块结构的方法，包括：在半导体衬底的顶部金属层上形成钝化层；在钝化层中形成开口以暴露顶部金属层的一部分；通过化学镀工艺或浸镀工艺在顶部金属层的暴露部分上形成第一金属化层；在钝化层和第一金属化层上形成保护层；在保护层中形成开口，以暴露第一金属化层的第一部分而覆盖第一金属化层的第二部分；以及在保护层上方形成电连接至第一金属化层的焊料凸块。
优选地，第一金属化层包括延伸至钝化层的顶面的边缘部分。
优选地，保护层覆盖第一金属化层的边缘部分。
优选地，第一金属化层包括镍层、锡层、钛层、钯层和金层中的至少一个。
优选地，顶部金属层是包括铜的焊盘区域。
优选地，该方法进一步包括：在第一金属化层和焊料凸块之间形成第二金属化层。
优选地，第二金属化层包括钛层、铜层和镍层中的至少一个。
优选地，钝化层包括介电层，并且保护层包括聚合物层。
根据本发明的又一方面，提供了一种形成凸块结构的方法，包括：在半导体衬底的顶部金属层上形成钝化层；在钝化层中形成开口以暴露顶部金属层，暴露的顶部金属层包括第一部分和第二部分；在钝化层和暴露的顶部金属层上形成保护层；在保护层中形成开口以暴露顶部金属层的第一部分而覆盖暴露的顶部金属层的第二部分；通过化学镀工艺或浸镀工艺在顶部金属层的第一部分上形成第一金属化层；以及在保护层上方形成电连接至第一金属化层的焊料凸块。
优选地，第一金属化层包括镍层、锡层、钛层、钯层和金层中的至少一个。
优选地，顶部金属层是包括铜的焊盘区域。
优选地，该方法进一步包括：在第一金属化层和焊料凸块之间形成第二金属化层。
优选地，第二金属化层包括钛层、铜层和镍层中的至少一个。
附图说明
图1A至1E是根据一个实施例的形成凸块结构的方法的截面图；
图2A和2B是示出了根据又一个实施例的形成凸块结构的方法的截面图；
图3A至3B是示出了根据又一个实施例的形成凸块结构的方法的截面图；以及
图4A至4C是示出了根据又一个实施例的形成凸块结构的方法的截面图。
具体实施方式
可以理解，下面公开提供了很多不同的实施例或示例，用于实现各种实施例的不同的特性。下面描述了部件和配置的具体实例以简化本公开。然而，本公开可能以不同的形式体现，并且不应该被解释为限于本文所描述的实施例；提供这些实施例是为了使说明书详尽并完整，并且将使本领域技术人员完全明白本发明。然而，显而易见的是，在没有这些具体细节的情况下也可以实施一个或多个实施例。
在附图中，为了清楚而放大层和区域的厚度和宽度。图中相似的参考数字表示相似的元件。图中示出的元件和区域实际上是示意性的，因此图中所示的相对尺寸或间隔不用于限制本公开的范围。
图1A至图1E是示出根据一个实施例的形成凸块结构的各个中间阶段的截面图。
参照图1A，根据一个实施例示出了其上形成有电路12的衬底10的一部分。例如，衬底10可以包括体硅、掺杂或非掺杂、或者绝缘体上半导体(SOI)衬底的有源层。通常，SOI衬底包括形成在绝缘层上的诸如硅的半导体材料层。例如，绝缘体层可以是隐埋氧化物(BOX)层或氧化硅层。在衬底(通常为硅衬底或玻璃衬底)上提供绝缘层。还可以使用诸如多层或梯度衬底的其他衬底。形成在衬底10上的电路12可以是适合于具体应用的任何类型的电路。在实施例中，电路12包括形成在衬底10上的电器件，其中一个或多个介电层覆盖电器件。金属层可形成在介电层之间，以在电器件之间传输电信号。电器件也可以形成在一个或多个介电层中。例如，电路12可以包括各种N型金属氧化物半导体(NMOS)和/或P型金属氧化物半导体(PMOS)器件，诸如晶体管、电容器、电阻器、二极管、光电二极管、熔丝等，它们被互连以执行一种或多种功能。功能可以包括存储结构、处理结构、传感器、放大器、功率分配、输入/输出电路等。本领域的技术人员应该理解，上述实施例中只是示意性的目的，以进一步解释一些说明性实施例的应用并且不以任何方式限制本公开。其他电路可根据需要用于给定的应用。
图1A还示出了形成在衬底10上方的互连结构14，其包括多个介电层16和相关的金属化层(未示出)。例如，至少一个介电层16可包括低介电系数(低K)材料，诸如磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、氟化硅酸盐玻璃(FSG)、SiOxCy、旋涂玻璃、旋涂聚合物、碳化硅材料、它们的化合物、它们的复合物、它们的组合等，其可通过诸如旋转、化学汽相沉积(CVD)和/或等离子体增强CVD(PECVD)的任何适当方法来形成。形成在介电层16中的金属化层的金属线或金属通孔被用于互连电路12并提供外部电连接。金属化层可由铜或铜合金形成，尽管它们也可以由其他金属形成。本领域技术人员应该会知晓金属化层的形成细节。此外，金属化层包括顶部金属层18，其形成在最上面的介电层16T中或上并被图案化以提供外部电连接并保护下面的层免受各种环境污染。根据一些实施例，最上面的介电层16T可以由介电材料形成，诸如氮化硅、氧化硅、非掺杂硅玻璃等。在一些实施例中，顶部金属层18由铜或铜合金形成，如果有必要的话，其是导电路由的一部分并具有通过平坦化工艺(诸如化学机械抛光(CMP))处理的暴露表面。在实施例中，顶部金属层18是焊盘区域，凸块结构将形成在其上以将衬底10中的集成电路连接至外部部件。
参照图1B，第一金属化层20以自对准方式形成为覆盖焊盘区域18。在实施例中，化学镀工艺22用于在焊盘区域18的暴露部分上沉积金属层。第一金属化层20可具有单层结构或包括由不同材料形成的多个子层的复合结构，并且可包括从主要由镍(Ni)、钛(Ti)、锡(Sn)、锡铅(SnPb)、金(Au)、银、钯(Pd)、铟(In)、镍钯金(NiPdAu)、镍金(NiAu)、锡基合金或钯基合金、其他类似材料、或通过化学镀工艺或浸镀工艺形成的合金所组成的组中选出的层。在一些实施例中，第一金属化层20具有大约0.2至3.0μm的厚度，例如0.3～0.5μm。在一个实施例中，金属覆盖层20是包括化学镀镍层、化学镀钯层和浸镀金层的三层结构，其也称为ENEPIG结构。在一个实施例中，第一金属化层20是包括化学镀镍层和化学镀钯层的双层结构，称为ENEP结构。在一个实施例中，金属覆盖层20是单层结构，其包括化学镀镍层、浸镀锡层或化学镀钛层。第一金属化层20也被称为直接形成在焊盘区域18上的自对准凸块下金属化(UBM)层。第一金属化层20可防止焊盘区域18中的铜被氧化和/或扩散到接合材料中。防止铜氧化和/或扩散增加了封装件的可靠性和接合强度。
接下来，如图1C所示，在所得到的结构上方形成一个或多个钝化层，诸如钝化层24。钝化层24被图案化以形成暴露第一金属化层20的部分20A的开口25。钝化层24可由介电材料形成，诸如非掺杂硅酸盐玻璃(USG)、氮化硅、二氧化硅、氧氮化硅或通过适当方法(诸如CVD、PVD等)形成的非多孔材料。在一个实施例中，钝化层24被形成为覆盖第一金属化层20的外围部分，并且通过钝化层24中的开口25暴露第一金属化层20的中心部分。钝化层24可以是单层或层积层。
接下来，如图1D所示，然后保护层26形成在钝化层24和暴露的第一金属化层20上。使用光刻和/或蚀刻工艺，进一步图案化保护层26以形成暴露第一金属化层20的开口27。在一些实施例中，暴露部分20A包括第一部分20B1和第二部分20B2。第一部分20B1可以是暴露部分20A的中心部分，以及第二部分20B2可以是暴露部分20A的外围部分。在一些实施例中，保护层26的开口27暴露第一部分20B1并覆盖第二部分20B2，使得保护层26位于第一金属化层20上。在一些实施例中，保护层26由聚合物层形成，诸如环氧树脂、聚酰亚胺、苯并环丁烯(BCB)、聚苯并恶唑(PBO)等，尽管还可以使用其他相对较软、通常为有机的介电材料。根据一些实施例，保护层26位于金属覆盖层上并用作应力缓冲层。
参照图1E，第二金属化层28和焊料凸块30顺序形成在所得到的结构上，以与第一金属化层20和焊盘区域18电接触。第二金属化层28是可选择的层，其可以包括钛、氮化钛、钽、氮化钽、铜、铜合金、镍、金、铝及它们的组合，并且可以使用物理汽相沉积、电镀、喷镀等形成。第二金属化层28有助于改善随后形成的焊料凸块的粘附性和封装可靠性。在一些实施例中，第二金属化层28是包括钛层和铜层的双层结构，其中钛层具有大约0.01μm至0.1μm之间的厚度，铜层具有大约0.1μm至0.5μm之间的厚度。在一些实施例中，第二金属化层28是包括钛层、铜层和镍层的三层结构，其中钛层具有大约0.01μm至0.1μm之间的厚度，铜层具有大约0.1μm至0.5μm之间的厚度，以及镍层具有大约0.1μm至0.5μm之间的厚度。第二金属化层28的制造包括：沉积一个或多个金属层并将焊料凸块30用作掩模来图案化金属层。因此，第二金属化层28沿着保护层26的开口27的侧壁和底部形成在焊料凸块30的下方并延伸至保护层27的顶面。通过电镀或球工艺在第二金属化层28上方形成焊料凸块30。焊料凸块30可包括无铅预焊层、SnAg或包括锡、铅、银、铜、镍、铋或它们的组合的合金的焊料。
在焊盘区域18上方完成包括第一金属化层20、第二金属化层28和焊料凸块30的凸块结构。在凸块结构中，第一金属化层20和第二金属化层28形成焊料凸块30下方的UBM结构32。在UBM结构32中，第一金属化层20是自对准UBM层，以及第二金属化层28是可选的UBM层。在凸块形成之后，例如，可以形成密封剂，可以执行切割工艺以分离各个管芯，以及可以执行晶圆级或管芯级堆叠等。然而，应该注意，实施例可用于不同的情况。例如，实施例可用于管芯-管芯接合结构、管芯-晶圆接合结构、晶圆-晶圆接合结构、管芯级封装、晶圆级封装等。
本实施例提供了作为自对准金属覆盖层的第一金属化层20以防止运输期间焊盘区域18的铜氧化。以自对准方式，通过化学镀工艺在焊盘区域18上形成第一金属化层20。这也简化了凸块形成工艺，从而显著减少了工艺成本。本实施例提供了作为自对准UBM层的第一金属化层20，并且提供了作为位于自对准UBM层上的应力缓冲层的保护层26，使得可以有效释放凸块应力，可以增强凸块可靠性裕度，并且可以实现提高电迁移(EM)寿命的加强凸块方案。因此，根据一些实施例，可以减少凸块裂缝并且可以消除低K介电质分层。已经发现，在焊盘区域具有自对准UBM层的凸块结构显著释放了凸块应力，并且聚合物层下方的低k介电层可以减少30％的应力。因此，在封装装配工艺中，可以增加连接可靠性并且可以降低凸块疲劳。
图1A至1E示出了在形成焊盘区域18之后形成第一金属化层20的实施例。根据一些实施例，第一金属化层20可以在形成钝化层24或形成保护层26之后形成，这将在图2至图4中进行描述。除非特别说明，否则这些实施例中的参考数字与图1A至1E所示的相同。
图2A和2B是示出根据又一实施例的形成凸块结构的方法的截面图。
参照图2A，在形成钝化层24之后，在暴露的焊盘区域18上形成第一金属化层20。在一些实施例中，在形成接合焊盘区域18之后，在介电层16和焊盘区域18上形成钝化层24，然后进行图案化以使开口25暴露焊盘区域18的部分18A。接下来，通过化学镀工艺或浸镀工艺将第一金属化层20形成为覆盖焊盘区域18的暴露部分18A。
参照图2B，在所得到的结构上形成保护层26以覆盖钝化层24和部分第一金属化层20。在一些实施例中，第一金属化层20包括中心部分20C和外围部分20D，其中通过保护层26的开口27暴露中心部分20C，并且通过保护层26覆盖外围部分20D。因此，保护层26位于第一金属化层20的外围部分20D上。然后，在所得到的结构上顺序形成第二金属化层28和焊料凸块30以与第一金属化层20和焊盘区域18电接触。这完成了凸块结构，其包括焊盘区域18上的第一金属化层20，其中第一金属化层20是位于钝化层24的开口25内并被保护层26部分覆盖的自对准UBM层。
图3A和3B是示出根据又一个实施例的形成凸块结构的方法的截面图。
参照图3A，在形成钝化层24和保护层26之后，在暴露的焊盘区域18上形成第一金属化层20。在一些实施例中，在形成接合焊盘区域18之后，在介电层16和焊盘区域18上形成钝化层24，然后进行图案化以使开口25暴露焊盘区域18的部分18A。焊盘区域18的暴露部分18A包括第一部分18B1和第二部分18B2。在一些实施例中，第一部分18B1是暴露部分18A的中心部分，而第二部分18B2是暴露部分18A的外围部分。
接下来，保护层26被形成为覆盖钝化层24和暴露部分18A的第二部分18B2，而通过保护层26的开口27(诸如如图1D所示)暴露了暴露部分18A的第一部分18B1。因此，保护层26位于焊盘区域18的第二部分18B2上。然后，通过化学镀工艺或浸镀工艺将第一金属化层20形成为覆盖焊盘区域18的第一部分18B1。参照图3B，在所得到的结构上顺序形成第二金属化层28和焊料凸块30以与第一金属化层20和焊盘区域18电接触。这完成了凸块结构，其包括位于焊盘区域18上的第一金属化层20，其中第一金属化层20是保护层26的开口27内的自对准UBM层。
图4A至4C是示出根据又一个实施例的形成凸块结构的方法的截面图。
参照图4A，在形成钝化层24之后，在暴露的焊盘区域18上形成第一金属化层20，并且第一金属化层20具有延伸至钝化层24的顶面24T的边缘部分20E。在一些实施例中，钝化层24形成在介电层16和焊盘区域18上以使开口25暴露焊盘区域18的部分18A。接下来，通过化学镀工艺或浸镀工艺将第一金属化层20形成为覆盖焊盘区域18的暴露部分18A。通过控制工艺的时间和镀速率，可以使第一金属化层20形成为从钝化层24的顶面24T突出，使得第一金属化层20的顶面20T高于钝化层24。第一金属化层20的厚度T可变得大于0.3μm，例如0.3≤T≤10μm。在一个实施例中，第一金属化层20还包括延伸至钝化层24的顶面24T的边缘部分20E。边缘部分20E具有大于或等于2μm的宽度W，例如，2≤W≤10μm。
参照图4B，在所得到的结构上形成保护层，以覆盖钝化层24和部分第一金属化层20，而通过保护层26的开口27暴露第一金属化层20的部分20F。在一个实施例中，保护层26覆盖第一金属化层20的边缘部分20E。因此，保护层26位于第一金属化层20上方。
然后，如图4C所示，在所得到的结构上顺序形成第二金属化层28和焊料凸块30，以与第一金属化层20和焊盘区域18电接触。这完成了凸块结构，其包括位于焊盘区域18上的第一金属化层20，其中第一金属化层20是夹在钝化层24和保护层26之间并具有延伸至钝化层24的边缘部分20E的自对准UBM层。
根据一些实施例，提供了一种形成凸块结构的方法，包括：通过化学镀工艺或浸镀工艺在半导体衬底的顶部金属层上形成第一金属化层；在第一金属化层上形成钝化层；在钝化层中形成开口以暴露部分第一金属化层，其中第一金属化层的暴露部分包括第一部分和第二部分；在聚合物层和第一金属化层上形成保护层；在保护层中形成开口以暴露第一金属化层的第一部分并覆盖第一金属化层的第二部分；以及在保护层上方形成焊料凸块，以电连接第一金属化层。
根据一些实施例，提供了一种形成凸块结构的方法，包括：在半导体衬底的顶部金属层上形成钝化层；在钝化层中形成开口，以暴露部分顶部金属层；通过化学镀工艺或浸镀工艺在顶部金属层的暴露部分上形成第一金属化层；在聚合物层和第一金属化层上形成保护层；在保护层中形成开口，以暴露第一金属化层的第一部分并覆盖第一金属化层的第二部分；以及在保护层上方形成焊料凸块，以电连接第一金属化层。
根据一些实施例，提供了一种形成凸块结构的方法，包括：在半导体衬底的顶部金属层上形成钝化层；在钝化层中形成开口，以暴露顶部金属层的一部分，其中顶部金属层的暴露部分包括第一部分和第二部分；在聚合物层和顶部金属层的暴露部分上形成保护层；在保护层中形成开口，以暴露顶部金属层的第一部分并覆盖暴露的顶部金属的第二部分；通过化学镀工艺或浸镀工艺在顶部金属层的第一部分上形成第一金属化层；以及在保护层上方形成焊料凸块，以电连接第一金属化层。
虽然参照示例性实施例具体示出并描述了本公开，但本领域技术人员应该理解，本公开可以具有许多实施例的变化。尽管详细描述了实施例及其特征，但应该理解，可以进行各种更改、替换和变更而不背离本实施例的精神和范围。
上面的方法实施例示出了示例性步骤，但是它们没必要以所示顺序执行。根据本公开的精神和范围，可以根据需要、替换、改变顺序和/或消除步骤。在阅读本公开之后，组合不同权利要求和/或不同实施例的实施例均在本公开的范围内并且对于本领域技术人员来说是显而易见的。

Claims (20)

1.一种形成凸块结构的方法，包括：
通过化学镀工艺或浸镀工艺在半导体衬底的顶部金属层上形成第一金属化层，其中，所述第一金属化层未横向延伸越过所述顶部金属层的横向外边缘；
在所述第一金属化层上方形成钝化层；
在所述钝化层中形成开口，以暴露所述第一金属化层，其中暴露的所述第一金属化层包括第一部分和第二部分；
在所述钝化层和所述第一金属化层上形成保护层；
在所述保护层中形成开口，以暴露所述第一金属化层的第一部分而覆盖所述第一金属化层的第二部分；以及
在所述保护层上方形成电连接至所述第一金属化层的焊料凸块。
2.根据权利要求1所述的方法，其中，所述第一金属化层包括镍层、锡层、钛层、钯层和金层中的至少一个。
3.根据权利要求1所述的方法，其中，所述顶部金属层是包括铜的焊盘区域。
4.根据权利要求1所述的方法，进一步包括：在所述第一金属化层和所述焊料凸块之间形成第二金属化层。
5.根据权利要求4所述的方法，其中，所述第二金属化层包括钛层、铜层和镍层中的至少一个。
6.根据权利要求1所述的方法，其中，所述钝化层包括介电层，并且所述保护层包括聚合物层。
7.根据权利要求1所述的方法，进一步包括：在形成所述第一金属化层之前，对所述顶部金属层执行抛光工艺。
8.一种形成凸块结构的方法，包括：
在半导体衬底的顶部金属层上形成钝化层；
在所述钝化层中形成开口以暴露所述顶部金属层的一部分；
通过化学镀工艺或浸镀工艺在所述顶部金属层的暴露部分上形成第一金属化层，其中，所述第一金属化层未横向延伸越过所述顶部金属层的横向外边缘；
在所述钝化层和所述第一金属化层上形成保护层；
在所述保护层中形成开口，以暴露所述第一金属化层的第一部分而覆盖所述第一金属化层的第二部分；以及
在所述保护层上方形成电连接至所述第一金属化层的焊料凸块。
9.根据权利要求8所述的方法，其中，所述第一金属化层包括延伸至所述钝化层的顶面的边缘部分。
10.根据权利要求9所述的方法，其中，所述保护层覆盖所述第一金属化层的所述边缘部分。
11.根据权利要求8所述的方法，其中，所述第一金属化层包括镍层、锡层、钛层、钯层和金层中的至少一个。
12.根据权利要求8所述的方法，其中，所述顶部金属层是包括铜的焊盘区域。
13.根据权利要求8所述的方法，进一步包括：在所述第一金属化层和所述焊料凸块之间形成第二金属化层。
14.根据权利要求13所述的方法，其中，所述第二金属化层包括钛层、铜层和镍层中的至少一个。
15.根据权利要求8所述的方法，其中，所述钝化层包括介电层，并且所述保护层包括聚合物层。
16.一种形成凸块结构的方法，包括：
在半导体衬底的顶部金属层上形成钝化层；
在所述钝化层中形成开口以暴露所述顶部金属层，暴露的所述顶部金属层包括第一部分和第二部分；
在所述钝化层和暴露的所述顶部金属层上形成保护层；
在所述保护层中形成开口以暴露所述顶部金属层的第一部分而覆盖暴露的所述顶部金属层的第二部分；
通过化学镀工艺或浸镀工艺在所述顶部金属层的第一部分上形成第一金属化层，其中，所述第一金属化层未横向延伸越过所述顶部金属层的横向外边缘；以及
在所述保护层上方形成电连接至所述第一金属化层的焊料凸块。
17.根据权利要求16所述的方法，其中，所述第一金属化层包括镍层、锡层、钛层、钯层和金层中的至少一个。
18.根据权利要求16所述的方法，其中，所述顶部金属层是包括铜的焊盘区域。
19.根据权利要求16所述的方法，进一步包括：在所述第一金属化层和所述焊料凸块之间形成第二金属化层。
20.根据权利要求19所述的方法，其中，所述第二金属化层包括钛层、铜层和镍层中的至少一个。
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