CN102842537A - 具有位于后钝化部上方的势垒层的凸块结构 - Google Patents

具有位于后钝化部上方的势垒层的凸块结构 Download PDF

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Publication number
CN102842537A
CN102842537A CN2011103448548A CN201110344854A CN102842537A CN 102842537 A CN102842537 A CN 102842537A CN 2011103448548 A CN2011103448548 A CN 2011103448548A CN 201110344854 A CN201110344854 A CN 201110344854A CN 102842537 A CN102842537 A CN 102842537A
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layer
barrier layer
semiconductor device
interconnection
connection pads
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CN102842537B (zh
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卢祯发
刘重希
李明机
余振华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种半导体器件包括：势垒层，位于焊料凸块和后钝化互连(PPI)层之间。势垒层由无电镀镍(Ni)层、无电镀钯(Pd)层、或者浸渍(Au)层中的至少一个形成。

Description

具有位于后钝化部上方的势垒层的凸块结构
相关申请的交叉参考
本申请涉及于2010年10月19日提交的申请号为12/907,249的共同待决的美国申请，其全部内容结合于此作为参考。
技术领域
本发明涉及半导体器件的制造，更具体地，涉及半导体器件中的凸块结构。
背景技术
现代集成电路实际上由成百上千的诸如晶体管和电容器的有源器件组成。这些器件最初彼此隔离，但是稍后互连在一起，从而形成功能电路。典型的互连结构包括：横向互连，例如金属线(布线)；和垂直互连，例如，通孔和接触。互连越来越多地决定现代集成电路的性能和密度的局限。在互连结构的顶部，在各个芯片的表面上形成结合焊盘，并且露出该接合焊盘。通过接合焊盘进行电连接，从而将芯片连接至封装衬底或另一管芯。可以将接合焊盘用于引线接合或倒转芯片接合。倒装芯片封装利用凸块建立在芯片的I/O焊盘和封装件的衬底或引线框之间的电接触。在结构上，凸块实际上包括：凸块本身和“凸块下金属”(UBM)，该凸块下金属位于凸块和I/O焊盘之间。
现在，晶圆级芯片规模封装(WLCSP)广泛用于其低成本和相对简单的工艺。在典型的WLCSP中，在钝化层上形成诸如重新分布线(RDL)的后钝化互连(PPI)线，然后，形成聚合物薄膜和凸块。现有的UBM形成工艺需要物理汽相沉积(PVD)步骤，金属电镀步骤，或者这两个步骤的组合，从而形成金属化膜。进一步需要利用光刻和蚀刻工艺施加光刻胶材料，从而限定用于与凸块接触的UBM面积。然而，蚀刻工艺使聚合物薄膜的表面变粗糙，从而在晶圆背侧研磨工艺以后，可能导致残余物。
发明内容
为解决上述问题，本发明提供给了一种半导体器件，包括：半导体衬底；钝化层，覆盖半导体衬底；互连层，覆盖钝化层，包括线区域和连接焊盘区域；保护层，覆盖互连层，并且露出互连层的连接焊盘区域；势垒层，形成在连接焊盘区域的露出部分上；以及焊料凸块，形成在势垒层上；其中，势垒层包括：镍(Ni)层、钯(Pd)层、或者金(Au)层中的至少一个。
其中，互连层包括铜。
其中，势垒层为无电镀Ni/无电镀Pd/浸渍Au(ENEPIG)结构。
其中，势垒层为无电镀Ni/无电镀Pd(ENEP)结构。
其中，势垒层为无电镀Ni/浸渍Au(ENIG)结构。
其中，保护层包括聚合物层。
其中，保护层具有露出连接焊盘区域的开口，并且开口具有大于或等于20μm的直径。
其中，势垒层形成在保护层的开口内。
该半导体器件进一步包括：另一保护层，位于互连层和钝化层之间。
其中，半导体衬底包括导电焊盘，其中，通过钝化层部分地覆盖导电焊盘，并且将导电焊盘电连接至互连层的线区域。
此外，本发明一种封装组件，包括：
半导体器件包括：后钝化互连PPI层，包括线区域和连接焊盘区域；聚合物层，覆盖PPI层的线区域，并且露出PPI层的连接焊盘区域；以及势垒层，位于PPI层的露出的连接焊盘区域上；衬底，包括导电区域；以及焊接点结构，位于半导体器件的势垒层和衬底的导电区域之间；其中，势垒层包括：镍(Ni)层、钯(Pd)层、或者金(Au)层中的至少一个。
其中，互连层包括铜。
其中，势垒层为无电镀Ni/无电镀Pd/浸渍Au(ENEPIG)结构。
其中，势垒层为无电镀Ni/无电镀Pd(ENEP)结构。
其中，势垒层为无电镀Ni/浸渍Au(ENIG)结构。
其中，聚合物层具有露出连接焊盘区域的开口，并且开口具有大于或等于20μm的直径。
此外，还提供了一种形成半导体器件的方法，包括以下步骤：提供半导体衬底；形成覆盖半导体衬底的钝化层；形成覆盖钝化层的互连层，互连层包括线区域和连接焊盘区域；形成覆盖互连层的保护层；在保护层中形成开口，从而露出互连层的连接焊盘区域；通过无电镀工艺或者浸渍电镀工艺在保护层的开口内的焊盘区域上形成势垒层；以及在势垒层上形成焊料凸块；其中，势垒层包括：镍(Ni)层、钯(Pd)层、或者金(Au)层中的至少一个。
其中，形成焊料凸块包括：将焊料球附接在势垒层上。
其中，开口的直径大于或等于20μm。
其中，势垒层包括：无电镀镍(Ni)层、无电镀钯(Pd)层、或者浸渍金(Au)层中的至少一个。
附图说明
图1-5为根据示例性实施例示出形成具有凸块结构的半导体器件的方法的各种中间阶段的横截面图；以及
图6为根据示例性实施例的封装组件的横截面图。
具体实施方式
下面，详细讨论本发明实施例的制造和使用。然而，应该理解，实施例提供了许多可以在各种具体环境中实现的可应用的发明概念。所讨论的具体实施例仅仅示出制造和使用实施例的具体方式，而不用于限制本发明的范围。本文所讨论的实施例涉及用于半导体器件的凸块结构的使用方式。如下文中所讨论的，公开了为了将一个衬底附接至另一衬底使用凸块结构的实施例，其中，每个衬底可以为管芯、晶圆、插入衬底、印刷电路板、封装衬底等，从而允许管芯到管芯、晶圆到管芯、晶圆到晶圆、管芯或者晶圆到插入衬底或印刷电路板或者封装衬底等。在整个附图和所描述的实施例中，将相同的参考标号用于指定相同的元件。
现在，将具体结合在附图中所示的示例性实施例作为参考。在可能的情况下，在附图和描述中使用相同的参考标号，从而指的是相同或相似的部件。在附图中，为了清楚和方便，可以放大形状和厚度。该描述尤其涉及根据本发明形成装置的一部分的元件或者直接地与该装置配合的更多元件。应该理解，没有具体示出或描述的元件可以采用本领域技术人员已知的各种形式。此外，当将层称作位于另一层上或者衬底“上”时，该层可能直接位于另一层上方或者该衬底上方，或者还可以存在中间层。整个本说明书中引用“一个实施例”或“某个实施例”意味着至少一个实施例包括关于所述实施例而描述的特定部件、结构或特征。因此在本说明书的各个位置出现的短语“在一个实施中”或“在某个实施例中”不一定均指同一个实施例。而且，在一个或多个实施例中可以以任何合适的方式组合特定部件、结构或特征。应理解，以下附图没有按比例绘制；而这些附图只是为了阐明。
图1-图4示出了根据实施例形成半导体器件中的凸块结构的方法的各个中间阶段。首先，参考图1，根据实施例示出了衬底10的一部分，该衬底具有形成在其上的电路12。例如，衬底10可以包括：绝缘体上半导体(SOI)衬底的体硅、掺杂或未掺杂、或者有源层。通常，SOI衬底包括：形成在绝缘体层上的半导体材料(例如，硅)的层。绝缘层可以为例如，隐埋氧化物(BOX)层或者氧化硅层。可以将绝缘体层设置在衬底上，通常为硅衬底或者玻璃衬底。还可以使用其他衬底，例如，多层或梯度衬底。
形成在衬底10上的电路12可以为适用于特定应用的任何类型的电路。在实施例中，电路12包括：形成在衬底10上的电气器件，该衬底具有覆盖电气器件的一个或多个介电层。可以在介电层之间形成金属层，从而在电气器件之间传递电信号。还可以在一个或多个介电层中形成电气器件。例如，电路12可以包括：互连的诸如晶体管的各种N型金属氧化物半导体(NMOS)和/或P型金属氧化物半导体(PMOS)器件、电容器、电阻器、二极管、发光二极管、熔丝等，从而实施可以一种或多种功能。多种功能可以包括：存储结构、处理结构、传感器、放大器、功率分布、输入/输出电路等。本领域中的技术人员之一应该理解，仅为了说明的目的，提供了以上实例，从而进一步说明了一些示例性实施例的应用，并且不是为了以任何方式限定本发明。可以将其他电路适当用于给定应用。
在图1中还示出了层间介电(ILD)层14。例如，ILD层14可以通过诸如旋涂、化学汽相沉积(CVD)、和/或等离子增强CVD(PECVD)的任何适当方法由低k介电材料(例如，磷硅玻璃(PSG)、硼磷硅玻璃(BPSG)、掺氟硅玻璃(FSG)、SiOxCy、旋涂玻璃、旋涂聚合物、碳化硅材料、其化合物、其组合物、或者其组合等)形成。还应该注意，ILD层14可以包括多个介电层。可以形成穿过ILD层14的触点(未示出)，从而提供与电路12的电接触。例如，触点可以由TaN、Ta、TiN、Ti、CoW、铜、钨、铝、银等，或者其组合的一层或多层形成。
在ILD层14的上方形成一个或多个金属间介电(IMD)层16和相关金属化层18。通常，将一个或多个IMD层16和相关金属化层(例如，金属线18和通孔19)用于彼此互连电路12，并且提供外部电连接。IMD层16可以由低k介电材料形成，例如，由通过PECVD技术或高密度等离子体CVD(HDPCVD)所形成的FSG形成，并且该IMD层可以包括中间蚀刻停止层。应该注意，一个或多个蚀刻停止层(未示出)可以位于介电层中的相邻介电层之间，例如，位于ILD层14和IMD层16之间。通常，当形成通孔和/或触点时，蚀刻停止层提供停止蚀刻工艺的机制。蚀刻停止层可以由介电材料形成，该介电材料具有与相邻层(例如，下层半导体衬底10、上层ILD层14、以及上层IMD层16)不同的蚀刻选择性。在实施例中，蚀刻停止层可以由通过CVD或者PECVD技术沉积的SiN、SiCN、SiCO、CN、其组合等形成。
金属化层可以由铜或铜合金形成，该金属化层还可以由其他金属形成。本领域的技术人员应理解金属化层的形成细节。此外，金属化层包括：在最上IMD层16T中或上方形成和图案化的顶部金属层20，从而提供外部电连接并且保护下层防止各种环境污染。最上IMD层16T可以由介电材料(例如，氮化硅、氧化硅、未掺杂硅玻璃等)形成。在随后的附图中，没有示出半导体衬底10、电路12、ILD层14、IMD层14、以及金属化层18和19。将顶部金属层20形成为位于最上IMD层16T上方的顶部金属化层的一部分。
下文中，形成和图案化导电焊盘22，从而与顶部金属层20接触，或者作为选择，通过通孔电连接至顶部金属层20。导电焊盘22可以由铝、铝铜(aluminum copper)、铝合金、铜、铜合金等形成。
参考图1，在导电焊盘22的上方形成和图案化诸如钝化层24的一个或多个钝化层。钝化层24可以通过诸如CVD、PVD等的任何适当方法由介电材料(例如，未掺杂硅玻璃(USG)、氮化硅、氧化硅、氮氧化硅、或者非多孔型材料)形成。形成钝化层24，从而覆盖导电焊盘22的外围部分，并且通过在钝化层24中的开口25露出导电焊盘22的中心部分。钝化层24可以为单层或者叠层。本领域中的技术人员之一应该理解，仅为了说明的目的，示出了单层导电焊盘和钝化层。同样地，其他实施例可以包括任何数量的导电层和/或钝化层。
图2示出了在钝化层24上形成和图案化的第一保护层26。例如，第一保护层26可以为聚合物层，将该第一保护层图案化，从而形成开口27，从而露出导电焊盘22。聚合物层可以由诸如环氧树脂、聚酰亚胺、苯并环丁烯(BCB)、聚苯并恶唑(PBO)等的聚合材料形成，但是还可以使用其他相对较软的、通常是有机、介电材料。形成方法包括：旋涂或者其他方法。
下文中，如图3所示，在第一保护层26的上方形成和图案化后钝化互连(PPI)线28并且填充开口27，从而电连接导电焊盘22。PPI线28包括互连线区域28I和连接焊盘区域28P。同时形成互连线区域28I和连接(landing)焊盘区域28P，并且可以由相同的导电材料形成。在随后工艺中在连接焊盘区域28P的上方形成凸块部件，并且将该凸块部件电连接至连接焊盘区域28P。例如，PPI线28可以包括但不限于：使用电镀、无电镀、溅射、化学汽相沉积方法等的铜、铝、铜合金、或者其他多变的(mobile)导体材料。在一些实施例中，PPI线28可以进一步包括：在含铜层顶部的含镍层(未示出)。在一些实施例中，PPI线28还可以用作电源线、重新分布线(RDL)、电感器、电容器、或者任何无源元件。通过PPI线28的传递，连接焊盘区域28P可以(或不)直接位于导电焊盘22的上方。
参考图3，然后，在衬底10的上方形成第二保护层30，从而覆盖PPI线28和第一保护层26的露出部分。使用光刻和/或蚀刻工艺，进一步将第二保护层30图案化，从而形成开口32，露出PPI线28的连接焊盘区域28P。开口32的形成方法可以包括光刻、湿蚀刻或者干蚀刻、激光钻孔等。在一个实施例中，开口32的直径D基本上等于20μm。在另一个实施例中，开口32的直径D大于20μm。在一些实施例中，第二保护层30由聚合物层(例如，环氧树脂、聚酰亚胺、苯并环丁烯(BCB)、聚苯并恶唑(PBO)等)形成，但是还可以使用其他相对较软的、通常是有机介电材料。在一些实施例中，第二保护层30由选自未掺杂的硅玻璃(USG)、氮化硅、氮氧化硅、氧化硅、和其组合的非有机材料形成。
为了保护PPI线28的露出部分，该程序继续在开口32中形成势垒层34。如图4所示，在开口32内的连接焊盘区域28P上形成势垒层34，从而防止PPI线28中的铜扩散到诸如焊料合金的接合材料中，该接合材料用于将衬底10接合至外部材料。防止铜扩散提高了封装件的可靠性和接合强度。势垒层34可以包括通过无电镀工艺或浸渍电镀工艺的镍(Ni)、锡、锡铅(SnPb)、金(Au)、银、钯(Pd)、铟(In)、镍-钯-金(NiPdAu)、镍金(NiAu)、Ni基合金、Au基合金、或者Pd基合金、其他类似材料、或者合金。势垒层34具有约0.1μm-10μm的厚度。在一个实施例中，势垒层34为三层结构，该三层结构包括无电镀Ni层、无电镀Pd层、以及浸渍Au层，该三层结构还称作ENEPIG(无电镀钯镍金)结构。例如，ENEPIG结构可以具有：具有至少2μm厚度的无电镀Ni层，具有至少0.02μm厚度的无电镀Pd层，以及具有至少0.01μm厚度浸渍Au层。在一个实施例中，势垒层34为双层结构，该双层结构包括无电镀Ni层和无电镀Pd层，将该双层结构称作ENEP(无电镀钯镍)结构。在一个实施例中，势垒层34为包括无电镀Ni层的单层结构，该单层结构还称作EN(无电镀镍)结构。在一个实施例中，势垒层34为双层结构，该双层结构包括无电镀Ni层和浸渍Au层，将该双层结构还称作ENIG(无电镀镍金)结构。
如图5所示，在势垒层34上形成焊料凸块36。在一个实施例中，通过将焊料球附接至势垒层34，然后使该材料回流来形成焊料凸块36。焊料凸块36可以包括：无铅前焊料层(lead-free pre-solder layer)，SnAg，或者焊接材料，包括：锡、铅、银、铜、镍、铋的合金、或者其组合。因此，在半导体器件上完成凸块结构。
本实施例提供了势垒层34作为在焊料凸块36和连接焊盘区域28P之间的保护膜，从而防止PPI线28中的铜扩散到焊接材料中。在开口32中形成势垒层34使用无电镀方法，从而提供有源区域作为随后的落球窗(ball-drop window)，该势垒层可以替换传统的凸块下金属(UBM)层。与现有的凸块下金属层(UBM)技术相比较，以上实施例不必在势垒层的形成期间，实施光刻、UBM蚀刻和去除残余物工艺(descum process)，因此，可以降低聚合物表面的粗糙度，并且可以去除带状残余物。这也简化了凸块形成工艺，从而大幅降低工艺成本。已经发现具有势垒层34的凸块结构可与剪切力(shear force)相比较，并且可以降低和/或去除钝化层的应力和裂纹。因此，在封装组件工艺中，可以提高结合可靠型，且可以降低凸块疲劳。
在凸块形成以后，例如，可以形成密封剂，可以实施分离工艺，从而分离独立管芯，并且可以实施晶圆级或管芯级堆叠等。然而，应该注意，可以使用多种不同情况的实施例。例如，可以使用管芯到管芯的接合结构、管芯到晶圆的接合结构、晶圆到晶圆的接合结构、管芯级封装、晶圆级封装等的多个实施例。
图6为示出倒装芯片组件的的示例性实施例的横截面图。上下翻转图5中所示的结构，并且将该结构附接至图6的底部处的另一衬底100。衬底100可以为封装衬底，板(例如，印刷电路板(PCB))、晶圆、管芯、插入衬底、或者其他适当衬底。通过各种导电连接点(attachment point)将凸块结构连接至衬底100。例如，在衬底100上形成和图案化导电区域102。导电区域102为接触焊盘或者导电迹线的一部分，通过掩模层104表示该导电迹线。在一个实施例中，掩模层104为在衬底100上形成和图案化的阻焊层，从而露出导电区域102。掩模层104具有掩模开口，该掩模开口提供了用于形成焊料结合的窗口。例如，焊料层包括锡、铅、银、铜、镍、铋的合金，或者其组合，该焊料层可以被设置在导电区域102上。将衬底10连接至衬底100，从而形成在势垒层34和导电区域102之间形成焊接点结构106。示例性连接工艺包括：焊剂施加、芯片放置、融化焊接点的回流、和/或清洗焊剂残留物。可以将集成电路衬底10、焊接点结构106、以及另一衬底100称作封装组件200，或者在本实施例中，称作倒装芯片封装组件。
根据示例性实施例的一个方面，半导体器件包括：半导体衬底、位于半导体衬底上方的钝化层、以及位于钝化层上方的互连层。互连层包括：线区域和连接焊盘区域。保护层覆盖互连层并且露出互连层的连接焊盘区域。在焊盘区域的露出部分上形成势垒层，并且在势垒层上形成焊料凸块。势垒层由镍(Ni)层、钯(Pd)层、以及金(Au)层中的至少一个形成。
根据示例性实施例的另一方面，封装组件包括：通过连接至衬底所连接的半导体器件。半导体器件包括：后钝化互连(PPI)层，该后钝化互连层具有线区域和连接焊盘区域；聚合物层，覆盖PPI层的线区域并且露出PPI层的连接焊盘区域；以及势垒层，位于PPI层的露出的连接焊盘区域上。衬底包括导电区域。在半导体器件的势垒层和衬底的导电区域之间形成焊接点结构。势垒层由镍(Ni)层、钯(Pd)层、以及金(Au)层中的至少一个形成。
根据示例性实施例的其他方面，形成半导体器件的方法包括以下步骤：形成覆盖半导体衬底的钝化层；形成覆盖钝化层的互连层；形成覆盖互连层的保护层；形成保护层的开口，从而露出互连层的连接焊盘区域；通过无电镀工艺或浸渍电镀工艺在保护层的开口中的焊盘区域上形成势垒层；以及在势垒层上形成焊料凸块。势垒层由镍(Ni)层、钯(Pd)层、以及金(Au)层中的至少一个形成。
在以上详细描述中，参照其特定示例性实施例描述了本发明。然而很明显在不背离本公开的宽泛主旨和范围的情况下，可以做各种更改、结构、工艺和改变。因此，说明书和附图是为了说明而不用于限定。应该理解本发明可以使用各种其它组合和环境且可以在本文中所述的发明概念的范围内改变或更改。

Claims (10)

1.一种半导体器件，包括：
半导体衬底；
钝化层，覆盖所述半导体衬底；
互连层，覆盖所述钝化层，包括线区域和连接焊盘区域；
保护层，覆盖所述互连层，并且露出所述互连层的所述连接焊盘区域；
势垒层，形成在所述连接焊盘区域的所述露出部分上；以及
焊料凸块，形成在所述势垒层上；
其中，所述势垒层包括：镍(Ni)层、钯(Pd)层、或者金(Au)层中的至少一个。
2.根据权利要求1所述的半导体器件，其中，所述互连层包括铜。
3.根据权利要求1所述的半导体器件，其中，所述势垒层为无电镀Ni/无电镀Pd/浸渍Au(ENEPIG)结构。
4.根据权利要求1所述的半导体器件，其中，所述势垒层为无电镀Ni/无电镀Pd(ENEP)结构。
5.根据权利要求1所述的半导体器件，其中，所述势垒层为无电镀Ni/浸渍Au(ENIG)结构。
6.根据权利要求1所述的半导体器件，其中，所述保护层包括聚合物层。
7.根据权利要求1所述的半导体器件，其中，所述保护层具有露出所述连接焊盘区域的开口，并且所述开口具有大于或等于20μm的直径。
8.根据权利要求7所述的半导体器件，其中，所述势垒层形成在所述保护层的开口内。
9.一种封装组件，包括：
半导体器件包括：
后钝化互连PPI层，包括线区域和连接焊盘区域；
聚合物层，覆盖所述PPI层的所述线区域，并且露出所述PPI层的所述连接焊盘区域；以及
势垒层，位于所述PPI层的露出的连接焊盘区域上；
衬底，包括导电区域；以及
焊接点结构，位于所述半导体器件的所述势垒层和所述衬底的所述导电区域之间；
其中，所述势垒层包括：镍(Ni)层、钯(Pd)层、或者金(Au)层中的至少一个。
10.一种形成半导体器件的方法，包括以下步骤：
提供半导体衬底；
形成覆盖所述半导体衬底的钝化层；
形成覆盖所述钝化层的互连层，所述互连层包括线区域和连接焊盘区域；
形成覆盖所述互连层的保护层；
在所述保护层中形成开口，从而露出所述互连层的所述连接焊盘区域；
通过无电镀工艺或者浸渍电镀工艺在所述保护层的开口内的所述焊盘区域上形成势垒层；以及
在所述势垒层上形成焊料凸块；
其中，所述势垒层包括：镍(Ni)层、钯(Pd)层、或者金(Au)层中的至少一个。
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