CN101425493A - 无铝垫的后端集成电路的晶圆级封装结构 - Google Patents

无铝垫的后端集成电路的晶圆级封装结构 Download PDF

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Publication number
CN101425493A
CN101425493A CNA200810089215XA CN200810089215A CN101425493A CN 101425493 A CN101425493 A CN 101425493A CN A200810089215X A CNA200810089215X A CN A200810089215XA CN 200810089215 A CN200810089215 A CN 200810089215A CN 101425493 A CN101425493 A CN 101425493A
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layer
passivation
macromolecule
rear end
connecting line
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CN101425493B (zh
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游秀美
郭祖宽
杨斐杰
陈世明
郑嘉仁
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明是有关于一种集成电路结构，包括有钝化层；穿孔设于钝化层中；含铜通道形成于穿孔中；高分子层形成于钝化层上，其中高分子层包括有一开口，并暴露出含铜通道；后端钝化连接(PPI)线形成于高分子层中，其中后端钝化连接线延伸至此开口中，并物理性地接触于含铜通道；以及底凸块金属层形成于后端钝化连接线上，并电性连接于后端钝化连接线。本发明提出的集成电路结构，可减少电阻电容延迟(RC－Delay)效应和减少制程成本。

Description

无铝垫的后端集成电路的晶圆级封装结构
技术领域
本发明是有关于一种集成电路，且特别是有关于制程的后端的集成电路。
背景技术
目前集成电路可以说是由数以百万的主动元件(例如电晶体和电容)所组成，这些元件最初是相互隔离的，接着再相互连接一起，以形成功能性电路。传统的相互连接(Interconnection)结构包括横向互连，例如：金属线(接线)，以及垂直互连，例如：穿孔(Via)和接面(Contact)。相互连接结构已逐渐地决定现代集成电路的性能限度和密度。
在连接结构的上方，接垫(Bond pads)形成并暴露于晶片的表面，可形成电性连接并经由接垫来连接晶片至一封装结构或另一晶片，接垫可用以进行打线接合(Wire bonding)或覆晶接合(Flip-chip boning)。
由于低成本和制程相对简单，晶圆级封装(Wafer Level Chip ScalePackage；WLCSP)目前已被广泛地使用。在传统WLCSP中，连接结构可形成于金属沉积层，其接着形成底凸块金属层(Under-Bump Metallurgy；UBM)和设置焊球(Solder ball)。图1为一种使用于WLCSP中的传统连接结构的剖面图，金属线102形成于一上金属层中，钝化层104形成于此上金属层上，铝垫106形成于钝化层104上，并透过铝通道108来连接于金属线102。
钝化层110形成于钝化层104和铝垫106上，且一开口形成于钝化层110中，以暴露出铝垫106。高分子层112接着形成于钝化层110上，并被图案化，以暴露出铝垫106。后钝化连接(Post-passivation interconnect；PPI)线114，其接着形成高分子层116和底凸块金属层(UBM)118，接着，设置焊球120于底凸块金属层118上。
然而，铝垫106和连接铝线的存在会造成电阻电容延迟(RC-Delay)效应的增加，其导致铝线和铝垫的电阻增加，以及寄生电容的增加。因此，需要改善制程的后端来解决此问题。
有鉴于上述现有的集成电路的晶圆级封装存在的缺陷，本发明人基于从事此类产品设计制造多年丰富的实务经验及专业知识，并配合学理的运用，积极加以研究创新，以期创设一种新型的无铝垫的后端集成电路的晶圆级封装结构，能够改进一般现有的集成电路，使其更具有实用性。经过不断的研究、设计，并经过反复试作样品及改进后，终于创设出确具实用价值的本发明。
发明内容
本发明的主要目的在于，克服现有的集成电路的晶圆级封装存在的缺陷，而提供一种新型的无铝垫的后端集成电路的晶圆级封装结构，所要解决的技术问题是使其可减少电阻电容延迟(RC-Delay)效应和减少制程成本，非常适于实用。
本发明的目的及解决其技术问题是采用以下技术方案来实现的。依据本发明提出的一种集成电路结构，其至少包括：一钝化层；一穿孔，设于该钝化层中；一含铜通道，形成于该穿孔中；一高分子层，覆盖于该钝化层上，其中该高分子层包括有一开口，其暴露出该含铜通道；一后端钝化连接线，形成于该高分子层中，其中该后端钝化连接线延伸至该开口中，并物理性地接触于该含铜通道；以及一底凸块金属层，形成于该后端钝化连接线上，并电性连接于该后端钝化连接线。
本发明的目的及解决其技术问题还可采用以下技术措施进一步实现。
前述的集成电路结构，其中所述的后端钝化连接线与该含铜通道的部分区域由相同材料所形成。
前述的集成电路结构，其中所述的含铜通道包括有一铜层，其形成于一粘着层上，该粘着层由该高分子层连续延伸至该穿孔的底部。
前述的集成电路结构，其至少还包括：一介电层；以及一铜单元，形成于该介电层中，且位于该钝化层的下方，其中该铜单元物理性地邻接于该含铜通道。
前述的集成电路结构，其至少还包括：一额外高分子层，形成于该后端钝化连接线和该高分子层上，其中该底凸块金属层至少具有部分位于该额外高分子层的一开口中。
前述的集成电路结构，其中所述的钝化层物理性地接触于该高分子层。
前述的集成电路结构，其中所述的含铜通道具有一宽度大于3μm。
前述的集成电路结构，其至少还包括：一焊球，设置于该底凸块金属层上。
本发明的目的及解决其技术问题还采用以下技术方案来实现。依据本发明提出的一种集成电路结构，其至少包括：一基材；一上介电层，形成于该基材上；一铜单元，形成于该上介电层中；一钝化层，形成于该上介电层上；一第一开口，形成于该钝化层中；一第一高分子层，形成于该钝化层上，其中该第一高分子层包括有一第二开口，其暴露出该第一开口；一后端钝化连接线，包括有一粘着层和一含铜层，其中该粘着层由该第一高分子层延伸至该第一开口和该第二开口，且连接于该铜单元；一第二高分子层，形成于该第一高分子层和该后端钝化连接线上；一第三开口，形成于该第二高分子层中；以及一底凸块金属层，具有至少一部分于该第三开口中，其中该底凸块金属层连接于该后端钝化连接线。
本发明的目的及解决其技术问题还可采用以下技术措施进一步实现。
前述的集成电路结构，其至少还包括：一第一额外铜单元和一第二额外铜单元，形成于该上介电层中；以及一额外后端钝化连接线，位于该第一高分子层上，其中该额外后端钝化连接线包括有一部分延伸至该钝化层和该第一高分子层，且电性连接于该第一额外铜单元和该第二额外铜单元。
本发明的目的及解决其技术问题另外还采用以下技术方案来实现。依据本发明提出的一种集成电路结构，其特征在于其至少包括：一介电层；一铜线，形成于该介电层中；一钝化层，包括有一无机材料，且形成于该介电层上；一高分子层，邻接并形成于该钝化层上；一底凸块金属层，形成于该高分子层上；以及一后端钝化连接线，电性连接于该底凸块金属层和该铜线，其中该后端钝化连接线包括有一部分位于该高分子层上，以及另一部分延伸至该高分子层和该钝化层中，且该后端钝化连接线物理性地连接于该铜线。
本发明的目的及解决其技术问题还可采用以下技术措施进一步实现。
前述的集成电路结构，其至少还包括：一额外高分子层，位于该后端钝化连接线和该高分子层上，其中该额外高分子层暴露于外界空气中。
本发明与现有技术相比具有明显的优点和有益效果。由以上可知，为达到上述目的，本发明的一方面在于提供一种集成电路结构。集成电路结构至少包括有钝化层；穿孔设于钝化层中；含铜通道形成于穿孔中；高分子层形成于钝化层上，其中高分子层包括有一开口，其暴露出含铜通道；后端钝化连接(PPI)线形成于高分子层中，其中后端钝化连接线延伸至此开口中，并物理性地接触于含铜通道；以及底凸块金属层形成于后端钝化连接线上，并电性连接于后端钝化连接线。
本发明的又一方面在于提供一种集成电路结构，其中集成电路结构至少包括有基材；上介电层形成于基材上；铜单元形成于上介电层中；钝化层形成于上介电层上；第一开口形成于钝化层中；第一高分子层形成于钝化层上，其中第一高分子层包括有第二开口，其暴露出第一开口；后端钝化连接线包括有一粘着层和一含铜层，其中粘着层由第一高分子层延伸至第一开口和第二开口，且连接于铜单元；第二高分子层形成于第一高分子层和后端钝化连接线上；第三开口形成于第二高分子层中；以及底凸块金属层具有至少一部分于三开口中，其中该底凸块金属层连接于后端钝化连接线。
本发明的又一方面在于提供一种集成电路结构，其中集成电路结构至少包括有介电层；铜线形成于介电层中；钝化层包括有无机材料，且形成于介电层上；高分子层邻接并形成于钝化层上；底凸块金属层形成于高分子层上；以及后端钝化连接线电性连接于底凸块金属层和铜线，其中后端钝化连接线包括有一部分位于高分子层上，以及另一部分延伸至高分子层和钝化层中，且后端钝化连接线物理性地连接于铜线。
本发明的又一方面在于提供一种集成电路结构的形成方法，其中此方法至少包括：提供半导体基材；形成介电层形成于半导体基材上；形成穿孔于介电层中；形成高分子层于介电层上，其中该介电层具有一开口，且开口暴露出此穿孔；形成后端钝化连接线，其具有部分位于高分子层上，其中后端钝化连接线延伸至此开口和穿孔中；以及形成底凸块金属层于后端钝化连接线上，并电性连接于后端钝化连接线。
本发明的又一方面在于提供一种集成电路结构的形成方法，其中此方法至少包括：提供具有基材、形成于基材上的上介电层以及形成于上介电层上的铜线的晶圆；形成钝化层于上介电层上；形成第一开口于钝化层中；形成第一高分子层于钝化层上；形成第二开口于第一高分子层中，并暴露出第一开口；形成粘着层于第一高分子层上，并延伸至第一开口和第二开口；形成晶种层于粘着层上；形成阻挡层，其具有一第三开口，并暴露出第一开口和第二开口；选择性地形成一铜层于部分晶种层上，并由第三开口暴露出；移除阻挡层；移除部分晶种层以及未受阻挡层保护的铜层；形成第二高分子层于第一高分子层和后端钝化连接线上；形成第四开口形成于第二高分子层中，并暴露出部分铜层；形成底凸块金属层，其中部分底凸块金属层位于第四开口中。
借由上述技术方案，本发明无铝垫的后端集成电路的晶圆级封装结构至少具有可减少电阻电容延迟(RC-Delay)效应和减少制程成本的优点及有益效果。
综上所述，本发明是有关于一种集成电路结构，包括有钝化层；穿孔设于钝化层中；含铜通道形成于穿孔中；高分子层形成于钝化层上，其中高分子层包括有一开口，并暴露出含铜通道；后端钝化连接(PPI)线形成于高分子层中，其中后端钝化连接线延伸至此开口中，并物理性地接触于含铜通道；以及底凸块金属层形成于后端钝化连接线上，并电性连接于后端钝化连接线。本发明提出的集成电路结构，可减少电阻电容延迟(RC-Delay)效应和减少制程成本。
本发明具有上述优点及实用价值，其不论在产品结构或功能上皆有较大改进，在技术上有显著的进步，并产生了好用及实用的效果，且较现有的集成电路具有增进的突出功效，从而更加适于实用，并具有产业的广泛利用价值，诚为一新颖、进步、实用的新设计。
上述说明仅是本发明技术方案的概述，为了能够更清楚了解本发明的技术手段，而可依照说明书的内容予以实施，并且为了让本发明的上述和其他目的、特征和优点能够更明显易懂，以下特举较佳实施例，并配合附图，详细说明如下。
附图说明
图1为一现有习用的后端结构，其中一铝垫形成于上金属层中的一后钝化层连接线和一铜单元之间。
图2及图3C至图16为本发明无铝垫的后端集成电路的晶圆级封装结构的一实施例的制程剖面图。
图3A和图3B为绘示图2的部分俯视图。
10：晶圆                    20：半导体基材
22：层间介电层              24：介电层
26：金属线                  28：金属线、铜单元
30：介电层                  32：钝化层
34：穿孔                    36：高分子层
38：开口
40：层                      401：粘着层
402：薄晶种层               403：金属线
46：阻挡层                  48：开口
50：通道                    52：后钝化层连接线
54：高分子层                56：开口
58：底凸块金属晶种层        60：阻挡层
62：开口                    64：底凸块金属层
68：焊球
70：额外后钝化层连接线      72：铜单元
102：金属线                 104：钝化层
106：铝垫                   108：铝通道
110：钝化层                 112：高分子层
114：后钝化连接线           116：高分子层
118：底凸块金属层           120：焊球
具体实施方式
为更进一步阐述本发明为达成预定发明目的所采取的技术手段及功效，以下结合附图及较佳实施例，对依据本发明提出的无铝垫的后端集成电路的晶圆级封装结构其具体实施方式、结构、特征及其功效，详细说明如后。为了方便说明，在以下的实施例中，相同的元件以相同的编号表示。
请参照图2，一晶圆10包括有半导体基材20。半导体基材20可以一块状硅(Bulk silicon)基材或绝缘上覆硅(Silicon-on-insulator)基材，其他半导体材料包括III族、IV族及V族材料亦可使用。集成电路元件，例如电晶体(未绘示)，形成于半导体基材20的表面。晶圆10还包括有层间介电层(Inter-layer dielectric；ILD)22形成于半导体基材20上，以及金属层形成于层间介电层22上。图2绘示出一底金属层和上金属层，底金属层包括有金属线26形成于介电层24中，上金属层包括有金属线28形成于介电层30中，正如习知技艺所知更多金属层可形成于上金属层和底金属层之间。在本实施例中，在金属层中的介电层，包括介电层24及30较佳由低k值介电常数材料所形成。在其他实施例中，介电层30形成于上金属层上，在此实施例中，介电层可以由非掺杂的硅玻璃(Un-doped SilicateGlass；USG)、氮化硅、氮氧化硅或其他常用材料所形成。低k值介电常数材料的介电常数(k值)较佳小于3.9，更佳小于2.8。金属线26及28较佳由铜或铜合金所形成，因而可分别选择性地视为铜单元26及28，虽然金属线26及28亦可由其他金属所形成。熟悉此领域者应可了解形成金属层的细节，为了简易说明，在以下说明图示中，半导体基材20、层间介电层22及此些金属层中的较低部分并未绘示。
图2亦绘示有钝化层32，其形成于介电层30上。一蚀刻终止层(未绘示)可形成于钝化层32和介电层30之间，在此较佳实施例中，钝化层32由无机材料所形成，无机材料可选自非掺杂的硅玻璃(USG)、氮化硅、氮氧化硅、氧化硅及其任意组合。
钝化层32可图案化，以形成穿孔34，穿孔34中可形成有铜单元28，穿孔34较佳明显小于接垫以及后续在晶圆上所形成的底凸块金属层(Under-Bump Metallurgy；UBM)。穿孔34较佳具有一尺寸，其大于3μm×3μm。在一实施例中，穿孔34可具有尺寸约5μm×5μm。图3A绘示图2的部分俯视图，其绘示出穿孔34直接形成于部分铜单元28(铜线)上。铜单元28亦可为一金属垫或一通道，第3B图绘示另一实施例，其中铜单元28一铜垫，且具有一宽度大于一连接铜线。在其他实施例中，如图3C所示，其一剖面图，铜单元28一通道形成于上金属层中，并由穿孔34所暴露出。
图4绘示高分子层36的形成和图案化，高分子层36较佳一高分子材料所形成，例如：环氧化物、聚亚酰胺(Polyimide；PI)、苯并环丁烯(BCB)及聚苯(PBO)等，亦可使用其他软性、有机的介电材料，其较佳形成方法包括旋转涂布或其他常用方法。高分子层36的厚度较佳约介于5μm和30μm之间。值得注意的是，在本说明中的尺寸仅为范例，其可随着集成电路的微小化而对应改变。
高分子层36可进行图案化来形成开口38，而暴露出穿孔34和铜单元28。可利用光显影技术来图案化高分子层36，接着，进行固化(Curing)步骤，以固化高分子层36。
请参照图5，粘着层401完全形成且覆盖于高分子层36以及开口34及38的侧壁和底部上。粘着层401可具有常用阻隔材料，例如：钛、氮化钛、钽、氮化钽及其任意组合，并可利用物理气相沉积(Physical vapordeposition；PVD)或溅镀(Sputtering)等方式形成。粘着层401可增进后续形成的铜线在高分子层36上的接着能力，粘着层401的厚度较佳可约介于30nm和100nm之间，更佳约50nm。
薄晶种层402完全形成于粘着层401上，薄晶种层402的材料包括有铜或铜合金，以及金属例如：银、金、铝及其任意组合。薄晶种层402的材料亦可包括有铝或铝合金。在一实施例中，薄晶种层402利用溅镀方式来形成，在其他实施例中，其他常用方法亦可使用，例如：物理气相沉积或无电电镀(Electroless plating)，薄晶种层402较佳具有一厚度约小于500nm。粘着层401和薄晶种层402在后续图示中绘示为层40。值得注意的是，虽然图5和后续图示中绘示层40完全填满穿孔34，在其他特殊例子中，层40可仅填满于穿孔34的底部。
请参照图6，阻挡层46预先形成，阻挡层46较佳由光阻材料所形成，其厚度约大于5μm，更佳约介于10μm和50μm之间，阻挡层46可被图案化，以形成开口48，而暴露出部分层40和开口34及38。
在图7中，开口48选择性地填入一金属材料，开口34(如图4所示)亦被完全填满，而形成通道(Via)50。在此较佳实施例中，此填入材料包括铜或铜合金，其他材料，例如：铝、银、金及其任意组合，亦可使用，其形成方法包括有溅镀、印刷、电镀、无电电镀及常用化学气相沉积法(Chemical vapor deposition；CVD)。
在填入金属材料于开口34及38时，相同金属材料亦形成于开口48中，而形成金属线403。在此说明中，金属线403及其下方的层40可视为后钝化层连接(Post-passivation interconnect；PPI)线52，PPI线52较佳具有一厚度约小于30μm，更佳约介于2μm和10μm之间。PPI线52更可包括有含镍层(未绘示)于铜线403的上方，其形成方法包括有溅镀、印刷、电镀、无电电镀及化学气相沉积法等。
在图8中，阻挡层46可被移除，此时，阻挡层46可以一干膜光阻(DryFilm)，其可利用碱性溶液来移除，若阻挡层46由光阻材料所形成，其可利用例如NMP(n-methyl pyrrolidone)、DMSO(dimethyl sulfoxide)或aminoethoxy ethanol等溶液来移除。因此，暴露出位于阻挡层46下方的层40。
请参照图9，层40所暴露出的部分所具有的粘着层和薄晶种层可被移除，在一实施例中，此移除步骤可包括利用一氨基酸来进行等方向性湿蚀刻(Isotropic wet etching)，由于其过程短暂而可视为快速蚀刻(Flashetching)。
图10绘示高分子层54的形成和图案化，高分子层54可具有高分子材料，其可选自环氧化物、聚亚酰胺(PI)、苯并环丁烯(BCB)及聚苯(PBO)等，并利用相同于高分子层36的方法来进行图案化。开口56形成于高分子层54，以暴露出PPI线52。由于高分子层36及56软性材质，因而可具有减少晶圆内应力的功效。另外，高分子层可轻易地形成数十微米(Microns)。
接着，如图11所示，形成底凸块金属(UBM)晶种层58，其包括有一钛层及一铜晶种层位于钛层上。UBM晶种层58可选择性地包括有复数层，其选自一铬铜合金层形成于一铬层上、一铜层形成于一钛钨合金层上、一镍钒合金层形成于一铝层上、一镍钒合金层形成于一钛层上以及其上述任意组合。
图12绘示阻挡层60的形成，其材料大致相同于阻挡层46(如图6所示)，开口62形成于阻挡层60中，以暴露出部分UBM晶种层58。接着，如第13图所示，底凸块金属(UBM)层64形成于开口62中，其形成方法大致相同于金属线403。UBM层64较佳由铜或铜合金所形成，其亦可包括银、铬、镍、锡、金或其任意组合，来形成于铜层上。UBM层64具有一厚度约介于1μm和20μm之间。
图14绘示阻挡层60的移除以及所暴露的UBM晶种层58，其细节相似于图8和图9，因而在此不再赘述。在图15中，焊球68设置于UBM层64上，正如现有习知技艺所知，焊球68可包括有合金例如：锡、铅、银、铜、镍及铋等，或者，亦可利用例如电镀或印刷等方法来形成铜凸块(Bump)于UBM层64上，以取代焊球68。接着，晶圆10可被切割，并被封装于一封装结构或其他晶片上，且具有焊球68设置于封装结构或其他晶片的接垫上。
值得注意的是，若需进行更多其他步骤，相似于PPI线52的额外导电层可形成于PPI线52和UBM层64之间。再者，额外PPI线可与PPI线52同时形成，其中额外PPI线亦可仅用以相互连接于铜单元之间，如图16所示的额外PPI线70，其连接于上金属层的二铜单元72之间。
本发明的实施例具有多个优点，其可避免使用铝垫于上金属单元28和铜PPI线52之间，因而减少电阻电容延迟(RC-Delay)效应，且由于可减少制程步骤，因而减少制程成本。
以上所述，仅是本发明的较佳实施例而已，并非对本发明作任何形式上的限制，虽然本发明已以较佳实施例揭露如上，然而并非用以限定本发明，任何熟悉本专业的技术人员，在不脱离本发明技术方案范围内，当可利用上述揭示的技术内容作出些许更动或修饰为等同变化的等效实施例，但凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本发明技术方案的范围内。

Claims (12)

1.一种集成电路结构，其特征在于其至少包括：
一钝化层；
一穿孔，设于该钝化层中；
一含铜通道，形成于该穿孔中；
一高分子层，覆盖于该钝化层上，其中该高分子层包括有一开口，其暴露出该含铜通道；
一后端钝化连接线，形成于该高分子层中，其中该后端钝化连接线延伸至该开口中，并物理性地接触于该含铜通道；以及
一底凸块金属层，形成于该后端钝化连接线上，并电性连接于该后端钝化连接线。
2.根据权利要求1所述的集成电路结构，其特征在于其中所述的后端钝化连接线与该含铜通道的部分区域由相同材料所形成。
3.根据权利要求2所述的集成电路结构，其特征在于其中所述的含铜通道包括有一铜层，其形成于一粘着层上，该粘着层由该高分子层连续延伸至该穿孔的底部。
4.根据权利要求1所述的集成电路结构，其特征在于其至少还包括：
一介电层；以及
一铜单元，形成于该介电层中，且位于该钝化层的下方，其中该铜单元物理性地邻接于该含铜通道。
5.根据权利要求1所述的集成电路结构，其特征在于其至少还包括：
一额外高分子层，形成于该后端钝化连接线和该高分子层上，其中该底凸块金属层至少具有部分位于该额外高分子层的一开口中。
6.根据权利要求1所述的集成电路结构，其特征在于其中所述的钝化层物理性地接触于该高分子层。
7.根据权利要求1所述的集成电路结构，其特征在于其中所述的含铜通道具有一宽度大于3μm。
8.根据权利要求1所述的集成电路结构，其特征在于其至少还包括：
一焊球，设置于该底凸块金属层上。
9.一种集成电路结构，其特征在于其至少包括：
一基材；
一上介电层，形成于该基材上；
一铜单元，形成于该上介电层中；
一钝化层，形成于该上介电层上；
一第一开口，形成于该钝化层中；
一第一高分子层，形成于该钝化层上，其中该第一高分子层包括有一第二开口，其暴露出该第一开口；
一后端钝化连接线，包括有一粘着层和一含铜层，其中该粘着层由该第一高分子层延伸至该第一开口和该第二开口，且连接于该铜单元；
一第二高分子层，形成于该第一高分子层和该后端钝化连接线上；
一第三开口，形成于该第二高分子层中；以及
一底凸块金属层，具有至少一部分于该第三开口中，其中该底凸块金属层连接于该后端钝化连接线。
10.根据权利要求9所述的集成电路结构，其至少还包括：
一第一额外铜单元和一第二额外铜单元，形成于该上介电层中；以及
一额外后端钝化连接线，位于该第一高分子层上，其中该额外后端钝化连接线包括有一部分延伸至该钝化层和该第一高分子层，且电性连接于该第一额外铜单元和该第二额外铜单元。
11.一种集成电路结构，其特征在于其至少包括：
一介电层；
一铜线，形成于该介电层中；
一钝化层，包括有一无机材料，且形成于该介电层上；
一高分子层，邻接并形成于该钝化层上；
一底凸块金属层，形成于该高分子层上；以及
一后端钝化连接线，电性连接于该底凸块金属层和该铜线，其中该后端钝化连接线包括有一部分位于该高分子层上，以及另一部分延伸至该高分子层和该钝化层中，且该后端钝化连接线物理性地连接于该铜线。
12.根据权利要求11所述的集成电路结构，其特征在于其至少还包括：
一额外高分子层，位于该后端钝化连接线和该高分子层上，其中该额外高分子层暴露于外界空气中。
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