CN105336578A - 具有通孔的堆叠结构上的缓冲层 - Google Patents

具有通孔的堆叠结构上的缓冲层 Download PDF

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Publication number
CN105336578A
CN105336578A CN201410658986.1A CN201410658986A CN105336578A CN 105336578 A CN105336578 A CN 105336578A CN 201410658986 A CN201410658986 A CN 201410658986A CN 105336578 A CN105336578 A CN 105336578A
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substrate
stress
semiconductor substrate
layer
buffer layer
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CN105336578B (zh
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卢祯发
蔡正原
杜友伦
蔡嘉雄
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供了具有通孔的堆叠结构上的缓冲层。一种结构包括第一和第二衬底、第一和第二应力缓冲层和钝化后互连(PPI)结构。第一和第二衬底包括第一和第二半导体衬底以及分别位于所述第一和第二半导体衬底上的第一和第二互连结构。第二互连结构位于第二半导体衬底的第一侧上。第一衬底在接合界面处接合至第二衬底。通孔至少延伸穿过第二半导体衬底进入第二互连结构。第一应力缓冲层位于与第二半导体衬底的第一侧相对的第二半导体衬底的第二侧上。PPI结构位于第一应力缓冲层上且电连接至通孔。第二应力缓冲层位于PPI结构和第一应力缓冲层上。

Description

具有通孔的堆叠结构上的缓冲层
技术领域
本发明涉及具有通孔的堆叠结构上的缓冲层。
背景技术
由于各种电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度的不断提高，半导体行业已经历了快速发展。在极大程度上，集成密度的提高源自于最小部件尺寸的不断减小(例如，将半导体工艺节点向亚20nm节点减小)，这样允许在给定区域内集成更多的组件。由于对小型化的需要，近来已经发展了更高速度和更大的带宽以及更低的功耗和延迟，所以已经提出一种更小且更富创造性的半导体管芯封装技术的需要。
随着半导体技术的进一步发展，例如3D集成电路(3DIC)的堆叠半导体器件已作为一种进一步降低半导体器件的物理尺寸的有效选择而出现。在堆叠半导体器件中，将诸如逻辑、存储、处理器电路等的有源电路制造在不同的半导体晶圆上。两个或更多的半导体晶圆可以彼此堆叠安装以进一步降低半导体器件的形状因数。
两个半导体晶圆可通过合适的接合技术接合在一起。堆叠半导体器件之间可提供电连接。堆叠半导体器件可提供具有较小形状因数的较高密度且考虑到增强的性能和较低的功耗。
发明内容
为解决现有技术中存在的问题，根据本发明的一个方面，提供了一种结构，包括：
第一衬底，包括第一半导体衬底和位于第一半导体衬底上的第一互连结构；
第二衬底，包括第二半导体衬底和位于第二半导体衬底的第一侧上的第二互连结构，第一衬底在接合界面处接合至第二衬底，第一互连结构和第二互连结构设置在第一半导体衬底和第二半导体衬底之间；
通孔，至少延伸穿过第二半导体衬底进入第二互连结构；
第一应力缓冲层，位于第二半导体衬底的第二侧上，第二半导体衬底的第二侧与第二半导体衬底的第一侧相对；
钝化后互连(PPI)结构，位于第一应力缓冲层上且电连接至通孔；以及
第二应力缓冲层，位于PPI结构和第一应力缓冲层上。
根据本发明的一个实施例，通孔延伸超出接合界面且进入第一互连结构。
根据本发明的一个实施例，通孔未延伸超出接合界面。
根据本发明的一个实施例，接合界面基本由电介质与电介质接合构成。
根据本发明的一个实施例，接合界面包括金属与金属接合。
根据本发明的一个实施例，开口穿过PPI结构，第二应力缓冲层至少部分地设置在开口中。
根据本发明的一个实施例，还包括：
凸块下结构，位于PPI结构上；以及
凸块接触件，位于凸块下结构上。
根据本发明的另一方面，提供了一种结构，包括：
接合结构，包括在接合界面处接合在一起的第一衬底和第二衬底，第一衬底包括位于第一介电层中的第一金属化图案，第二衬底包括半导体衬底和位于第二半导体衬底上的第二介电层中的第二金属化图案，接合结构还包括延伸穿过半导体衬底的通孔；
应力缓冲结构，位于半导体衬底上，应力缓冲结构包括第一应力缓冲层和重布件，第一应力缓冲层设置在半导体衬底和重布件之间，重布件电连接至通孔；以及
外部连接件，电连接至重布件。
根据本发明的一个实施例，应力缓冲结构还包括第二应力缓冲层，重布件设置在第一应力缓冲层和第二应力缓冲层之间。
根据本发明的一个实施例，通孔延伸至第二衬底的第二金属化图案的一部分并且未延伸超出接合界面。
根据本发明的一个实施例，通孔延伸至第二衬底的第一金属化图案的一部分。
根据本发明的一个实施例，重布件具有在外部连接件电连接至重布件的区域中穿过重布件的开口。
根据本发明的一个实施例，位于接合界面处的第一衬底的第一表面基本由第一介电材料构成，并且位于接合界面处的第二衬底的第二表面基本由第二介电材料构成，第一表面直接接合至第二表面。
根据本发明的一个实施例，第一金属化图案的第一部分位于接合界面处，并且第二金属化图案的第二部分位于接合界面处，第一金属化图案的第一部分直接接合至第二金属化图案的第二部分。
根据本发明的又一方面，提供了一种方法，包括：
将第一衬底接合至第二衬底，第二衬底包括半导体衬底；
从半导体衬底的一侧形成至少延伸穿过半导体衬底的通孔；
在半导体衬底的一侧上形成第一应力缓冲层；
在第一应力缓冲层上形成电连接至通孔的钝化后互连(PPI)结构；以及
在PPI结构和第一应力缓冲层上形成第二应力缓冲层。
根据本发明的一个实施例，接合基本由电介质与电介质接合构成。
根据本发明的一个实施例，接合包括将第一衬底的第一金属化图案接合至第二衬底的第二金属化图案。
根据本发明的一个实施例，形成通孔包括形成延伸进入第一衬底的通孔。
根据本发明的一个实施例，形成PPI结构包括形成具有穿过PPI结构的开口的PPI结构。
根据本发明的一个实施例，还包括电连接至PPI结构的接触凸块。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明的各方面。应该强调的是，根据工业中的标准实践，没有按比例绘制各种部件。实际上，为了清楚地讨论，各种部件的数量和尺寸可以被任意增加或减少。
图1A、图1B和图2至图8是根据一些实施例的在形成接合结构的中间阶段的结构的各种截面图。
图9是根据一些实施例的图6的修改。
图10A、10B、10C、10D和图10E是根据一些实施例的具有穿过其的开口的钝化后互连件(PPI)的一部分的实例布局图。
图11是根据一些实施例的包括图9的修改的接合结构的截面图。
图12A、图12B和图13至图19是根据一些实施例的在形成接合结构的中间步骤中结构的各种截面图。
图20是根据一些实施例的图17的修改。
图21是根据一些实施例的包括图20的修改的接合结构的截面图。
具体实施方式
以下公开内容提供了许多用于实现主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者第二部件上形成第一部件可以包括以直接接触的方式形成第一部件和第二部件的实施例，且也可以包括在第一部件和第二部件之间可以形成附加部件，使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字母。该重复是为了简单和清楚的目的，并且其本身并没有规定所讨论的各个实施例和/或配置之间的关系。此外，本文讨论的一些方法实施例被讨论为以一种特定顺序实施，然而，其他方法实施例以任意逻辑顺序注重性能方面。
而且，为了便于描述，诸如“下面”、“之下”、“下部”、“之上”、“上部”等的空间相对术语在此可以用于描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的定向之外，空间相对术语旨在包括器件在使用或操作过程中的不同定向。装置可以以其他方式定向(旋转90度或为其他定向)，并且在此使用的空间相对描述符可以同样地作出相应的解释。
本文讨论的实施例是在堆叠和/或接合结构的背景下，且更具体地，具有至少延伸穿过半导体衬底的通孔的堆叠和/或接合结构。本领域的技术人员会很容易地理解可对本文所讨论实施例做出各种修改，其他实施例也可考虑这种修改。
图1A、图1B和图2至图8是根据实施例的在形成接合结构的中间阶段的结构的各种截面图。先参照图1A和图1B，在接合工艺之前，根据各个实施例示出了第一衬底100和第二衬底200。在一个实施例中，第二衬底200与第一衬底100具有相似的部件，并且为了简化下列讨论，第二衬底200的具有“2xx”形式的参考标号的部件与第一衬底的具有“1xx”形式的参考标号的部件相似，其中，“xx”对于第一衬底100和第二衬底200为相同标号。第一衬底100和第二衬底200的各种元件将被分别称为“第一<元件>1xx”和“第二<元件>2xx”。
在一个实施例中，第一衬底100包括具有形成在其上的第一电气电路(由包括第一晶体管104的第一电气电路所示)的第一半导体衬底102。第一半导体衬底102可包括例如块体半导体、绝缘体上半导体(SOI)衬底等，其可以为掺杂或未掺杂。第一半导体衬底102可以是晶圆。通常，SOI衬底包括形成在绝缘层上的半导体材料层。绝缘层可以是例如埋氧(BOX)层、氧化硅层等。绝缘层设置在衬底上，通常为硅或玻璃衬底。也可使用其他衬底，诸如多层或梯度衬底。在一些实施例中，第一半导体衬底102的半导体材料可包括硅、锗、化合物半导体(包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、和/或锑华铟)、合金半导体(包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP)、或它们的组合。
形成在第一半导体衬底102上的第一电气电路可以为适用于特定应用的任何类型的电路。在一个实施例中，电路包括形成在第一半导体衬底102上的电气器件，具有金属化图案的一个或多个介电层覆盖在电气器件的上面。介电层内的金属化图案可在电气器件之间发送电信号和/或将电信号发送到第一衬底100外部的节点。电气器件还可形成在一个或多个介电层内。
例如，第一电气电路可包括诸如晶体管、电容器、电阻器、二极管、光电二极管、熔断器等的各种器件，它们互连以实施一种或多种功能。第一电气电路可包括存储结构、处理结构、传感器、放大器、功率分布、输入/输出电路等。图中所示实例示出了第一衬底100中的第一晶体管104。每个第一晶体管104包括第一半导体衬底102的有源区中的源极/漏极区，其中，有源区被诸如浅沟槽隔离(STI)的隔离区限定在第一半导体衬底102中。每个第一晶体管104还包括设置在相应源极/漏极区之间的第一半导体衬底102上的栅极结构。栅极结构包括第一半导体衬底102上的栅极电介质、栅极电介质上的栅电极、以及栅极电介质和栅电极的相对侧面上的栅极间隔件。本领域的技术人员会意识到，提供的上述实例为说明目的。根据情况，其他电路可用于指定应用。
图1还示出了第一层间介电(ILD)层106和第一金属间介电(IMD)层108和110。第一ILD层106和第一IMD层108和110可通过诸如旋涂、化学气相沉积(CVD)、和等离子体增强CVD(PECVD)的现有技术中已知的任意合适方法由例如低K介电材料形成，诸如磷硅酸玻璃(PSG)、硼磷硅酸玻璃(BPSG)、FSG、SiOxCy、旋涂玻璃、旋涂聚合物、碳化硅材料、它们的化合物、它们的合成物、它们的组合等。还应该注意，第一ILD层106和第一IMD层108和110可包括任意数量的介电层。
形成穿过第一ILD层106的第一接触件130以提供至第一晶体管104(诸如至第一晶体管104的源极/漏极区)的电接触件。例如，通过使用光刻工艺沉积和图案化第一ILD层106上的光刻胶材料以暴露出第一ILD层106的即将成为第一接触件130的部分，从而可形成第一接触件130。诸如各向异性干蚀刻工艺的蚀刻工艺可用于在第一ILD层106中形成开口。开口可与扩散势垒层和/或粘合层(未示出)排成一行并且填充有导电材料。扩散势垒层可包括一层或多层TaN、Ta、TiN、Ti、CoW等，并且导电材料可包括铜、钨、铝、银、和它们的组合等，从而形成图1A和图1B所示的第一接触件130。
同样地，可包括至下面金属化图案的通孔的第一金属化图案132、134和136分别形成在第一ILD层106和第一IMD层108和110中。例如，通过使用光刻技术沉积和图案化相应第一ILD层106和第一IMD层108和110上的光刻胶材料以暴露出第一ILD层106或第一IMD层108或110的即将成为相应第一金属化图案132、134或136的部分，从而可形成第一金属化图案132、134和136。诸如各向异性干蚀刻工艺的蚀刻工艺可用于在第一ILD层106或第一IMD层108或110中形成凹槽/开口。凹槽/开口可与扩散势垒层和/或粘合层(未示出)排成一行并且填充有导电材料。扩散势垒层可包括一层或多层TaN、Ta、TiN、Ti、CoW等，并且导电材料可包括铜、钨、铝、银、和它们的组合等，从而形成图1A和图1B所示的第一金属化图案132、134和136。通常，第一ILD层106和第一IMD层108和110以及相关的第一金属化图案132、134和136用于互连电气电路并且提供外电气连接。
为了便于本文讨论，标示出第一衬底100中的第一IMD层110中的第一金属化图案136的第一互连线/焊盘136a、136b、136c和136d和第二衬底200中的第二IMD层210中的第二金属化图案236的第二互连线/焊盘236a、236b、236c、236d、236e、236f和236g。
还应该注意，一个或多个蚀刻停止层(未示出)可布置在ILD层和IMD层(例如，第一ILD层106、第一IMD层108和110)的相邻层之间。通常，蚀刻停止层提供当形成通孔和/或接触件时停止蚀刻工艺的机制。蚀刻停止层由具有不同于相邻层的蚀刻选择率的介电材料形成，例如，下面的第一半导体衬底102和上面的第一ILD层106之间的蚀刻停止层。在一个实施例中，蚀刻停止层可由通过CVD或PECVD技术沉积的SiN、SiCN、SiCO、CN、它们的组合等形成。
在所示实施例中，第一附加介电层138形成在第一IMD层110上方。第一附加介电层138可通过诸如旋涂、CVD和PECVD的现有技术中已知任意合适方法由例如低K介电材料(诸如PSG、BPSG、FSG、SiOxCy、旋涂玻璃、旋涂聚合物、碳化硅材料、它们的化合物、它们的合成物、它们的组合等)形成。第一接合介电层140形成在第一附加介电层138上方。第一接合介电层140可以是考虑了衬底之间的接合的任意介电层；例如，第一接合介电层140可以是通过热氧化、CVD等形成的氧化物、氮氧化硅(SiON)等。
参照图2，第一衬底100和第二衬底200被布置成第一半导体衬底102和第二半导体衬底202的器件侧彼此相对并且接合在一起，例如通过接合附加介电层138被接合在一起。在所示实施例中，使用诸如电介质与电介质接合(例如，氧化物与氧化物接合)的直接接合工艺将第一衬底100和第二衬底200接合在一起。其他实施例可考虑其他接合工艺，诸如金属与金属接合(例如，铜与铜接合)、金属与电介质接合(例如，氧化物与铜接合)、它们的任意组合等。
应该注意，接合可以在晶圆级，其中，第一衬底100和第二衬底200接合在一起并且然后被分割成单独的管芯。在其他实施例中，可在管芯与管芯级或管芯与晶圆级实施接合。
参照图3，第一衬底100和第二衬底200接合之后，可将薄化工艺应用于第二衬底200的背面，例如，应用于第二半导体衬底202的背面。在一个实施例中，通过使用诸如研磨、抛光、工序、工序、和/或化学蚀刻的合适技术可薄化第二衬底200的背面。例如，薄化之前，第一半导体衬底102和第二半导体衬底202中的每一个可具有介于约100μm至775μm之间的厚度，并且在薄化之后，第二半导体衬底202可具有介于约2μm至3μm之间的厚度。
参照图4，形成通孔30、32和34。如下给出更为详细的讨论，形成从第二衬底200的背面开始延伸的电气连接以选择第一衬底100的第一互连线/焊盘136a和136c中的一些和/或选择第二互连线/焊盘236g的一些。
首先，为通孔30、32和34形成穿过第二半导体衬底202的开口。可以使用光刻技术形成开口，例如沉积和图案化第二半导体衬底202上的光刻胶材料以暴露出第二半导体衬底202的将形成开口的位置。诸如各向异性干蚀刻工艺的蚀刻工艺可用于在第二半导体衬底202中产生开口。在这些工艺期间可在第二半导体衬底202上存在各种层，诸如硬掩模层(多层)、抗反射涂覆(ARC)层(多层)等或它们的组合。
在第二半导体衬底202的背面上方和沿着第二半导体衬底202中的开口的侧壁可形成一个或多个介电膜。介电膜可提供通孔和器件电路之间的钝化和隔离并且可在例如后续蚀刻工艺期间提供对第二半导体衬底202的保护。此外，介电膜可防止金属离子扩散进第二半导体衬底202中。
在一个实施例中，沿着第二半导体衬底202的背面以及开口中形成多层介电膜。多层介电膜包括第一介电膜及其上方的第二介电膜。选择第一介电膜和第二介电膜的材料，使得两层之间存在相对较高的蚀刻选择率。可使用的介电材料的实例为用于第一介电膜的氮化物材料和用于第二介电膜的氧化物。使用CVD技术可形成诸如氮化硅(Si3N4)层的氮化物层。通过热氧化或通过CVD技术可形成诸如二氧化硅层的氧化物层。可使用其他材料，包括其他氧化物、其他氮化物、SiON、SiC、低K介电材料(例如，黑钻石)、和/或高K氧化物(例如，HfO2、Ta2O5)。使用例如干蚀刻工艺由第二介电膜形成间隔件型结构，使得第二介电膜被蚀刻同时对第一介电膜产生很少损坏或无损坏。
图案化掩模形成在第二半导体衬底202的背面上方，例如，其可以为已经历了作为光刻工艺的一部分的沉积、掩模、暴露和显影的光刻胶材料。图案化掩模被图案化以限定延伸穿过相应开口的孔口，这些开口穿过第二半导体衬底202并穿过第二衬底200的第二介电层206、208、210、238和240以及第一衬底100的第一介电层140和138的至少一些第一介电层，从而暴露出从第一互连线/焊盘136a和136c和第二互连线/焊盘236g中所选择的互连线/焊盘的部分，如下文给出更为详细的解释。实施一个或多个蚀刻工艺以形成这些孔口。可实施诸如干蚀刻、各向异性湿蚀刻的合适蚀刻工艺、或任何其他合适的各向异性蚀刻或图案化工艺以形成孔口。
如图4可知，通孔30的孔口延伸至第二互连线/焊盘236a和236b以及至第一互连线/焊盘136a。通孔32的孔口延伸至第二互连线/焊盘236e和236f以及至第一互连线/焊盘136c。通孔34的孔口延伸至第二互连线/焊盘236g。在一个实施例中，第一和第二互连线/焊盘由诸如铜的合适金属材料形成，其展示出不同于介电层206、208、210、238、240、140和138的蚀刻率(选择率)。这样，第二互连线/焊盘236a、236b、236e和236f可用作用于介电层238、240、140和138的蚀刻工艺的硬掩模层。可使用选择蚀刻工艺以快速地蚀刻介电层238、240、140和138，同时仅蚀刻第二互连线/焊盘236a、236b、236e和236f的一部分。此外，第二互连线/焊盘236可用作蚀刻工艺的蚀刻停止层。继续蚀刻工艺直到暴露出第一互连线/焊盘136a和136c，从而形成从第二衬底200的背面延伸至互连线/焊盘136a、136c和236g的孔口。
应该注意，蚀刻工艺可延伸穿过用于形成介电层的各种层，其可包括各种类型的材料和蚀刻停止层。因此，蚀刻工艺可利用多种蚀刻剂以蚀刻穿过各种层，其中，基于被蚀刻的材料选择蚀刻剂。
导电材料形成在孔口内。在一个实施例中，通过沉积一个或多个扩散和/或势垒层和沉积晶种层可形成导电材料。例如，沿着孔口的侧壁可形成包括一层或多层Ta、TaN、TiN、Ti、CoW等的扩散势垒层。晶种层(未示出)可由铜、镍、金、它们的任意组合等形成。通过诸如PVD、CVD等的合适沉积技术可形成扩散势垒层和晶种层。一旦在开口中已沉积晶种层，使用例如电化学镀工艺或其他合适工艺将诸如钨、钛、铝、铜、它们的组合等的导电材料填充到孔口中。填充的孔口形成通孔30、32和34。
从第二半导体衬底202的背面可去除例如多余导电材料和/或介电膜的多余材料。在实施例中，沿着第二半导体衬底202的背面可留下多层介电膜的一层或多层，以提供额外保护免受环境伤害。使用蚀刻工艺、平坦化工艺(例如，CMP工艺)等可去除任意多余材料。
参照图5，沿着第二半导体衬底202的背面形成介电覆盖层40。介电覆盖层40可以包括例如通过使用诸如溅射、CVD等的合适沉积技术形成的一层或多层介电材料，诸如氮化硅、氮氧化硅、碳氧化硅、碳化硅、它们的组合、和它们的多层。
形成穿过介电覆盖层40的通孔42。例如通过使用光刻技术沉积和图案化介电覆盖层40上的光刻胶材料以暴露出介电覆盖层40的即将成为介电覆盖层40的部分，从而可形成通孔42。可使用诸如各向异性干蚀刻工艺的蚀刻工艺在介电覆盖层40内产生开口。开口可与扩散势垒层和/或粘合层(未示出)排成一排，并且填充有导电材料。扩散势垒层可包括一层或多层TaN、Ta、TiN、Ti、CoW等，并且导电材料可包括铜、钨、铝、银、它们的组合等，从而形成图5所示的通孔42。
导电焊盘44形成在通孔42上方且与其电连接并且在介电覆盖层40上方。导电焊盘44可包括铝，但是诸如铜的其他材料也可使用。使用诸如溅射的沉积工艺或其他合适工艺可形成导电焊盘44以形成材料层，之后，通过合适的工艺(诸如光刻掩模和蚀刻)可去除材料层的部分以形成导电焊盘44。然而，可使用任意合适的工艺形成导电焊盘44。
钝化层46形成在介电覆盖层40和导电焊盘44上。钝化层46可包括一种或多种合适的介电材料，诸如氧化硅、氮化硅、它们的组合等。使用例如CVD、PECVD、或任意合适的工艺可形成钝化层46。已经形成钝化层46之后，通过去除钝化层46的一部分暴露出下面的导电焊盘44的至少一部分可制成穿过钝化层46至导电焊盘44的开口。使用合适的光刻和蚀刻工艺可形成开口。
参照图6，第一应力缓冲层48形成在钝化层46上方。第一应力缓冲层48可吸收应力以例如防止应力透入第二衬底200。第一应力缓冲层48的材料可具有介于约2GPa至约4GPa之间的杨氏模量，且更具体地，介于约2GPa至约3GPa之间，如约2.1GPa。此外，第一应力缓冲层48的材料可具有介于90MPa至约200MPa之间的抗张强度，且更具体地说，介于约120MPa至约170MPa之间，诸如，145MPa。此外，第一应力缓冲层48的材料在破裂之前可具有介于约5％至约50％之间的伸长率，且更具体地说，介于约30％至约50％之间，诸如，约40％。第一应力缓冲层48可由诸如聚酰亚胺、聚苯并恶唑(PBO)、苯并环丁烯(BCB)等的聚合物形成。通过旋转涂覆、层压等可形成第一应力缓冲层48。图案化第一应力缓冲层48以形成穿过钝化层46中的开口的开口，并且穿过该开口暴露出导电焊盘44。第一应力缓冲层48的图案化可包括光刻技术。可实施固化步骤以固化第一应力缓冲层48。第一应力缓冲层48可具有介于约3μm至约10μm之间的厚度，并且更为具体地，介于约5μm至约7μm之间，诸如约6μm。尽管图6示出了一个第一应力缓冲层48，但是可形成多个应力缓冲层。
钝化后互连件(PPI)50形成在第一应力缓冲层48上方且填充第一应力缓冲层48和钝化层46中的开口，从而形成与导电焊盘44的电连接。可将PPI50用作重布层以允许后续形成的电连接至导电焊盘44的凸块下金属(UBM)设置在第二衬底200上的任意理想位置。在一个实施例中，通过使用诸如物理气相沉积(PVD)、溅射等的合适形成工艺形成晶种层可形成PPI50，其可包括钛铜合金。然后可形成光刻胶以覆盖晶种层并且可图案化光刻胶以暴露出晶种层的位于PPI50理想所处位置的部分。
一旦光刻胶已形成且图案化，通过诸如电镀的沉积工艺可在晶种层上形成诸如铜的导电材料。尽管所讨论的材料和方法适用于形成导电材料，但是这些材料和方法仅为实例。可使用诸如AlCu或Au的任意其他合适的材料，以及诸如CVD或PVD的任意其他合适的形成工艺形成PPI50。
一旦已经形成导电材料，诸如通过使用氧气等离子体通过诸如灰化的合适去除工艺可去除光刻胶。此外，去除光刻胶之后，通过例如合适的蚀刻工艺可去除晶种层的被光刻胶覆盖的部分。
参照图7，第二应力缓冲层52形成在PPI50和第一应力缓冲层48上方。例如，第二应力缓冲层52还可吸收应力以防止应力透入第二衬底200。第二应力缓冲层52的材料可具有介于约2GPa至约4GPa之间的杨氏模量，且更具体地，介于约2GPa至约3GPa之间，如约2.1GPa。此外，第二应力缓冲层52的材料可具有介于约90MPa至约200MPa之间的抗张强度，且更具体地说，介于约120MPa至约170MPa之间，诸如，约145MPa。此外，第二应力缓冲层52的材料在破裂之前可具有介于约5％至约50％之间的伸长率，且更具体地说，介于约30％至约50％之间，诸如，约40％。第二应力缓冲层52可由诸如聚酰亚胺、PBO、BCB等的聚合物形成。通过旋转涂覆、层压等可形成第二应力缓冲层52。图案化第二应力缓冲层52以形成开口，穿过该开口暴露出PPI50。第二应力缓冲层52的图案化可包括光刻技术。可实施固化步骤以固化第二应力缓冲层52。第二应力缓冲层52可具有介于约3μm至约10μm之间的厚度，并且更为具体地，介于约5μm至约7μm之间，诸如约6μm。尽管图7示出了一个第二应力缓冲层52，但是可形成多个应力缓冲层。
UBM54可形成在第二应力缓冲层52中的开口中且与PPI50电接触。UBM54可包括诸如钛层、铜层和镍层的三层导电材料。本领域的技术人员会意识到，具有很多合适的材料和层布置，诸如铬/铬-铜合金/铜/金的布置、钛/钛钨/铜的布置、或铜/镍/金的布置，它们可适用于形成UBM54。
通过在第二应力缓冲层52上方以及沿着穿过第二应力缓冲层52至PPI50的开口的内部形成每个层，可形成UBM54。使用诸如电化学镀的电镀工艺可形成每个层，但是可以使用诸如溅射、蒸发、或PECVD工艺的其他形成工艺。一旦已经形成理想的层，然后可以通过合适的光刻掩模和蚀刻工艺去除层的部分，以去除不期望的材料且留下理想形状(诸如圆形、八角形、正方形或矩形)的UBM54，但是可以可选地形成任意的理想形状。
参照图8，在UMB54上形成接触凸块56。接触凸块56可为受控熔塌芯片连接(C4)和/或可包括诸如焊料、锡的材料或诸如银、无铅锡或铜的其他合适的材料。在接触凸块56为锡焊料凸块的实施例中，通过先经由蒸发、电镀、印刷、焊料转移、植球等形成锡层可形成接触凸块56。一旦在结构上已经形成锡层，可实施回流以将材料成型为理想的凸块形状。可使用其他凸块结构。例如，还可使用具有焊料连接件的金属柱。
图9至图11示出了对图1A、图1B和图2至图8所示的实施例的修改。图9类似于上述的图6。PPI50在其上将形成UBM54的区域中图案化有开口。图10A至图10E为具有开口60的PPI50的一部分的实例布局视图。图10A至图10E中的PPI50的部分位于图11的UBM54的下面。在图10A中，形成穿过PPI50的单行布置的开口60a。在图10B中，形成穿过PPI50的以两个横向交叉线布置的开口60b。在图10C中，形成穿过PPI50的以四个横向交叉线布置的开口60c。在图10D中，形成穿过PPI50的以5×5阵列布置的开口60d。在图10E中，形成穿过PPI50的以3×3阵列布置的开口60e。这些布局视图为实例，并且还可使用其他的开口60的布置。
图11类似于上述图8。如所示，第二应力缓冲层52填充PPI50中的开口60。由于开口60和位于PPI50中的开口60中的第二应力缓冲层52，还可进一步吸收应力且防止应力透入第二衬底200。
图12A、图12B和图13至图19示出了根据一些实施例的在形成接合结构的中间步骤中的结构的各种截面图。图12A和图12B示出了与先前参照图1A和图1B所述的衬底相似的第一衬底100和第二衬底200。图12A和图12B中的第一衬底100和第二衬底200示出了金属化图案132、134、136、232、234和236可具有各种配置。为了便于本文的讨论，标示出第二衬底200中的第二ILD层206中的第二互连线/焊盘232a和236b。此外，在该实施例中，第一衬底100和第二衬底200之间的接合可使用不同的机制，如下文给出进一步的讨论，并且这样，省略了附加介电层138和238以及接合的介电层140和240。
参照图13，第一衬底100和第二衬底200被配置成使第一半导体衬底102和第二半导体衬底202的器件侧彼此相对，并且被接合在一起。在所示实施例中，使用诸如金属与金属接合(例如，铜与铜接合)、金属与电介质接合(例如，氧化物与铜接合)的直接接合工艺、或它们的组合将第一衬底100和第二衬底200接合在一起。例如，IMD层110和210接合在一起，互连线/焊盘136a和236a接合在一起，互连线/焊盘136b和236b接合在一起，互连线/焊盘136c和236c接合在一起，以及互连线/焊盘136d和236d接合在一起。此外，可将第一互连线/焊盘136a、136b、136c和136d中的一个或多个接合至第二IMD层210，并且可将第二互连线/焊盘236a、236b、236c和236d中的一个或多个接合至第一IMD层110。
参照图14，如图3所讨论，接合第一衬底100和第二衬底200之后，可将薄化工艺应用至第二衬底200的背面。在一个实施例中，通过使用诸如研磨、抛光、工序、工序、和/或化学蚀刻的合适技术可薄化第二衬底200的背面。
参照图15，形成通孔70和72。如下文给出的更为详细的讨论，将形成从第二衬底200的背面开始延伸的电连接，以选择一些第二互连线/焊盘232a和232b。
首先，为通孔70和72形成穿过第二半导体衬底202的开口。使用例如光刻技术沉积和图案化第二半导体衬底202上的光刻胶材料以暴露出第二半导体衬底202的将形成开口的位置，从而可形成开口。诸如各向异性干蚀刻工艺的蚀刻工艺可用于在第二半导体衬底202中产生开口。在这些工艺期间可在第二半导体衬底202上存在各种层，诸如，硬掩模层(多层)、抗反射涂(ARC)层(多层)等、或它们的组合。
在第二半导体衬底202的背面上方以及沿着第二半导体衬底202中的开口的侧壁可形成一个或多个介电膜(多膜)。介电膜(多膜)可提供通孔和器件电路之间的钝化和隔离并且可在例如后续蚀刻工艺期间提供对第二半导体衬底202的保护。此外，介电膜(多膜)可防止金属离子扩散进第二半导体衬底202内。
在一个实施例中，沿着第二半导体衬底202的背面以及在开口中形成多层介电膜。多层介电膜包括第一介电膜和位于第一介电膜上方的第二介电膜。选择第一介电膜和第二介电膜的材料，使得两层之间存在相对较高的蚀刻选择率。可使用的介电材料的实例为用于第一介电膜的氮化物材料和用于第二介电膜的氧化物。使用CVD技术可形成诸如氮化硅(Si3N4)层的氮化物层。通过热氧化或通过CVD技术可形成诸如二氧化硅层的氧化物层。可使用其他材料，包括其他氧化物、其他氮化物、SiON、SiC、低K介电材料(例如，黑钻石)、和/或高K氧化物(例如，HfO2、Ta2O5)。使用例如干蚀刻工艺由第二介电膜形成间隔件型结构，使得第二介电膜被蚀刻同时对第一介电膜产生很少损坏或无损坏。
图案化掩模形成在第二半导体衬底202的背面上方，例如，其可以为已经历了作为光刻工艺的一部分的沉积、掩模、暴露和显影的光刻胶材料。图案化掩模被图案化以穿过第二半导体衬底202和穿过第二ILD层206限定延伸穿过相应开口的孔口，从而暴露出从第二互连线/焊盘232a和232b中所选择的互连线/焊盘的部分，如下文给成更为详细的解释。实施一个或多个蚀刻工艺以形成这些孔口。可实施诸如干蚀刻、各向异性湿蚀刻的合适蚀刻工艺、或任何其他合适的各向异性蚀刻或图案化工艺以形成孔口。
由图15可知，用于通孔70的孔口延伸至第二互连线/焊盘232a。用于通孔72的孔口延伸至第二互连线/焊盘232b。在一个实施例中，第二互连线/焊盘232a和232b由诸如铜的合适金属材料形成，其可用作蚀刻停止层。可使用选择蚀刻工艺以蚀刻介电第二ILD层206。继续蚀刻工艺直到暴露出第二互连线/焊盘232a和232b，从而形成从第二衬底200的背面延伸至互连线/焊盘232a和232b的孔口。
应该注意，蚀刻工艺可延伸穿过用于形成介电层的各种层，其可包括各种类型的材料和蚀刻停止层。因此，蚀刻工艺可利用多种蚀刻剂以蚀刻穿过各种层，其中，基于被蚀刻的材料选择蚀刻剂。
导电材料形成在孔口内。在一个实施例中，通过沉积一个或多个扩散和/或势垒层和沉积晶种层可形成导电材料。例如，沿着孔口的侧壁可形成包括一层或多层Ta、TaN、TiN、Ti、CoW等的扩散势垒层。晶种层(未示出)可由铜、镍、金、它们的任意组合等形成。通过诸如PVD、CVD等的合适沉积技术可形成扩散势垒层和晶种层。一旦在开口中已沉积晶种层，例如使用电化学镀工艺或其他合适工艺将诸如钨、钛、铝、铜、它们的组合等的导电材料填充到孔口中。填充的孔口形成通孔70和72。如先前所述，可从第二半导体衬底202的背面去除多余的材料，例如，多余的导电材料和/或介电膜。
参照图16至图19，如上述参照图5至图8的讨论，继续处理以形成介电覆盖层40、穿过介电覆盖层40的通孔42、位于通孔42上方且与其电接触以及位于介电覆盖层40上方的导电焊盘44、位于介电覆盖层40和导电焊盘44上的钝化层46、位于钝化层46上方的第一应力缓冲层48、位于第一应力缓冲层48上方的PPI50、位于PPI50和第一应力缓冲层48上方的第二应力缓冲层52、位于第二应力缓冲层52中的开口中且与PPI50电接触的UBM54、以及位于UBM54上的接触凸块56。
图20和图21示出了对图12A、图12B和图13至图19所示实施例的修改。图20类似于上述讨论的图17。PPI50在将形成UBM54的区域图案化有开口。如先前实施例，图10A至图10E为具有开口60的PPI50的布局视图。这些布局视图为实例，并且还可使用其他的开口60的布置。图21类似于上述讨论的图19。如所示，第二应力缓冲层52填充PPI50中的开口60。由于开口60和PPI50中的开口60中的第二应力缓冲层52，可进一步吸收应力并且可防止应力透入第二衬底200。
如通篇讨论，实施例可包括堆叠和/或接合结构内的诸如第一应力缓冲层48和第二应力缓冲层52的应力缓冲层。在接合结构通过诸如凸块56附接至进一步不同的衬底之后，应力缓冲层可吸收例如由热循环和热膨胀失配导致的应力。应力缓冲层吸收应力可防止应力到达且影响接合和/或堆叠结构中的一个或多个衬底中的孔(诸如通孔)和介电层(诸如低k介电层)。例如，可降低通孔和低k介电层的破裂和分层。因此，应力缓冲层可增强接合和/或堆叠结构的可靠性。
一个实施例是一种结构。该结构包括第一衬底、第二衬底、第一应力缓冲层、钝化后互连(PPI)结构、和第二缓冲层。第一衬底包括第一半导体衬底和位于第一半导体衬底上的第一互连结构。第二衬底包括第二半导体衬底和位于第二半导体衬底的第一侧上的第二互连结构。第一衬底在接合界面处接合至第二衬底。第一互连结构和第二互连结构设置在第一半导体衬底和第二半导体衬底之间。通孔至少延伸穿过第二半导体衬底进入第二互连结构。第一应力缓冲层位于第二半导体衬底的第二侧上。第二半导体衬底的第二侧与第二半导体衬底的第一侧相对。PPI结构位于第一应力缓冲层上且电连接至通孔。第二应力缓冲层位于PPI结构和第一应力缓冲层上。
另一个实施例是一种结构。该结构包括接合结构、应力缓冲结构和外部连接件。接合结构包括在接合界面处接合在一起的第一衬底和第二衬底。第一衬底包括位于第一介电层中的第一金属化图案，以及第二衬底包括半导体衬底和半导体衬底上的第二介电层中的第二金属化图案。接合结构还包括延伸穿过半导体衬底的通孔。应力缓冲结构位于半导体衬底上。应力缓冲结构包括第一应力缓冲层和重布件，以及第一应力缓冲层设置在半导体衬底和重布件之间。重布件电连接至通孔。外部连接件电连接至重布件。
再一个实施例是一种方法。该方法包括将第一衬底接合至第二衬底。第二衬底包括半导体衬底。该方法还包括：在半导体衬底的一侧形成且至少延伸穿过半导体衬底的通孔；在半导体衬底的一侧上形成第一应力缓冲层；在第一应力缓冲层上形成且电连接至通孔的钝化后互连(PPI)结构；以及在PPI结构和第一应力缓冲层上形成第二应力缓冲层。
前文概述了多个实施例的特征，从而使本领域技术人员可以更好地理解本发明的各个方面。本领域技术人员应理解，其可以容易地将本公开用作设计或修改其他工艺或结构的基础，从而实现相同目的和/或实现本发明引入的实施例的相同优点。本领域技术人员还应理解，这种等效结构不偏离本发明的主旨和范围，并且其可以在不背离本发明主旨和范围的前提下进行多种改变、替换、或变化。

Claims (10)

1.一种结构，包括：
第一衬底，包括第一半导体衬底和位于所述第一半导体衬底上的第一互连结构；
第二衬底，包括第二半导体衬底和位于所述第二半导体衬底的第一侧上的第二互连结构，所述第一衬底在接合界面处接合至所述第二衬底，所述第一互连结构和所述第二互连结构设置在所述第一半导体衬底和所述第二半导体衬底之间；
通孔，至少延伸穿过所述第二半导体衬底进入所述第二互连结构；
第一应力缓冲层，位于所述第二半导体衬底的第二侧上，所述第二半导体衬底的所述第二侧与所述第二半导体衬底的所述第一侧相对；
钝化后互连(PPI)结构，位于所述第一应力缓冲层上且电连接至所述通孔；以及
第二应力缓冲层，位于所述PPI结构和所述第一应力缓冲层上。
2.根据权利要求1所述的结构，其中，所述通孔延伸超出所述接合界面且进入所述第一互连结构。
3.根据权利要求1所述的结构，其中，所述通孔未延伸超出所述接合界面。
4.根据权利要求1所述的结构，其中，所述接合界面基本由电介质与电介质接合构成。
5.根据权利要求1所述的结构，其中，所述接合界面包括金属与金属接合。
6.根据权利要求1所述的结构，其中，开口穿过所述PPI结构，所述第二应力缓冲层至少部分地设置在所述开口中。
7.一种结构，包括：
接合结构，包括在接合界面处接合在一起的第一衬底和第二衬底，所述第一衬底包括位于第一介电层中的第一金属化图案，所述第二衬底包括半导体衬底和位于所述第二半导体衬底上的第二介电层中的第二金属化图案，所述接合结构还包括延伸穿过所述半导体衬底的通孔；
应力缓冲结构，位于所述半导体衬底上，所述应力缓冲结构包括第一应力缓冲层和重布件，所述第一应力缓冲层设置在所述半导体衬底和所述重布件之间，所述重布件电连接至所述通孔；以及
外部连接件，电连接至所述重布件。
8.根据权利要求7所述的结构，其中，所述应力缓冲结构还包括第二应力缓冲层，所述重布件设置在所述第一应力缓冲层和所述第二应力缓冲层之间。
9.一种方法，包括：
将第一衬底接合至第二衬底，所述第二衬底包括半导体衬底；
从所述半导体衬底的一侧形成至少延伸穿过所述半导体衬底的通孔；
在所述半导体衬底的所述一侧上形成第一应力缓冲层；
在所述第一应力缓冲层上形成电连接至所述通孔的钝化后互连(PPI)结构；以及
在所述PPI结构和所述第一应力缓冲层上形成第二应力缓冲层。
10.根据权利要求9所述的方法，其中，所述接合基本由电介质与电介质接合构成。
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109712953A (zh) * 2017-10-25 2019-05-03 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法和半导体器件
CN110085605A (zh) * 2018-11-12 2019-08-02 友达光电股份有限公司 显示装置
WO2020088208A1 (en) * 2018-11-01 2020-05-07 Changxin Memory Technologies, Inc. Wafer stacking method and wafer stacking structure
CN111128721A (zh) * 2019-12-04 2020-05-08 长江存储科技有限责任公司 存储器的制作方法及存储器
CN112259510A (zh) * 2020-10-23 2021-01-22 中北大学 高过载环境中工作的传感器封装防护结构及其制备方法

Families Citing this family (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5853351B2 (ja) * 2010-03-25 2016-02-09 ソニー株式会社 半導体装置、半導体装置の製造方法、及び電子機器
US8735219B2 (en) 2012-08-30 2014-05-27 Ziptronix, Inc. Heterogeneous annealing method and device
US8877554B2 (en) * 2013-03-15 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices
US9793243B2 (en) * 2014-08-13 2017-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Buffer layer(s) on a stacked structure having a via
CN105742196B (zh) * 2014-12-09 2018-07-27 中国科学院微电子研究所 半导体器件制造方法
KR101731700B1 (ko) * 2015-03-18 2017-04-28 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US9711478B2 (en) * 2015-10-19 2017-07-18 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device with an anti-pad peeling structure and associated method
US9984987B2 (en) * 2016-08-05 2018-05-29 Nanya Technology Corporation Semiconductor structure and manufacturing method thereof
US10367031B2 (en) * 2016-09-13 2019-07-30 Imec Vzw Sequential integration process
TWI822659B (zh) 2016-10-27 2023-11-21 美商艾德亞半導體科技有限責任公司 用於低溫接合的結構和方法
WO2018081705A1 (en) * 2016-10-31 2018-05-03 The Regents Of The University Of California Flexible fan-out wafer level process and structure
US10074602B2 (en) * 2016-11-11 2018-09-11 Advanced Semiconductor Engineering, Inc. Substrate, semiconductor package structure and manufacturing process
CN109087906B (zh) * 2017-06-13 2021-01-15 联华电子股份有限公司 电连接装置
CN112164688B (zh) * 2017-07-21 2023-06-13 联华电子股份有限公司 芯片堆叠结构及管芯堆叠结构的制造方法
US10510631B2 (en) * 2017-09-18 2019-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. Fan out package structure and method of manufacturing the same
KR102438179B1 (ko) * 2017-11-02 2022-08-30 삼성전자주식회사 반도체 장치 및 이를 포함하는 반도체 패키지, 및 상기 반도체 장치의 제조 방법
WO2019152512A1 (en) * 2018-01-31 2019-08-08 The Regents Of The University Of California Flexible and stretchable interconnects for flexible systems
US10741477B2 (en) * 2018-03-23 2020-08-11 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices and methods of forming the same
US10665559B2 (en) * 2018-04-11 2020-05-26 Taiwan Semiconductor Manufacturing Co., Ltd. Device, semiconductor package and method of manufacturing semiconductor package
CN112368845A (zh) * 2018-06-19 2021-02-12 新唐科技日本株式会社 半导体装置
WO2020010056A1 (en) 2018-07-03 2020-01-09 Invensas Bonding Technologies, Inc. Techniques for joining dissimilar materials in microelectronics
US10903142B2 (en) * 2018-07-31 2021-01-26 Intel Corporation Micro through-silicon via for transistor density scaling
US11158573B2 (en) 2018-10-22 2021-10-26 Invensas Bonding Technologies, Inc. Interconnect structures
US11538803B2 (en) * 2018-12-14 2022-12-27 Intel Corporation Integration of III-V transistors in a silicon CMOS stack
US11244920B2 (en) * 2018-12-18 2022-02-08 Invensas Bonding Technologies, Inc. Method and structures for low temperature device bonding
US11094811B2 (en) * 2019-04-19 2021-08-17 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US11373968B2 (en) 2019-04-26 2022-06-28 Cirrus Logic, Inc. Via structure for semiconductor dies
US10770424B1 (en) * 2019-08-13 2020-09-08 Nanya Technology Corporation Semiconductor structure and method of manufacturing thereof
KR20210021626A (ko) * 2019-08-19 2021-03-02 삼성전자주식회사 반도체 장치
US11211352B2 (en) * 2019-10-01 2021-12-28 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structure to prevent metal redeposit and to prevent bond pad consumption and corrosion
CN110690165B (zh) * 2019-10-15 2020-06-02 杭州见闻录科技有限公司 一种芯片封装方法及封装结构
US20210125948A1 (en) * 2019-10-28 2021-04-29 Nanya Technology Corporation Semiconductor device and method for fabricating the same
US11610812B2 (en) * 2019-10-31 2023-03-21 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-wafer capping layer for metal arcing protection
DE102020126234A1 (de) * 2019-10-31 2021-05-06 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-wafer-abdeckschicht für metalldurchschlagschutz
US11476248B2 (en) * 2019-12-26 2022-10-18 Taiwan Semiconductor Manufacturing Co., Ltd. Three dimensional integrated circuit and fabrication thereof
US11127718B2 (en) * 2020-01-13 2021-09-21 Xilinx, Inc. Multi-chip stacked devices
US11088090B1 (en) 2020-02-12 2021-08-10 Qualcomm Incorporated Package comprising a substrate that includes a stress buffer layer
US11043469B1 (en) * 2020-02-19 2021-06-22 Nanya Technology Corporation Method of forming three dimensional semiconductor structure
FR3108205A1 (fr) * 2020-03-12 2021-09-17 Stmicroelectronics (Grenoble 2) Sas Circuit intégré comprenant une partie d’interconnexion comportant un élément de soudure saillant et procédé de fabrication correspondant
TW202137499A (zh) * 2020-03-17 2021-10-01 聯華電子股份有限公司 半導體元件及其製作方法
WO2021188846A1 (en) 2020-03-19 2021-09-23 Invensas Bonding Technologies, Inc. Dimension compensation control for directly bonded structures
KR20220026809A (ko) 2020-08-26 2022-03-07 삼성전자주식회사 반도체 패키지
US20240153893A1 (en) * 2022-11-03 2024-05-09 Qorvo Us, Inc. Wafer-level hybrid bonded rf switch with redistribution layer
CN117116888A (zh) * 2023-01-16 2023-11-24 荣耀终端有限公司 半导体封装结构及其制备方法、电子设备

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020197458A1 (en) * 1998-12-29 2002-12-26 Industrial Technology Research Institute Method for improving integrated circuits bonding firmness
CN1669123A (zh) * 2002-07-15 2005-09-14 因芬尼昂技术股份公司 具应力吸收半导体层之半导体组件及其制造方法
CN1941344A (zh) * 2005-09-27 2007-04-04 台湾积体电路制造股份有限公司 焊垫
US20100140752A1 (en) * 2008-12-10 2010-06-10 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Compliant Polymer Layer Between UBM and Conformal Dielectric Layer/RDL for Stress Relief
US20110193197A1 (en) * 2010-02-05 2011-08-11 International Business Machines Corporation Structure and method for making crack stop for 3d integrated circuits

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5851911A (en) * 1996-03-07 1998-12-22 Micron Technology, Inc. Mask repattern process
KR100306842B1 (ko) * 1999-09-30 2001-11-02 윤종용 범프 패드에 오목 패턴이 형성된 재배치 웨이퍼 레벨 칩 사이즈 패키지 및 그 제조방법
KR100537552B1 (ko) 2000-07-31 2005-12-16 매그나칩 반도체 유한회사 반도체 소자 및 그의 제조 방법
US6961595B2 (en) 2002-08-08 2005-11-01 Flarion Technologies, Inc. Methods and apparatus for operating mobile nodes in multiple states
WO2006096678A1 (en) 2005-03-08 2006-09-14 Qualcomm Flarion Technologies, Inc. Transmission methods and apparatus combining pulse modulation and hierarchical modulation
US7410884B2 (en) 2005-11-21 2008-08-12 Intel Corporation 3D integrated circuits using thick metal for backside connections and offset bumps
KR100804392B1 (ko) * 2005-12-02 2008-02-15 주식회사 네패스 반도체 패키지 및 그 제조 방법
US7898095B2 (en) 2006-03-20 2011-03-01 Tezzaron Semiconductor, Inc. Fiducial scheme adapted for stacked integrated circuits
KR101571566B1 (ko) 2008-08-11 2015-11-25 엘지전자 주식회사 무선 통신 시스템에서 제어신호 전송 방법
JP5389932B2 (ja) 2008-11-14 2014-01-15 エルジー エレクトロニクス インコーポレイティド 多重アンテナシステムにおける複数のリソースを用いたデータ送信方法及び装置
US20100193950A1 (en) 2009-01-30 2010-08-05 E.I.Du Pont De Nemours And Company Wafer level, chip scale semiconductor device packaging compositions, and methods relating thereto
US7994045B1 (en) * 2009-09-08 2011-08-09 Amkor Technology, Inc. Bumped chip package fabrication method and structure
US8446006B2 (en) 2009-12-17 2013-05-21 International Business Machines Corporation Structures and methods to reduce maximum current density in a solder ball
US8415238B2 (en) 2010-01-14 2013-04-09 International Business Machines Corporation Three dimensional integration and methods of through silicon via creation
KR101121827B1 (ko) 2010-04-13 2012-03-21 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
JP6019599B2 (ja) 2011-03-31 2016-11-02 ソニー株式会社 半導体装置、および、その製造方法
GB2496379A (en) 2011-11-04 2013-05-15 Univ Edinburgh A freespace optical communication system which exploits the rolling shutter mechanism of a CMOS camera
US9607921B2 (en) * 2012-01-12 2017-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package interconnect structure
US8563403B1 (en) * 2012-06-27 2013-10-22 International Business Machines Corporation Three dimensional integrated circuit integration using alignment via/dielectric bonding first and through via formation last
US9240853B2 (en) 2012-11-16 2016-01-19 Huawei Technologies Co., Ltd. Systems and methods for sparse code multiple access
US9166663B2 (en) 2012-12-14 2015-10-20 Futurewei Technologies, Inc. System and method for open-loop MIMO communications in a SCMA communications system
US9773732B2 (en) * 2013-03-06 2017-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for packaging pad structure
US9793243B2 (en) 2014-08-13 2017-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Buffer layer(s) on a stacked structure having a via
US10014271B2 (en) * 2015-11-20 2018-07-03 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and method of manufacturing the same
US9748206B1 (en) * 2016-05-26 2017-08-29 Taiwan Semiconductor Manufacturing Co., Ltd. Three-dimensional stacking structure and manufacturing method thereof
US10541228B2 (en) * 2017-06-15 2020-01-21 Taiwan Semiconductor Manufacturing Company, Ltd. Packages formed using RDL-last process
US10535636B2 (en) * 2017-11-15 2020-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Integrating passive devices in package structures
US10685935B2 (en) * 2017-11-15 2020-06-16 Taiwan Semiconductor Manufacturing Company, Ltd. Forming metal bonds with recesses

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020197458A1 (en) * 1998-12-29 2002-12-26 Industrial Technology Research Institute Method for improving integrated circuits bonding firmness
CN1669123A (zh) * 2002-07-15 2005-09-14 因芬尼昂技术股份公司 具应力吸收半导体层之半导体组件及其制造方法
CN1941344A (zh) * 2005-09-27 2007-04-04 台湾积体电路制造股份有限公司 焊垫
US20100140752A1 (en) * 2008-12-10 2010-06-10 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Compliant Polymer Layer Between UBM and Conformal Dielectric Layer/RDL for Stress Relief
US20110193197A1 (en) * 2010-02-05 2011-08-11 International Business Machines Corporation Structure and method for making crack stop for 3d integrated circuits

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109712953A (zh) * 2017-10-25 2019-05-03 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法和半导体器件
CN109712953B (zh) * 2017-10-25 2020-10-16 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法和半导体器件
WO2020088208A1 (en) * 2018-11-01 2020-05-07 Changxin Memory Technologies, Inc. Wafer stacking method and wafer stacking structure
US11348873B2 (en) 2018-11-01 2022-05-31 Changxin Memory Technologies, Inc. Wafer stacking method and wafer stacking structure
CN110085605A (zh) * 2018-11-12 2019-08-02 友达光电股份有限公司 显示装置
CN110085605B (zh) * 2018-11-12 2021-07-06 友达光电股份有限公司 显示装置
CN111128721A (zh) * 2019-12-04 2020-05-08 长江存储科技有限责任公司 存储器的制作方法及存储器
CN112259510A (zh) * 2020-10-23 2021-01-22 中北大学 高过载环境中工作的传感器封装防护结构及其制备方法
CN112259510B (zh) * 2020-10-23 2022-11-22 中北大学 高过载环境中工作的传感器封装防护结构及其制备方法

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