CN107256853A - 钝化后互连结构及其形成方法 - Google Patents

钝化后互连结构及其形成方法 Download PDF

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Publication number
CN107256853A
CN107256853A CN201710272117.9A CN201710272117A CN107256853A CN 107256853 A CN107256853 A CN 107256853A CN 201710272117 A CN201710272117 A CN 201710272117A CN 107256853 A CN107256853 A CN 107256853A
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China
Prior art keywords
layer
conductive
interconnection
protective layer
imc
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CN201710272117.9A
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Inventor
吴逸文
林正怡
何明哲
刘重希
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN107256853A publication Critical patent/CN107256853A/zh
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Abstract

一种半导体器件包括：导电层，该导电层通过浸镀锡工艺形成于钝化后互连(PPI)结构的表面上；聚合物层，该聚合物层形成于导电层上并且经图案化具有暴露出一部分导电层的开口；以及焊料凸块，该焊料凸块形成于聚合物层的开口中以电连接至PPI结构。本发明提供了钝化后互连结构及其形成方法。

Description

钝化后互连结构及其形成方法
本申请要求是于2012年2月9日提交的申请号为201210028995.3的名称为“钝化后互连结构及其形成方法”的发明专利申请的分案申请。
技术领域
本发明涉及半导体器件的制造，更具体而言，涉及钝化后互连(PPI)结构的制造。
背景技术
现代集成电路由数百万有源器件(诸如，晶体管和电容器)组成。这些器件最初彼此隔离，但随后被互连在一起形成了功能电路。典型的互连结构包括横向互连，诸如金属线(引线)；以及纵向互连，诸如通孔和接触件。互连对现代集成电路的性能限定和密度具有越来越大的决定作用。在互连结构的顶部上，在相应芯片的表面上形成并暴露出接合焊盘。通过接合焊盘形成电连接以使芯片与封装衬底或另一个管芯相连接。接合焊盘可以被用于引线接合或倒装芯片接合。倒装芯片封装使用凸块在芯片的输入/输出(I/O)焊盘和封装件的衬底或引线框之间建立电接触。在结构上，凸块实际上包括凸块本身以及位于凸块和I/O焊盘之间的“凸块下金属化层”(UBM)。
现今，晶圆级芯片规模封装(WLCSP)由于其低成本和相对较为简单的工艺而得到广泛应用。在典型的WLCSP中，在钝化层上形成钝化后互连(PPI)线(诸如，再分配线(RDL))，然后再形成聚合物膜和凸块。然而，凸块和聚合物层之间的界面的粘合性很差并且会受到湿气侵袭，这可能导致聚合物层分层。
发明内容
本发明提供了一种半导体器件，所述半导体器件包括：半导体衬底；钝化层，所述钝化层位于所述半导体衬底的上面；互连层，所述互连层位于所述钝化层的上面并且包括线区域和接合焊盘区域；导电层，所述导电层形成于所述互连层的表面上，其中，所述导电层包含锡(Sn)；保护层，所述保护层形成于所述导电层上并且包括开口，所述开口暴露出位于所述接合焊盘区域上的一部分所述导电层；以及焊料凸块，所述焊料凸块形成于所述保护层的所述开口中并且被配置成与所述导电层电连接。
在上述半导体器件中，所述导电层包括金属间化合物(IMC)层。
在上述半导体器件中，所述IMC层包含铜和锡。
在上述半导体器件中，所述导电层包括位于所述互连层的所述线区域上的第一IMC层，以及位于所述接合焊盘区域上的第二IMC层。
在上述半导体器件中，所述第二IMC层比所述第一IMC层厚。
在上述半导体器件中，所述保护层包括聚合物层。
在上述半导体器件中，所述互连层包括铜层或铜合金层。
上述半导体器件进一步包括位于所述互连层和所述钝化层之间的另一保护层。
在上述半导体器件中，所述另一保护层包括聚合物层。
另一方面，本发明提供了一种封装组件，所述封装组件包括通过焊料结构与衬底电连接的半导体器件，所述半导体器件包括：钝化后互连(PPI)结构，所述PPI结构包括线区域和接合焊盘区域；金属间化合物(IMC)层，所述IMC层位于所述PPI结构的所述线区域和所述接合焊盘区域的表面上，其中，所述IMC层包含锡和铜；以及保护层，所述保护层位于所述IMC层上并且暴露出位于所述PPI结构的所述接合焊盘区域上的一部分所述IMC层，其中，所述焊料结构形成于所述IMC层的暴露部分上。
在上述封装组件中，所述衬底包括导电迹线。
在上述封装组件中，所述焊料结构形成于所述IMC层和所述导电迹线之间。
在上述封装组件中，位于所述PPI结构的所述接合焊盘区域上的所述IMC层比位于所述PPI结构的所述线区域上的所述IMC层厚。
在上述封装组件中，所述保护层包括聚合物层。
在上述封装组件中，所述PPI结构包括铜层或铜合金层。
又一方面，本发明提供了一种方法，所述方法包括：在半导体衬底上面形成钝化层；在所述钝化层上面形成互连层，其中，所述互连层包括线区域和接合焊盘区域；采用浸镀工艺在所述互连层的表面上形成包含锡的金属层；在所述金属层上形成保护层；以及在所述保护层中形成开口以暴露出位于所述互连层的所述接合焊盘区域上的一部分所述金属层。
上述方法进一步包括在所述保护层的所述开口中形成焊料凸块。
上述方法进一步包括对所述焊料凸块实施热回流工艺。
上述方法进一步包括在所述互连层和所述保护层之间形成包含锡和铜的金属间化合物层。
上述方法进一步包括在所述互连层和所述焊料凸块之间形成包含锡和铜的金属间化合物层。
附图说明
图1至图5是示出了根据示例性实施例形成具有钝化后互连(PPI)结构的半导体器件的方法的各个中间阶段的剖面图；
图6是根据示例性实施例的具有金属间化合物(IMC)层的PPI结构的剖面图；以及
图7是根据示例性实施例的封装组件的剖面图。
具体实施方式
在下面详细讨论本发明各实施例的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体环境中实现的可应用的概念。所讨论的具体实施例仅仅是制造和使用本发明的示例性具体方式，而不用于限制本发明的范围。本文所述的实施例涉及用于半导体器件的凸块结构的应用。如将在下面所讨论的那样，所公开的实施例应用凸块结构将一个衬底接合至另一个衬底，其中，每个衬底都可以是管芯、晶圆、插件衬底、印刷电路板、或封装衬底等，从而实现了管芯对管芯、晶圆对管芯、晶圆对晶圆、或管芯或晶圆对插件衬底或印刷电路板或封装衬底等。在所有各个视图和示例性实施例中，类似的参考标号用于表示类似的元件。
现详细参考附图中所示出的示例性实施例。只要有可能，在附图和说明书中所用的相同的参考标号是指相同或类似的元件。为了清楚和简便，可以放大附图中的形状和厚度。本说明书将具体涉及形成根据本发明的装置的部分或更直接地与根据本发明的装置相结合的元件。可以理解，未具体地示出或描述的元件可以采用本领域技术人员公知的各种形式。另外，当一层被称为位于另一层上或在衬底“上”时，可以是直接位于另一层上或位于衬底上，或者也可以存在中间层。在整个说明书中提及的“一个实施例”或“实施例”意味着关于该实施例所描述的特定的部件、结构或特征被包括在至少一个实施例中。因此，在本说明书全文的各个位置中出现的短语“在一个实施例中”或“在实施例中”不一定全都是指相同的实施例。另外，在一个或多个实施例中可以以任何合适的方式组合这些特定的部件、结构或特征。应当理解，下面的附图没有按比例绘制；而且，这些附图仅仅是用于说明的目的。
图1至图5示出了根据实施例形成半导体器件的方法的各个中间阶段。首先参考图1，根据实施例，示出了具有在其上形成的电路的衬底10的一部分。衬底10可以包括，例如，体硅(掺杂的或未掺杂的)或绝缘体上半导体(SOI)衬底的有源层。可以将衬底10设置成晶圆级尺寸或芯片级尺寸。也可以使用其他衬底，诸如多层衬底或梯度衬底。
在衬底10上形成的电路12可以是适用于特定用途的任何类型的电路。在实施例中，电路12包括在衬底10上形成的电子器件以及位于该电子器件上面的一个或多个介电层。可以在介电层之间形成金属层以在电子器件之间发送电信号。也可以在一个或多个介电层中形成电子器件。例如，电路12可以包括互连用于实施一个或多个功能的各种N型金属氧化物半导体(NMOS)和/或P型金属氧化物半导体(PMOS)器件，诸如晶体管、电容器、电阻器、二极管、光电二极管、和熔丝等。这些功能可以包括存储器结构、处理结构、传感器、放大器、功率分配、或输入/输出电路等。本领域普通技术人员将理解，以上实例仅仅用于说明的目的，以进一步解释一些示例性实施例的用途，并不以任何方式限制本发明。也可以使用适用于给定用途的其他电路。
图1中还示出了层间介电(ILD)层14。ILD层14可以通过任何适当的方法诸如旋涂、化学汽相沉积(CVD)和/或等离子体增强CVD(PECVD)由例如低K介电材料(诸如，磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、氟化的硅酸盐玻璃(FSG)、SiOxCy、旋涂玻璃、旋涂聚合物、硅碳材料、其化合物、其复合物、或其组合等)形成。在一些实施例中，ILD层14可以包括多个介电层。可以形成穿过ILD层14的接触件(未示出)，从而提供与电路12的电接触。该接触件可以由例如TaN、Ta、TiN、Ti、CoW、铜、钨、铝、或银等、或其组合的一个或多个层形成。
在ILD层14上方形成一个或多个金属间介电(IMD)层16以及相关的金属化层18。通常，使用一个或多个IMD层16和相关的金属化层(诸如，金属线18和通孔19)以使电路12彼此互连并且用于提供外部电连接。IMD层16可以由低K介电材料(诸如，FSG)通过PECVD技术或高密度等离子体CVD(HDPCVD)等形成，并且可以包括中间蚀刻停止层。在一些实施例中，可以在相邻的介电层(例如，ILD层14和IMD层16)之间设置一个或多个蚀刻停止层(未示出)。通常，蚀刻停止层在形成通孔和/或接触件时提供用于停止蚀刻工艺的机构。这些蚀刻停止层由其蚀刻选择性与相邻的层(例如，下面的半导体衬底10、上面的ILD层14以及上面的IMD层16)不同的介电材料形成。在实施例中，蚀刻停止层可以由SiN、SiCN、SiCO、CN、或其组合等通过CVD或PECVD技术沉积而形成。
在一些实施例中，金属化层可以由铜或铜合金或者由其他金属形成。本领域技术人员应了解金属化层的形成细节。另外，金属化层包括在最上面的IMD层中或在最上面的IMD层上形成并且经图案化的顶部金属层20，该顶部金属层20用于提供外部电连接并且用于保护下面各层免受各种环境污染。在一些实施例中，最上面的IMD层可以由介电材料(诸如，氮化硅、氧化硅、和未掺杂的硅玻璃等)形成。在后面的附图中，未示出半导体衬底10、电路12、ILD层14以及金属化层18和19。在一些实施例中，形成顶部金属层20作为位于最上面的IMD层上的顶部金属层的一部分。
此后，形成导电焊盘22并且将其图案化以接触顶部金属层20，或者可选地通过通孔电连接至顶部金属层20。在一些实施例中，导电焊盘22可以由铝、铝铜、铝合金、铜、或铜合金等形成。
参考图1，在导电焊盘22上方形成并且图案化一个或多个钝化层，诸如钝化层24。在一些实施例中，钝化层24可以由介电材料(诸如，未掺杂的硅酸盐玻璃(USG)、氮化硅、氧化硅、氮氧化硅或无孔材料)通过任何适当的方法(诸如，CVD、或PVD等)形成。形成钝化层24用于覆盖导电焊盘22的周围部分并且通过钝化层24中的开口暴露出导电焊盘22的中央部分。钝化层24可以是单层或层压层。本领域普通技术人员将理解，所示出的单层导电焊盘和钝化层仅仅用于说明的目的。因此，其他实施例可以包括任意数量的导电层和/或钝化层。
接下来，在钝化层24上方形成并且图案化第一保护层26。在一些实施例中，第一保护层26可以是例如聚合物层，将其图案化以形成开口27，通过该开口27暴露出导电焊盘22。在一些实施例中，聚合物层可以由聚合物材料(诸如，环氧树脂、聚酰亚胺、苯并环丁烯(BCB)、和聚苯并恶唑(PBO)等)形成，但是也可以使用其他相对较软的，通常是有机的介电材料。形成方法包括旋涂或其他方法。
参考图2，至少一个金属化层形成于第一保护层26上并且填充开口27，然后经图案化作为互连层28，该互连层28与导电焊盘22电连接并且可以暴露出一部分第一保护层26。在至少一个实施例中，互连层28是钝化后互连(PPI)结构28，其也可以作为电源线、再分配线(RDL)、电感器、电容器或任何无源元件起作用。PPI结构28包括互连线区域28I和接合焊盘区域(landing pad region)28P。在一些实施例中，互连线区域28I和接合焊盘区域28P可以同时形成，并且可以由相同的导电材料形成。在后续工艺中，将在接合焊盘区域28P上方形成凸块部件，并且该凸块部件与接合焊盘区域28P电连接。在一些实施例中，PPI结构28可以包含铜、铝、铜合金或其他可移动导电材料，采用电镀、化学镀、溅射、和化学汽相沉积方法等形成。在一个实施例中，PPI结构28包括铜层或铜合金层。在图2的实施例中，装配区域28P不直接位于导电焊盘22上方。在其他实施例中，通过PPI结构28的布线，接合焊盘区域28P直接位于导电焊盘22上方。
参考图3，在PPI结构28上形成导电层34。在实施例中，导电层34是包含锡的金属层。在一些实施例中，导电层34包括至少一个锡层或至少一个锡合金层。在一些实施例中，导电层34可以保护PPI结构28的表面防止PPI结构28中的铜扩散到接合材料中。在一些实施例中，导电层34也可以充当抗氧化层来防止PPI结构28的铜表面在后续加工过程中被氧化。在一些实施例中，导电层34可以进一步充当粘合层起作用，该粘合层改进了PPI结构28和随后形成的聚合物层之间的界面粘合性。因此，导电层34可以增加封装件的可靠性和接合强度。在一些实施例中，导电层34的厚度小于约3μm，例如，厚度为约0.1μm至约3μm。
在一些实施例中，导电层34的形成方法包括浸镀工艺(immersion process)或化学镀工艺，其中以自对准方式在PPI结构28的表面上形成导电层34。在一个实施例中，导电层34是包括浸镀Sn层的单层结构。在一个实施例中，导电层34是包括化学镀Ni层、化学镀Pd层以及浸镀Au层的三层结构，该结构也被称为ENEPIG结构。例如，该ENEPIG结构可以具有厚度为至少0.5μm的化学镀Ni层、厚度为至少0.02μm的化学镀Pd层以及厚度为至少0.01μm的浸镀Au层。在一个实施例中，导电层34是包括化学镀Ni层和化学镀Pd层的双层结构，被称为ENEP结构。在一个实施例中，导电层34是包括化学镀Ni层以及浸镀Au层的双层结构，该结构也被称为ENIG结构。
参考图4，然后在衬底10上形成第二保护层30来覆盖导电层34。在一些实施例中，第二保护层30延伸以覆盖第一保护层26的暴露部分。采用光刻和/或蚀刻工艺，进一步图案化第二保护层30以形成开口32，该开口32暴露出位于PPI结构28的接合焊盘区域28P中的至少一部分导电层34。开口32的形成方法可以包括光刻、湿式或干式蚀刻、和/或激光钻孔等。在一些实施例中，第二保护层30由聚合物层(诸如，环氧树脂、聚酰亚胺、苯并环丁烯(BCB)、和聚苯并恶唑(PBO)等)形成，但是也可以使用其他相对较软的，通常是有机的介电材料。在一些实施例中，第二保护层30由选自未掺杂的硅酸盐玻璃(USG)、氮化硅、氮氧化硅、氧化硅及其组合的非有机材料形成。
如图5中所示，在导电层34的暴露部分上形成焊料凸块36，以便与PPI结构28电连接。在一个实施例中，通过在开口32中接合焊球然后热回流焊料材料来形成焊料凸块36。在一些实施例中，焊料凸块36可以包括无铅的预焊料层、SnAg或包括锡、铅、银、铜、镍、铋或其组合的合金的焊料材料。在实施例中，焊料凸块36具有大于30μm的厚度。在一些实施例中，焊料凸块36具有约40μm至约70μm的厚度，但是该厚度可以更大或更小。在一些实施例中，可以通过用光刻技术电镀焊料层，然后通过回流工艺来形成焊料凸块。在一些实施例中，焊料凸块36具有约200μm至约300μm的直径。在其他实施例中，焊料凸块36具有约100μm至约200μm的直径。在又一些实施例中，焊料凸块36具有约50μm至约100μm的直径。在又一些实施例中，焊料凸块36具有约10μm至50μm的直径。在一些实施例中，焊料凸块36包括所谓的“微凸块”。
在一些实施例中，在热回流工艺过程中，导电层34中的锡(Sn)易于与PPI结构28中的铜(Cu)反应，从而在其间形成金属间化合物(IMC)层。在一个实施例中，导电层34在IMC形成过程中被完全消耗掉，在PPI结构28和第二保护层30之间形成了Cu-Sn IMC层34a。在一些实施例中，导电层34中的锡(Sn)易于与焊料凸块36中的锡(Sn)以及PPI结构28中的铜(Cu)反应，从而在其间形成另一金属间化合物(IMC)层。在一个实施例中，导电层34在IMC形成过程中被完全消耗掉，在焊料凸块36和PPI结构28的接合焊盘区域28P之间形成Cu-Sn IMC层34b。在实施例中，Cu-Sn IMC层34b比Cu-Sn IMC层34a厚。由此，完成了具有PPI结构28和焊料凸块36的半导体器件100。
所示的实施例在PPI结构28上设置导电层34作为抗氧化膜，以避免加工过程中的铜氧化。导电层34还被用作PPI结构28和第二保护层30之间的粘合膜，该粘合膜可以增强铜层和聚合物层之间的界面粘合性并保护铜层免受湿气侵袭，从而消除了聚合物层之间的分层问题或焊料凸块和聚合物层之间的分层问题。导电层34进一步充当焊料凸块36和接合焊盘区域28P之间的保护膜，从而防止PPI结构28中的铜扩散到焊料材料中。由此，在封装组件工艺中，能够增强接点可靠性并且能够降低凸块疲劳。
在凸块形成之后，例如，可以形成封装件，可以实施分离工艺来分离各个管芯，以及可以实施晶圆级或管芯级堆叠等。然而，应该注意，这些实施例可以用于许多不同的情况。例如，实施例可以用于管芯对管芯接合结构、管芯对晶圆接合结构、晶圆对晶圆接合结构、管芯级封装、或晶圆级封装等。
图7是描述倒装芯片组件的示例性实施例的剖面图。图6中所示的器件100被翻转倒置并接合至图6的位于底部的另一衬底200。在一些实施例中，衬底200可以是封装衬底、板(例如，印刷电路板(PCB))、晶圆、管芯、插件衬底或其他适当的衬底。凸块结构通过各种导电接合点连接至衬底200。例如，在衬底200上形成并且图案化导电区域202。导电区域202是接触焊盘或导电迹线的一部分，其通过掩模层204显示出来。在一个实施例中，掩模层204是在衬底200上形成的并经图案化以暴露出导电区域202的阻焊层。掩模层204具有掩模开口，该开口提供了用于焊接形成的窗口。例如，可以在导电区域202上设置包含锡、铅、银、铜、镍、铋或其组合的合金的焊料层。在一些实施例中，器件100可以与衬底200相连接以在导电层34和导电区域202之间形成接点焊料结构206。示例性连接工艺包括助焊剂应用、芯片放置、回流熔化的焊料接点和/或清洗助焊剂残余物。集成电路器件100、接点焊料结构206以及另一衬底200可以被称为封装组件300，或者在本实施例中可以被称为倒装芯片封装组件。
根据示例性实施例的一个方面，半导体器件包括：位于半导体衬底上面的钝化层；互连层，该互连层位于钝化层上面并且经图案化具有线区域和接合焊盘区域；在互连层的表面上形成的包含锡(Sn)的导电层；在导电层上形成的并且具有开口的保护层，该开口暴露出位于接合焊盘区域上的一部分导电层；以及在保护层的开口上形成的并且与导电层电连接的焊料凸块。在实施例中，导电层包括金属间化合物(IMC)层。在实施例中，IMC层包含铜和锡。在实施例中，导电层包括位于互连层的线区域上的第一IMC层，以及位于接合焊盘区域上的第二IMC层。在实施例中，第二IMC层比第一IMC层厚。在一些实施例中，保护层包括聚合物层，互连层包括铜层或铜合金层。在其他实施例中，在互连层和钝化层之间形成另一保护层，并且该保护层包括聚合物层。
根据示例性实施例的另一方面，封装组件包括通过焊料结构与衬底电连接的半导体器件。该半导体器件包括钝化后互连(PPI)结构，该PPI结构包括线区域和接合焊盘区域；位于PPI结构的线区域和接合焊盘区域的表面上的金属间化合物(IMC)层；以及位于IMC层上并且暴露出位于PPI结构的接合焊盘区域上的一部分IMC层的保护层。IMC层包含锡和铜，以及焊料结构形成于IMC层的暴露部分上。在实施例中，衬底包括导电迹线，以及焊料结构形成于IMC层和导电迹线之间。在实施例中，位于PPI结构的接合焊盘区域上的IMC层比位于PPI结构的线区域上的IMC层厚。在一些实施例中，保护层包括聚合物层，以及PPI结构包括铜层或铜合金层。
根据示例性实施例的其他方面，一种方法包括：提供半导体衬底；在半导体衬底上面形成钝化层；在钝化层上面形成互连层，该互连层包括线区域和接合焊盘区域；采用浸镀工艺在互连层的表面上形成包含锡的金属层；在金属层上形成保护层；以及在保护层中形成开口以暴露出位于互连层的接合焊盘区域上的一部分金属层。在实施例中，该方法进一步包括：在保护层的开口上形成焊料凸块，以及对该焊料凸块实施热回流工艺。在实施例中，该方法进一步包括：在互连层和保护层之间形成包含锡和铜的金属间化合物层。在实施例中，该方法进一步包括在互连层和焊料凸块之间形成包含锡和铜的金属间化合物层。
在上述详细描述中，参考本发明的具体的示例性实施例描述了本发明。然而，很明显在不背离本发明更广泛的主旨和范围的情况下，可以进行各种更改、结构、工艺以及改变。因此，本说明书和附图被视为说明性的而不是限制性的。可以理解，本发明可以使用各种其他组合和环境且能够在本文所表达的发明理念的范围内进行改变或更改。

Claims (15)

1.一种半导体器件，包括：
半导体衬底；
导电焊盘，位于所述半导体衬底的上面；
钝化层，位于所述半导体衬底和所述导电焊盘的上面；
第一保护层，位于所述钝化层上面；
互连层，位于所述第一保护层的上面并且包括线区域和接合焊盘区域，其中，所述互连层与所述导电焊盘直接接触；
导电层，所述导电层是金属间化合物(IMC)层并且形成于所述互连层的所述线区域和所述接合焊盘区域的表面上，所述导电层两端延伸出的两侧壁内侧与所述互连层的两端侧壁相接，并且所述导电层两端延伸出的两侧壁相对，其中，所述导电层包含锡(Sn)；
第二保护层，形成于所述导电层上并且包括开口，所述开口暴露出位于所述接合焊盘区域上的一部分所述导电层，其中，所述导电层用作所述互连层与所述第二保护层之间的粘合膜以保护所述互连层免受湿气侵袭；以及
焊料凸块，形成于所述第二保护层的所述开口中并且被配置成与所述金属间化合物层电连接，所述金属间化合物层的位于所述开口中的部分的顶面高于所述金属间化合物层的未位于所述开口中的部分的顶面，其中，在所述线区域上，所述焊料凸块远离所述导电焊盘的最大距离大于所述导电层远离所述导电焊盘的最大距离。
2.根据权利要求1所述的半导体器件，其中，所述IMC层包含铜和锡。
3.根据权利要求1所述的半导体器件，其中，所述导电层包括位于所述互连层的所述线区域上的第一IMC层，以及位于所述接合焊盘区域上的第二IMC层。
4.根据权利要求3所述的半导体器件，其中，所述第二IMC层比所述第一IMC层厚。
5.根据权利要求1所述的半导体器件，其中，所述第二保护层包括聚合物层。
6.根据权利要求1所述的半导体器件，其中，所述互连层包括铜层或铜合金层。
7.根据权利要求1所述的半导体器件，其中，所述第一保护层包括聚合物层。
8.一种封装组件，包括通过焊料结构与衬底电连接的半导体器件，所述半导体器件包括：
导电焊盘，位于所述衬底的上面；
第一保护层，位于所述导电焊盘的上方；
钝化后互连(PPI)结构，位于所述第一保护层上面，所述PPI结构包括线区域和接合焊盘区域，其中，所述PPI结构与所述导电焊盘直接接触；
金属间化合物(IMC)层，位于所述PPI结构的所述线区域和所述接合焊盘区域的表面上，所述IMC层两端延伸出的两侧壁内侧与所述PPI结构的两端侧壁相接，并且所述IMC层两端延伸出的两侧壁相对，其中，所述IMC层包含锡和铜；以及
第二保护层，位于所述IMC层上并且暴露出位于所述PPI结构的所述接合焊盘区域上的一部分所述IMC层，其中，所述金属间化合物层用作所述钝化后互连结构与所述第二保护层之间的粘合膜以保护所述钝化后互连结构免受湿气侵袭，
其中，所述焊料结构形成于所述IMC层的暴露部分上，所述金属间化合物层的暴露部分的顶面高于所述金属间化合物层的非暴露部分的顶面，其中，在所述线区域上，所述焊料结构远离所述导电焊盘的最大距离大于所述IMC层远离所述导电焊盘的最大距离。
9.根据权利要求8所述的封装组件，其中，所述衬底包括导电迹线。
10.根据权利要求9所述的封装组件，其中，所述焊料结构形成于所述IMC层和所述导电迹线之间。
11.根据权利要求8所述的封装组件，其中，位于所述PPI结构的所述接合焊盘区域上的所述IMC层比位于所述PPI结构的所述线区域上的所述IMC层厚。
12.根据权利要求8所述的封装组件，其中，所述第二保护层包括聚合物层。
13.根据权利要求8所述的封装组件，其中，所述PPI结构包括铜层或铜合金层。
14.一种形成半导体器件的方法，包括：
在半导体衬底上形成导电焊盘；
在导电焊盘上面形成钝化层；
在所述钝化层上面形成第一保护层；
在所述第一保护层上面形成互连层，其中，所述互连层包括线区域和接合焊盘区域，其中，所述互连层与所述导电焊盘直接接触；
采用浸镀工艺在所述互连层的表面上形成包含锡的金属层，其中，所述金属层形成于所述互连层的所述线区域和所述接合焊盘区域的表面上，所述金属层两端延伸出的两侧壁内侧与所述互连层的两端侧壁相接，并且所述金属层两端延伸出的两侧壁相对；
在所述金属层上形成第二保护层；
在所述第二保护层中形成开口以暴露出位于所述互连层的所述接合焊盘区域上的一部分所述金属层；以及
在所述互连层和所述第二保护层之间形成包含锡和铜的金属间化合物层，其中，所述金属间化合物层用作所述互连层与所述第二保护层之间的粘合膜以保护所述互连层免受湿气侵袭；
在所述第二保护层的所述开口中形成焊料凸块；以及
在所述互连层和所述焊料凸块之间形成包含锡和铜的金属间化合物层，其中，所述互连层和所述焊料凸块之间形成的金属间化合物层的顶面高于所述互连层和所述第二保护层之间形成的金属间化合物层的顶面，其中，在所述线区域上，所述焊料凸块远离所述导电焊盘的最大距离大于所述金属间化合物层远离所述导电焊盘的最大距离。
15.根据权利要求14所述的方法，进一步包括对所述焊料凸块实施热回流工艺。
CN201710272117.9A 2011-11-08 2012-02-09 钝化后互连结构及其形成方法 Pending CN107256853A (zh)

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Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI449141B (zh) * 2011-10-19 2014-08-11 Richtek Technology Corp 晶圓級晶片尺度封裝元件以及其製造方法
US9099396B2 (en) 2011-11-08 2015-08-04 Taiwan Semiconductor Manufacturing Company, Ltd. Post-passivation interconnect structure and method of forming the same
US9059109B2 (en) * 2012-01-24 2015-06-16 Taiwan Semiconductor Manufacturing Company, Ltd. Package assembly and method of forming the same
US8884400B2 (en) * 2012-12-27 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Capacitor in Post-Passivation structures and methods of forming the same
US9236320B2 (en) * 2013-06-28 2016-01-12 Xintec Inc. Chip package
US9466581B2 (en) * 2013-10-18 2016-10-11 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package device and manufacturing method thereof
TWI576869B (zh) * 2014-01-24 2017-04-01 精材科技股份有限公司 被動元件結構及其製作方法
US9466560B2 (en) * 2014-05-28 2016-10-11 United Microelectronics Corp. Interposer fabricating process and wafer packaging structure
US9397056B2 (en) * 2014-06-03 2016-07-19 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device having trench adjacent to receiving area and method of forming the same
WO2016002455A1 (ja) * 2014-07-03 2016-01-07 Jx日鉱日石金属株式会社 放射線検出器用ｕｂｍ電極構造体、放射線検出器及びその製造方法
US9543259B2 (en) * 2014-10-01 2017-01-10 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure with oval shaped conductor
JP6455091B2 (ja) * 2014-11-12 2019-01-23 富士通株式会社 電子装置及び電子装置の製造方法
US9520372B1 (en) * 2015-07-20 2016-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level package (WLP) and method for forming the same
JP2017033984A (ja) * 2015-07-29 2017-02-09 セイコーエプソン株式会社 半導体装置及びその製造方法、並びに、電子機器
US10049996B2 (en) * 2016-04-01 2018-08-14 Intel Corporation Surface finishes for high density interconnect architectures
US10403591B2 (en) * 2017-10-31 2019-09-03 Xilinx, Inc. Chip package assembly with enhanced interconnects and method for fabricating the same
CN107968092B (zh) * 2017-11-16 2018-12-14 长江存储科技有限责任公司 3d nand中的金属间化合物保护层及其形成方法
TWI717845B (zh) * 2019-09-20 2021-02-01 華邦電子股份有限公司 封裝結構及其形成方法
US11251100B2 (en) * 2019-09-25 2022-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure having an anti-arcing pattern disposed on a passivation layer and method of fabricating the semiconductor structure
US11145596B2 (en) 2019-12-17 2021-10-12 Winbond Electronics Corp. Package structure and method of forming the same
TWI789748B (zh) 2021-04-26 2023-01-11 友達光電股份有限公司 電子裝置及其製造方法
CN114509884B (zh) * 2022-02-24 2023-11-17 京东方科技集团股份有限公司 线路板及其制备方法、功能背板、背光模组和显示装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWM398194U (en) * 2010-04-15 2011-02-11 di-qun Hu Semiconductor package device
US20110101520A1 (en) * 2009-10-29 2011-05-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Die Contact Structure and Method
CN102094202A (zh) * 2009-12-15 2011-06-15 同和金属技术有限公司 Cu系材料的Sn镀层的剥离方法

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10135270A (ja) * 1996-10-31 1998-05-22 Casio Comput Co Ltd 半導体装置及びその製造方法
US6107180A (en) * 1998-01-30 2000-08-22 Motorola, Inc. Method for forming interconnect bumps on a semiconductor die
JP4095731B2 (ja) * 1998-11-09 2008-06-04 株式会社ルネサステクノロジ 半導体装置の製造方法及び半導体装置
AU5109900A (en) * 1999-06-15 2001-01-02 Fujikura Ltd. Semiconductor package, semiconductor device, electronic device, and method of manufacturing semiconductor package
JP3996315B2 (ja) * 2000-02-21 2007-10-24 松下電器産業株式会社 半導体装置およびその製造方法
TW490821B (en) * 2000-11-16 2002-06-11 Orient Semiconductor Elect Ltd Application of wire bonding technique on manufacture of wafer bump and wafer level chip scale package
US6743660B2 (en) * 2002-01-12 2004-06-01 Taiwan Semiconductor Manufacturing Co., Ltd Method of making a wafer level chip scale package
TW521390B (en) * 2002-02-01 2003-02-21 Taiwan Semiconductor Mfg Method to produce interconnect with inhibited copper electromigration (EM)
US7701069B2 (en) * 2003-06-30 2010-04-20 Intel Corporation Solder interface locking using unidirectional growth of an intermetallic compound
JP2007073681A (ja) * 2005-09-06 2007-03-22 Renesas Technology Corp 半導体装置およびその製造方法
KR100859641B1 (ko) 2006-02-20 2008-09-23 주식회사 네패스 금속간 화합물 성장을 억제시킨 솔더 범프가 형성된 반도체칩 및 제조 방법
US20100117231A1 (en) * 2006-08-30 2010-05-13 Dennis Lang Reliable wafer-level chip-scale solder bump structure
US7973418B2 (en) * 2007-04-23 2011-07-05 Flipchip International, Llc Solder bump interconnect for improved mechanical and thermo-mechanical performance
US7863742B2 (en) * 2007-11-01 2011-01-04 Taiwan Semiconductor Manufacturing Company, Ltd. Back end integrated WLCSP structure without aluminum pads
US8241954B2 (en) * 2007-12-03 2012-08-14 Stats Chippac, Ltd. Wafer level die integration and method
US7776655B2 (en) * 2008-12-10 2010-08-17 Stats Chippac, Ltd. Semiconductor device and method of forming conductive pillars in recessed region of peripheral area around the device for electrical interconnection to other devices
US8378485B2 (en) * 2009-07-13 2013-02-19 Lsi Corporation Solder interconnect by addition of copper
US8324738B2 (en) * 2009-09-01 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned protection layer for copper post structure
US8659155B2 (en) * 2009-11-05 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming copper pillar bumps
US8659170B2 (en) 2010-01-20 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having conductive pads and a method of manufacturing the same
TWM397597U (en) * 2010-04-15 2011-02-01 Di-Quan Hu Package structure of integrated circuit
US8546254B2 (en) * 2010-08-19 2013-10-01 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming copper pillar bumps using patterned anodes
US9099396B2 (en) * 2011-11-08 2015-08-04 Taiwan Semiconductor Manufacturing Company, Ltd. Post-passivation interconnect structure and method of forming the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110101520A1 (en) * 2009-10-29 2011-05-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Die Contact Structure and Method
CN102094202A (zh) * 2009-12-15 2011-06-15 同和金属技术有限公司 Cu系材料的Sn镀层的剥离方法
TWM398194U (en) * 2010-04-15 2011-02-11 di-qun Hu Semiconductor package device

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