TW201320209A - 半導體元件與其製法 - Google Patents

半導體元件與其製法 Download PDF

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Publication number
TW201320209A
TW201320209A TW101112182A TW101112182A TW201320209A TW 201320209 A TW201320209 A TW 201320209A TW 101112182 A TW101112182 A TW 101112182A TW 101112182 A TW101112182 A TW 101112182A TW 201320209 A TW201320209 A TW 201320209A
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Taiwan
Prior art keywords
layer
interconnect
semiconductor device
protective layer
conductive
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TW101112182A
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English (en)
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TWI466204B (zh
Inventor
Yi-Wen Wu
Zheng-Yi Lim
Ming-Che Ho
Chung-Shi Liu
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Taiwan Semiconductor Mfg
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Publication of TW201320209A publication Critical patent/TW201320209A/zh
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Publication of TWI466204B publication Critical patent/TWI466204B/zh

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Abstract

本發明提供一種半導體元件，其包括藉由浸鍍錫製程形成導電層於後保護層內連線(PPI)結構之上。高分子層形成於導電層之上且被圖案化形成開口，開口暴露導電層的一部份。焊料凸塊形成於高分子層的開口中，以電性連接到後保護層內連線(PPI)結構。

Description

半導體元件與其製法
本發明係有關於一種半導體元件之製法，且特別是有關於一種後保護層內連線(post-passivation interconnect(PPI))結構之製法。
現今之積體電路係由實質上數百萬個主動元件所組成，其中主動元件例如電晶體與電容。這些元件初始彼此絕緣，但藉由後續連接該些元件，以形成一功能性電路。典型的內連線結溝包括水平(lateral)內連線結構(例如金屬線)與垂直內連線(例如導通孔(vias)與接觸插塞(contacts))。對現今積體電路(IC)而言，內連線結構對於其性能與密度之極限的影響日益重要。接合墊(bond pad)會形成於內連線結構的最上層，並暴露於相對應晶片之表面上。藉由接合墊將晶片電性連接到封裝基材或另一晶粒上。接合墊亦使用於打線接合(wire bonding)與覆晶接合(flip-chip bonding)。覆晶接合(flip-chip bonding)利用凸塊建立晶片輸入/輸出(I/O)墊片與基板或封裝導線架之間的電性連接。就結構上而言，凸塊實際上包括凸塊本身與凸塊底層金屬(under-bump metallurgy,UBM)介於凸塊與輸出/輸入(I/O)墊片之間。
晶圓級晶片尺寸封裝(wafer level chip scale packaging,WLCSP)是目前廣泛被使用的一種封裝方法，其成本低且製程簡單。於一般的晶圓級晶片尺寸封裝(WLCSP)中，後保護層內連線(post-passivation interconnect(PPI))結構，例如重新佈線層(redistribution lines,RDLs)形成於保護層上，接著形成高分子層與凸塊。然而，因為介於凸塊與高分子層之間的介面具有較差的黏著力且會受到濕氣的干擾，所以高分子層可能因此脫層。
本發明提供一種半導體元件，包括：一半導體基板；一保護層形成於該半導體基板之上；一內連線層形成於該保護層之上，其中該內連線層包括一連線區域與一座落墊層區域(landing pad region)；一導電層形成於該內連線層之表面上，其中該導電層包括錫(Sn)；一保護層形成於該導電層之上，其中該保護層包括位於該座落墊層區域(landing pad region)之上的一開口，且該開口暴露該導電層之一部份；以及一焊料凸塊形成於該保護層之開口中，用以與該導電層電性連接。
本發明另提供一種封裝結構，包括一半導體元件藉由一焊料結構電性連接到一基板，其中該半導體元件包括：一後保護層內連線(post-passivation interconnect(PPI))結構，其包括一連線區域與一座落墊層區域(landing pad region)；一介金屬化合物層(intermetallic compound(IMC) layer)，形成於該後保護層內連線(post-passivation interconnect(PPI))結構之該連線區域與該座落墊層區域(landing pad region)之上，其中該介金屬化合物層包括錫與銅；以及一保護層形成於該介金屬化合物層(IMC layer)之上，且該保護層於該後保護層內連線(PPI)結構之該座落墊層區域(landing pad region)之上暴露該介金屬化合物層之一部份；其中該焊料結構形成於該介金屬化合物層之暴露部份上。
本發明亦提供一種半導體元件之製法，包括以下步驟：形成一保護層於一半導體基板之上；形成一內連線層於該保護層之上，其中該內連線層包括一連線區域與一座落墊層區域(landing pad region)；使用一浸鍍製程(immersion process)形成一金屬層於該內連線層之表面上，其中該金屬層包括錫(Sn)；形成一保護層於該金屬層之上；以及於該保護層中形成一開口，以暴露位於該內連線層之座落墊層區域(landing pad region)之上的金屬層之一部份。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：
以下特舉出本發明之實施例，並配合所附圖式作詳細說明。以下實施例的元件和設計係為了簡化所揭露之發明，並非用以限定本發明。此處所揭露之實施例係關於半導體元件使用凸塊結構。如下所述，所揭露之實施例為了將一基板附著於另一基板上，所以使用凸塊結構，其中毎個基板各自可包括晶粒、晶圓、中介層基板(interposer substrate)、印刷電路板(printed circuit board)、封裝結構或類似之結構，因此可達成晶粒對晶粒(die-to-die)、晶圓對晶粒(wafer-to-die)、晶圓對晶圓(wafer-to-wafer)、晶粒或晶圓對中介層基板(die or wafer to interposer substrate)、印刷電路板或封裝結構或類似之結構。於本發明於各個實施例中，相同的元件係使用相同的參考符號。
下述實施例伴隨圖式作說明。圖式中相同的參考標號代表相同或類似的元件。於圖中，為了簡化與清晰的目的，元件的形狀與厚度可能被擴大。依據本發明所揭露之實施例，本文所述特別是形成一裝置之一部份的元件，或是與該裝置直接協同作用之元件。可了解的是，元件可能未顯示成本領域人士所熟知之各種形狀。再者，當一層形成於另一層之上或於基板之上，可能是直接位於另一層之上或直接位於基板之上，或有可能有其他的中間層。說明書中出現之用語”於一個實施例”或”於一實施例”意指一特定之結構特徵(feature)、結構(structure)或特性(characteristic)包含於至少本發明之一實施例中。因此，出現於說明書中各處之用語”於一個實施例”或”於一實施例”並不代表相同的實施例。再者，於一或多個實施例中，可以以任何合適方法結合特定之結構特徵(feature)、結構(structure)或特性(characteristic)。須注意的是，下述圖形並非依據尺寸繪製，該些圖式僅為了幫助說明。
第1-5圖顯示本發明實施例之半導體元件的製法流程圖。請先參見第1圖，於本發明之一實施例中，基板10的一部份具有電路形成於其中。基板10可包括，例如摻雜或未摻雜的塊狀矽、或主動層的絕緣層上覆矽基材(silicon on insulator,SOI)。基板10可以是晶圓級(wafer level scale)或晶片級。亦可使用其他基板，例如多層基板或梯度基板(gradient subatrate)。
形成於基板10之上的電子電路12可以是適用於特定應用的任何類型。於一實施例中，電子電路12包括電子元件形成於基板10之上，與一或多層介電層形成於電子元件之上。金屬層可形成於介電層之間，用以佈局電子元件的電子訊號。電子元件亦可形成於一或多個介電層中。舉例而言，電子電路12可包括各種彼此連接的N-型金屬氧化物半導體(NMOS)及/或P-型金屬氧化物半導體(PMOS)，例如電晶體、電容、電阻、二極體、光二極體、保險絲或類似的元件，以執行一或多個功能。這些功能可包括記憶體結構(memory structures)、處理器結構(processing structures)、感測器(sensors)、放大器(amplifiers)、電源分佈(power distribution)、輸出/輸入電路(input/output circuitry)或類似之結構。本領域人士應能了解的是，上述實施例僅用以舉例說明，並非用以限定本發明。對於特定的應用亦可使用其他電路。
第1圖顯示一層間介電層(inter-layer dielectric(ILD) layer) 14。層間介電層(ILD layer) 14可由例如，低介電常數(low-K)材料所組成，例如磷矽玻璃(phosphosilicate Glass,PSG)、硼磷矽玻璃(borophosphosilicate Glass,BPSG)、氟矽玻璃(fluorinated silica glass,FSG)、SiOxCy、旋塗式玻璃(Spin-On-Glass)、旋塗式高分子(Spin-On-Polymer)、碳矽材料、或上述之化合物，或上述之複合物或上述之組合，或類似之材料。層間介電層(ILD layer) 14可由合適的方法形成，例如化學氣相沉積法(CVD)及/或電漿增強型化學氣相沉積法(PECVD)。於一些實施例中，層間介電層(ILD layer) 14可包括複數層介電層。導電接觸(圖中未顯示)可形成於層間介電層(ILD layer) 14中，以提供電性接觸到電子電路12。導電接觸可由，例如一或多層氮化鉭(TaN)、鉭(Ta)、氮化鈦(TiN)、鈦(Ti)、鎢化鈷(CoW)、銅、鎢、鋁、銀或類似之材料，或上述之組合而形成。
一或多個金屬層間介電層(inter-metal dielectric(IMD) layer)16與相關的金屬層18形成於層間介電層(ILD layer) 14之上。一般而言，一或多層金屬層間介電層(IMD layer) 16與相關的金屬層18(例如金屬線18與導通孔19)用於電性連接到電子電路12，以提供外部的電路連接。金屬層間介電層(IMD layer)16可由例如，低介電常數(low-K)材料所組成，例如氟矽玻璃(fluorinated silica glass,FSG)所組成。形成金屬層間介電層(IMD layer)16之方法包括電漿增強型化學氣相沉積法(PECVD)或高密度電漿化學氣相沉積法(HDPCVD)，或類似之方法。金屬層間介電層(IMD layer)16可包括中間蝕刻停止層(intermediate etch stop layers)。於一些實施例中，一或多層蝕刻停止層(圖中未顯示)可置於相鄰的介電層之間，介電層例如層間介電層(ILD layer) 14或金屬層間介電層(IMD layer)16。一般而言，當形成導通孔及/或導電接觸時，蝕刻停止層提供蝕刻製程停止的作用。蝕刻停止層由具有不同蝕刻選擇率的相鄰介電材料所組成，例如底層的半導體基板10、半導體基板10之上的層間介電層(ILD layer) 14或金屬層間介電層(IMD layer)16。於一實施例中，蝕刻停止層可由氮化矽(SiN)、碳氮化矽(SiCN)、碳氧化矽(SiCO)、氮化碳(CN)、上述之組合或類似之材料藉由化學氣相沉積法(CVD)或電漿增強型化學氣相沉積法(PECVD)所組成。
於一些實施例中，金屬層可由銅或銅合金，或其他金屬所組成。熟知本領域之人士應能了解形成金屬層之細節。再者，金屬層包括一頂部金屬層20形成於最上層之金屬層間介電層(IMD layer)之上並加以圖案化，以提供外部的電性連接，且保護底下各層免受各種環境的污染。於一些實施例中，最上層之金屬層間介電層(IMD layer)可由介電材料所形成，例如氮化矽、氧化矽、未摻雜的矽玻璃、與類似之材料。於後續的圖式中，半導體基板10、電子電路12、層間介電層(ILD layer) 14、金屬層18與19並未顯示於圖中。於一些實施例中，頂部金屬層20形成於最上層金屬層間介電層(IMD layer)之上，作為最上層金屬層之一部份。
因此，形成導電墊(conductive pad)22並加以圖案化，以電性連接頂部金屬層20，或者藉由導通孔(via)電性連接到頂部金屬層20。於一些實施例中，導電墊22可由鋁、鋁銅合金、鋁合金、銅、銅合金或類似之材料所組成。
於第1圖中，一或多層保護層，例如保護層24形成於導電墊22之上並加以圖案化。於一些實施例中，保護層24可由介電材料所組成，例如未摻雜的矽酸鹽玻璃(undoped silicate glass,USG)、氮化矽、氧化矽、氮氧化矽、或非多孔性材料由合適的方法所形成，方法例如化學氣相沉積法(CVD)、物理氣相沉積法(PVD)或類似之方法。形成保護層24用以覆蓋導電墊22的周邊部份，且藉由形成於保護層中的開口以暴露導電墊22的中心部份。保護層24可以是單一層或是壓合層(laminated layer)。熟知本領域人士應能得知，單一層保護層與導電墊，僅為了幫助說明。因此，其他實施例中可包括多層導電層及/或保護層。
接著，形成於第一保護層26於保護層24之上並加以圖案化。於一些實施例中，第一保護層26可以是，例如高分子層，其被圖案化以形成開口27，藉由開口27暴露出導電墊22。於一些實施例中，高分子層可以是高分子材料，例如環氧樹脂(epoxy)、聚亞醯胺(polyimide)、苯並環丁烯(bis-benzocyclobutenes,BCB)、聚苯噁唑(polybenzoxazole,PBO)或類似之材料，亦可使用其他相對軟的材料，通常是有機材料、介電材料。形成之方法包括旋轉塗佈法(spin coating)或其他方法。
請參見第2圖，至少一金屬層形成於第一保護層26之上且填充開口27，接著金屬層被圖案化形成內連線層28，內連線層26電性連接到導電墊22且可暴露第一保護層26的一部分。於至少一實施例中，內連線層28是後保護層內連線(post-passivation interconnect(PPI))結構28，其可作為電源線、重新佈線層(re-distribution lines,RDL)、電感、電容或其他被動元件。後保護層內連線(PPI)結構28包括內連線區域28I與座落墊層區域(landing pad region) 28P。於一些實施例中，內連線區域28I與座落墊層區域(landing pad region) 28P可同時形成，且可由相同導電材料所組成。於後續步驟中，凸塊結構特徵將會形成於且電性連接於座落墊層區域(landing pad region) 28P上。於一些實施例中，後保護層內連線(PPI)結構28可包括銅、鋁、銅合金或其他流動的導電材料(mobile conductive material)，使用電鍍、無電極電鍍、濺鍍、化學氣相沉積等類似之方法形成。於一實施例中，後保護層內連線(PPI)結構28包括一銅層或一銅合金層。於第2圖之實施例中，座落墊層區域(landing pad region) 28P並未直接位於導電墊22之上。於其他實施例中，藉由後保護層內連線(PPI)結構28之佈線設計，座落墊層區域(landing pad region) 28P可直接位於導電墊22之上。
請參見第3圖，導電層34形成於後保護層內連線(PPI)結構28上。於一實施例中，導電層34是包括錫的金屬層。於一些實施例中，導電層34包括至少一錫層與至少一錫合金層。於一些實施例中，導電層34可保護後保護層內連線(PPI)結構28，以避免後保護層內連線(PPI)結構28中的銅擴散到接合材料(bonding material)中。於一些實施例中，導電層34可作為抗氧化層，以避免後保護層內連線(PPI)結構28中的銅表面受到後續製程的影響而氧化。於一些實施例中，導電層34尚可作為黏著層，可改善後保護層內連線(PPI)結構28與後續形成之高分子層之間的界面黏著力。因此，導電層34可以加強封裝結構的可靠度(reliability)與接合強度(bonding strength)。於一些實施例中，導電層34的厚度小於3 μm，例如，介於0.1-3 μm。
於一些實施例中，導電層34的形成方法包括浸鍍製程(immersion process)或無電極電鍍製程，其中導電層34藉由自對準方法(self-alignment manner)形成於後保護層內連線(PPI)結構28的表面上。於一實施例中，導電層34為包括浸鍍錫層(immersion Sn layer)的單一層結構。於一實施例中，導電層34為三層結構，其包括無電極電鍍鎳(Ni)層、無電極電鍍鉑(Pd)層與浸鍍金(Au)層，其為已知的ENEPIG結構。舉例而言，ENEPIG結構可具有厚度為約0.5 μm的無電極電鍍鎳層、厚度至少為0.02 μm的無電極電鍍鉑(Pd)層、厚度至少為0.01 μm的浸鍍金層。於一實施例中，導電層34為包括無電極電鍍鎳(Ni)層與無電極電鍍鉑(Pd)層的雙層結構，稱為ENEP結構。於一實施例中，導電層34為包括無電極電鍍鎳(Ni)層與浸鍍金層之雙層結構，稱為ENIG結構。
請參見第4圖，第二保護層30接著形成於基板10之上，以覆蓋導電層34。於一些實施例中，第二保護層30延伸至覆蓋住第一保護層26的暴露部份。利用微影製程(photolithography)及/或蝕刻製程(etching processes)圖案化第二保護層30，以形成開口32，開口32暴露出位於後保護層內連線(PPI)結構28的座落墊層區域(landing pad region) 28P中的導電層34的一部份。形成開口32的方法包括微影(lithography)、濕式或乾式蝕刻(wet or dry etching)、雷射鑽孔(laser drill)及/或類似的方法。於一些實施例中，第二保護層30由高分子層所形成，例如環氧樹脂(epoxy)、聚亞醯胺(polyimide)、苯並環丁烯(bis-benzocyclobutenes,BCB)、聚苯噁唑(polybenzoxazole,PBO)或類似之材料，亦可使用其他相對軟的材料，通常是有機材料、介電材料。於一些實施例中，第二保護層30可由非有機材料所組成，例如未摻雜的矽酸鹽玻璃(undoped silicate glass,USG)、氮化矽、氮氧化矽、氧化矽或上述之組合。
如第5圖所示，焊料凸塊36形成於導電層34的暴露區域上，以電性連接到後保護層內連線(PPI)結構28。於一實施例中，焊料凸塊36藉由黏著焊料錫球(solder ball)於開口32中，之後熱回焊(thermal reflowing)焊料錫球。於一些實施例中，焊料凸塊36可包括不含鉛的預焊料層(lead-free pre-solder layer)、錫銀合金(SnAg)或焊料材料，其中焊料材料包括錫(tin)、鉛(lead)、銀(silver)、銅(copper)、鎳(nickel)、鉍(bismuth)或上述組合之合金。於一實施例中，焊料凸塊36具有厚度大於30 μm。於一些實施例中，焊料凸塊36具有厚度範圍為約40-70 μm，雖然厚度可以更大或更小。於一些實施例中，焊料凸塊36可藉由電鍍焊料層搭配微影製程以及隨後的回焊製程所形成。於一些實施例中，焊料凸塊36之直徑為約200-300 μm。於其他實施例中，焊料凸塊36之直徑為約100-200 μm。於又一些實施例中，焊料凸塊36之直徑為約50-100 μm。於再一些實施例中，焊料凸塊36之直徑為約10-50 μm。於一些實施例中，焊料凸塊36包括微凸塊(micro-bumps)。
於一些實施例中，於熱回焊製程期間，導電層34中的錫(Sn)會傾向於和後保護層內連線(PPI)結構28的銅(Cu)形成介金屬化合物層(intermetallic compound,IMC)介於兩者之間。於一實施例中，於介金屬化合物層(intermetallic compound,IMC)形成的期間，導電層34完全被消耗，形成銅錫介金屬化合物層(Cu-Sn IMC layer) 34a於後保護層內連線(PPI)結構28與第二保護層30之間。於一實施例中，導電層34中的錫(Sn)會傾向於和焊料凸塊36中的錫與後保護層內連線(PPI)結構28的銅(Cu)形成另一種介金屬化合物層(intermetallic compound,IMC)介於其間。於一實施例中，於介金屬化合物層(intermetallic compound,IMC)形成的期間，導電層34完全被消耗，形成銅錫介金屬化合物層(Cu-Sn IMC layer) 34b於焊料凸塊36與後保護層內連線(PPI)結構28中的座落墊層區域(landing pad region) 28P中。於一實施例中，銅錫介金屬化合物層(Cu-Sn IMC layer) 34b比銅錫介金屬化合物層(Cu-Sn IMC layer) 34a更厚。依據上述，可完成一具有後保護層內連線(PPI)結構28與焊料凸塊36的半導體元件100。
本發明所提供之導電層34位於後保護層內連線(PPI)結構28，作為抗氧化層膜，可避免銅於製程中氧化。導電層34亦可作為後保護層內連線(PPI)結構28與第二保護層之間的黏著層，其可增加銅層與高分子層之間的介面黏著力，且保護銅層免受濕氣的攻擊，並且可消除高分子層之間的脫層問題，或消除焊料凸塊與高分子層間的脫層問題。導電層34尚可作為焊料凸塊36與後保護層內連線(PPI)結構28中的座落墊層區域(landing pad region) 28P之間的保護層，以避免後保護層內連線(PPI)結構28中的銅擴散到焊料材料中。因此，於封裝製程中，可提高接點可靠度(joint reliability)與降低凸塊疲勞(bump fatigue)。
於凸塊形成之後，舉例而言，可形成封裝材料，可進行切割製程(singulation process)，以切割成單獨的晶粒，以及可進行晶圓級(wafer-level)或晶粒級(die-level)的堆疊或類似的製程。然而，需了解的是，此實施例可應用於許多不同的情況。舉例而言，實施例可應用於晶粒對晶粒(die-to-die)接合結構、晶粒對晶圓(die-to-wafer)接合結構、晶圓對晶圓(wafer-to-wafer)接合結構、晶粒級封裝、晶圓級封裝或類似之結構。
第7圖為覆晶封裝(flip-chip assembly)的實施例之剖面圖。顯示於第6圖之元件100被反轉朝下，並黏著到另一基板200(如第7圖底部)。於一些實施例中，基板200可以是封裝基板，電路板(例如印刷電路板(PCB))、晶圓、晶粒、中介層基板、或其他合適的基板。凸塊結構可藉由各種導電附著接點連接到(coupled)基板200。舉例而言，形成導電區域202於基板200上並加以圖案化。導電區域202可以是導電墊或導線的一部份，其由罩幕層(mask layer)204所呈現。於一實施例中，罩幕層204為焊料阻擋層，其形成於基板200之上並被圖案化，以暴露導電區域202。罩幕層(mask layer) 204具有罩幕開口，其提供焊料接點形成時所需之操作視窗(window)。舉例而言，焊料層包括錫(tin)、鉛(lead)、銀(silver)、銅(copper)、鎳(nickel)、鉍(bismuth)或上述組合之合金，其形成於導電區域202之上。於一些實施例中，元件100可接合至基板200，以形成接點焊料結構206介於導電層34與導電區域202之間。接合製程包括助焊劑應用(flux application)、晶片放置(chip placement)、熔融焊料接點的回焊(reflowing of melting solder joints)及/或助焊劑殘留物的清潔(cleaning of flux reside)。積體電路元件100、接點焊料結構206與其他基板200可稱為封裝結構300，或於其他實施例中稱為覆晶封裝結構。
依據本發明示範的實施例中，半導體元件包括被動層形成於半導體基板之上，內連線層形成於被動層之上以及被圖案化形成線區域與座落墊層區域(landing pad region)，包括錫的導電層形成於內連線層的表面上，保護層形成於導電層之上且具有開口，以暴露位於座落墊層區域(landing pad region)上的一部份導電層，以及焊料凸塊(solder bump)形成於保護層之開口中以電性連接到導電層。於一實施例中，導電層包括介金屬化合物層(IMC layer)。於一實施例中，介金屬化合物層(IMC layer)包括銅與錫。於一實施例中，導電層包括第一介金屬化合物層(IMC layer)於內連線層的線區域上，以及第二介金屬化合物層(IMC layer)於座落墊層區域(landing pad region)上。於一實施例中，第二介金屬化合物層(IMC layer)厚於第一介金屬化合物層(IMC layer)。於一些實施例中，保護層包括高分子層，內連線層包括銅層與銅合金層。於其他實施例中，其他保護層形成於內連線層與保護層之間，且保護層包括高分子層。
依據本發明另一示範的實施例中，封裝結構包括半導體元件藉由焊料結構電性連接到基板。半導體元件包括後保護層內連線(post-passivation interconnect(PPI))結構，後保護層內連線結構包括一連線區域與一座落墊層區域(landing pad region)；介金屬化合物層(intermetallic compound(IMC) layer)形成於後保護層內連線(PPI)結構之該連線區域與該座落墊層區域(landing pad region)之上；以及保護層形成於介金屬化合物層(IMC layer)之上，且該保護層於後保護層內連線(PPI)結構之座落墊層區域(landing pad region)之上暴露介金屬化合物層之一部份。介金屬化合物層(IMC layer)包括錫與銅，且焊料結構形成於介金屬化合物層(IMC layer)之暴露部份。於一實施例中，基板包括導線，與焊料結構形成於介金屬化合物層(IMC layer)與導線之間。於一實施例中，形成於後保護層內連線(PPI)結構之座落墊層區域(landing pad region)上的介金屬化合物層(IMC layer)厚於形成於後保護層內連線結構中的連線區域上的介金屬化合物層(IMC layer)。於一些實施例中，保護層包括高分子層，後保護層內連線(PPI)結構包括銅層或銅合金層。
依據本發明另一示範的實施例中，一種半導體元件之製法包括以下步驟：提供基板；形成保護層於半導體基板之上；形成內連線層於保護層之上，其中內連線層包括一連線區域與一座落墊層區域(landing pad region)；使用一浸鍍製程(immersion process)形成包括錫(Sn)之金屬層於該內連線層之表面上；形成一保護層於金屬層之上；以及於保護層中形成開口，以暴露位於內連線層之座落墊層區域(landing pad region)之上的金屬層之一部份。於一實施例中，方法尚包括形成焊料凸塊形成於保護層之開口中；以及對焊料凸塊進行一熱回焊製程(thermally reflowing process)。於一實施例中，方法尚包括形成包括錫與銅之介金屬化合物層(IMC layer)介於內連線層與保護層之間。於一實施例中，方法尚包括形成包括錫與銅之介金屬化合物層介於內連線層與焊料凸塊之間。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10．．．基板
12．．．電子電路
14．．．層間介電層(inter-layer dielectric(ILD) layer)
16．．．金屬層間介電層(inter-metal dielectric(IMD) layer)
18．．．金屬層
19．．．導通孔
20．．．頂部金屬層
22．．．導電墊
24．．．保護層
26．．．第一保護層
27．．．開口
28．．．後保護層內連線(PPI)結構
28I．．．內連線區域
28P．．．座落墊層區域(landing pad region)
30．．．第二保護層
32．．．開口
34．．．導電層
34a．．．銅錫介金屬化合物層(Cu-Sn IMC layer)
34b．．．銅錫介金屬化合物層(Cu-Sn IMC layer)
36．．．焊料凸塊
100．．．半導體元件
200．．．基板
202．．．導電區域
204．．．罩幕層(mask layer)
206．．．接點焊料結構
300．．．封裝結構
第1~5圖為一系列剖面圖，用以說明本發明製作半導體元件之製程階段。
第6圖為一剖面圖，用以說明本發明具有介金屬化合物層(IMC layer)之後保護層內連線(PPI)結構28。
第7圖為一剖面圖，用以說明本發明實施例之封裝結構。
16．．．金屬層間介電層(inter-metal dielectric(IMD) layer)
20．．．頂部金屬層
22．．．導電墊
24．．．保護層
26．．．第一保護層
28I．．．內連線區域
28P．．．座落墊層區域(landing pad region)
30．．．第二保護層
34．．．導電層
36．．．焊料凸塊

Claims (12)

  1. 一種半導體元件，包括：一半導體基板；一保護層形成於該半導體基板之上；一內連線層形成於該保護層之上，其中該內連線層包括一連線區域與一座落墊層區域(landing pad region)；一導電層形成於該內連線層之表面上，其中該導電層包括錫(Sn)；一保護層形成於該導電層之上，其中該保護層包括位於該座落墊層區域(landing pad region)之上的一開口，且該開口暴露該導電層之一部份；以及一焊料凸塊形成於該保護層之開口中，用以與該導電層電性連接。
  2. 如申請專利範圍第1項所述之半導體元件，其中該導電層包括一介金屬化合物層(intermetallic compound(IMC) layer)。
  3. 如申請專利範圍第2項所述之半導體元件，其中該介金屬化合物層(IMC layer)包括銅與錫。
  4. 如申請專利範圍第2項所述之半導體元件，其中該導電層包括一第一介金屬化合物層與一第二介金屬化合物層，其中該一第一介金屬化合物層於該內連線層之連線區域之上，該第二介金屬化合物層於該座落墊層區域(landing pad region)之上。
  5. 如申請專利範圍第4項所述之半導體元件，其中該二介金屬化合物層厚於該第一介金屬化合物層。
  6. 如申請專利範圍第1項所述之半導體元件，其中該保護層包括一高分子層。
  7. 如申請專利範圍第1項所述之半導體元件，其中該內連線層包括一銅層或一銅合金層。
  8. 一種半導體元件之製法，包括以下步驟：形成一保護層於一半導體基板之上；形成一內連線層於該保護層之上，其中該內連線層包括一連線區域與一座落墊層區域(landing pad region)；使用一浸鍍製程(immersion process)形成一金屬層於該內連線層之表面上，其中該金屬層包括錫(Sn)；形成一保護層於該金屬層之上；以及於該保護層中形成一開口，以暴露位於該內連線層之座落墊層區域(landing pad region)之上的金屬層之一部份。
  9. 如申請專利範圍第8項所述之半導體元件之製法，尚包括形成一焊料凸塊於該保護層之開口中。
  10. 如申請專利範圍第9項所述之半導體元件之製法，尚包括對該焊料凸塊進行一熱回焊製程(thermally reflowing process)。
  11. 如申請專利範圍第8項所述之半導體元件之製法，尚包括形成一介金屬化合物層介於該內連線層與該保護層之間，其中該介金屬化合物層包括錫與銅。
  12. 如申請專利範圍第9項所述之半導體元件之製法，尚包括形成一介金屬化合物層介於該內連線層與該焊料凸塊之間，其中該介金屬化合物層包括錫與銅。
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