CN102005417A - 用于铜柱结构的自对准保护层 - Google Patents

用于铜柱结构的自对准保护层 Download PDF

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Publication number
CN102005417A
CN102005417A CN2010102722165A CN201010272216A CN102005417A CN 102005417 A CN102005417 A CN 102005417A CN 2010102722165 A CN2010102722165 A CN 2010102722165A CN 201010272216 A CN201010272216 A CN 201010272216A CN 102005417 A CN102005417 A CN 102005417A
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layer
post
copper
interconnection line
bond pad
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CN102005417B (zh
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刘重希
余振华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种形成在钝化层中的铜柱，用以与下部的接合焊盘区域电连接，并且延伸以从钝化层中突出。保护层以自对准方式形成在铜柱的侧壁表面和顶表面。保护层是含锰氧化层、含锰氮化层或者含锰氮氧化层。

Description

用于铜柱结构的自对准保护层
相关申请的交叉参考
本申请要求于2009年9月1日提交的美国临时专利申请第61/238,749号的优先权，其全部内容并入本申请作为参考。
技术领域
本发明涉及半导体装置的制造，更具体地来说，涉及半导体装置的凸块结构。
背景技术
现代的集成电路由百万计的有源器件(比如晶体管和电容器)制成。这些器件最初相互独立，但是随后会相互连接以形成功能电路。典型的互连结构包括横向互连(比如金属线(布线))，以及垂直互连(比如导通孔和触点)。互连对于现代集成电路的性能和密度的限制日益明显。在互连结构的顶部，形成有接合焊盘，并且暴露在相关芯片的表面。通过接合焊盘而形成电连接，以将芯片与封装衬底或者其他管芯相连接。接合焊盘可以用于电线接合和倒装芯片(flip-chip)接合。晶圆片级芯片规模封装技术(WLCSP)由于其低成本和相对简单的工艺目前广泛使用。在典型的WLCSP中，互连结构形成在金属化层上，然后形成凸点下金属层(UBM)，以及安装锡球。
倒装芯片封装利用凸块在芯片I/O焊盘和衬底或者封装的引线框架之间建立电连接。从结构上讲，凸块实际上包括了凸块本身，以及位于凸块和I/O焊盘之间的所谓的凸点下金属层(UBM)。UBM一般包括粘附层、阻隔层以及润湿层，并以该顺序排列在I/O焊盘上。根据所使用的材料，凸块本身分为锡凸块、金凸块、铜柱凸块以及混合金属凸块。目前，建议使用铜互连柱技术。取代使用锡凸块，电子部件通过铜柱连接到衬底上。铜互连柱技术将凸块桥连的可能性降到最低达到更细的间距，为电路减小了负载电容，并且使得电路部件能够以更高的频率运行。然而，铜在制造过程期间容易氧化。氧化了的铜柱会使得电子部件在衬底上的附着强度较低。由于较高的漏电流，较低的附着强度会导致严重的可靠性上的忧虑。氧化了的铜柱也会沿着底部填充(填充未满)和铜柱的界面导致底部填充开裂。该裂缝会进一步蔓延到用于接合铜柱到衬底的低k层或者锡。
发明内容
根据本发明的一种半导体装置，包括：
半导体衬底；
所述半导体衬底上的接合焊盘区域；
在所述接合焊盘区域上并与所述接合焊盘区域电连接的含铜柱；以及
所述含铜柱表面上的保护层，其中，所述保护层包括锰(Mn)。
根据本发明的一个实施例的半导体装置，其中，所述保护层是包括锰的氧化层。
根据本发明的一个实施例的半导体装置，其中，所述保护层是包括锰的氮化层。
根据本发明的一个实施例的半导体装置，其中，所述保护层是包括锰的氮氧化层。
根据本发明的一个实施例的半导体装置，其中，所述含铜柱包括顶表面和侧壁表面，其中所述保护层形成在所述含铜柱的侧壁表面上。
根据本发明的一个实施例的半导体装置，其中，所述保护层形成在所述含铜柱的顶表面上。
根据本发明的一个实施例的半导体装置，进一步包括形成在所述含铜柱顶表面的盖层。
根据本发明的一个实施例的半导体装置，其中，所述盖层包括至少锡、银、镍、金中之一或者它们的组合。
根据本发明的一个实施例的半导体装置，进一步包括：
在所述半导体衬底上并且将所述接合焊盘区域的一部分暴露出来的钝化层，其中，
所述含铜柱形成在所述钝化层中并且在所述接合焊盘区域的暴露部分之上，以及
延伸所述含铜柱以从所述钝化层突出；以及
形成在接合焊盘区域和含铜柱之间的凸点下金属(UBM)层。
根据本发明的半导体装置，进一步包括：
在所述半导体衬底上并且将所述接合焊盘区域的一部分暴露出来的钝化层；
形成在所述钝化层并且所述接合焊盘区域的暴露部分之上的互连线，其中所述互连线与所述接合焊盘区域电连接；
形成在所述互连线之上并暴露所述接合焊盘区域的一部分的聚合物层，其中
所述含铜柱形成在所述聚合物层中并且延伸以从所述聚合物层中突出，以及
所述含铜柱形成在所述互连线的暴露部分之上并与所述互连线的暴露部分电连接；以及
形成在所述互连线和所述含铜柱之间的凸点下金属(UBM)层。
根据本发明的一个实施例的半导体装置，进一步包括形成在所述聚合物层和所述互连线之间的介电层，以及形成在所述聚合物层和所述钝化层之间的介电层，。
根据本发明的一个实施例的半导体装置，其中，所述介电层包括氮化硅层。
根据本发明的一个实施例的半导体装置，其中，所述互连线包括铜。
根据本发明的一个实施例的半导体装置，其中，所述聚合物层包括聚酰亚胺。
根据本发明的一个实施例的半导体装置，进一步包括形成在所述钝化层和所述互连线之间的粘附层。
根据本发明的一个实施例的半导体装置，其中所述粘合层包括至少钛、铜之一或者它们的组合。
根据本发明的一种半导体装置，包括：
半导体衬底；
在所述半导体衬底上的导电区域；
在所述半导体衬底上的钝化层，具有暴露部分所述导电区域的第一开口；
在所述钝化层上并且填充所述第一开口的互连线，所述互连线与所述导电区域电连接；
在所述互连线上的聚合物层，所述聚合物层具有暴露部分所述互连线的第二开口；
在所述第二开口中形成的铜柱，所述铜柱与所述互连线电连接，并且从聚合物层突出；以及
在所述铜柱侧壁表面上形成的保护层，其中，所述保护层包括含锰氧化层、含锰氮化层或者含锰氮氧化层。
根据本发明的一个实施例的半导体装置，进一步包括在所述铜柱顶表面上的盖层。
根据本发明的一种半导体装置，包括：
半导体衬底；
在所述半导体衬底上的导电区域；
在所述半导体衬底上的钝化层，具有暴露部分所述导电区域的开口；
在所述开口中形成并且与所述导电区域电连接的铜柱，并且所述铜柱从所述钝化层中突出；以及
在所述铜柱的侧壁表面上形成的保护层，其中所述保护层包括含锰氧化层、含锰氮化层或者含锰氮氧化层。
根据本发明的一个实施例的半导体装置，进一步包括所述铜柱顶表面上的盖层。
附图说明
通过参考以下优选实施例的详细描述并结合附图，本发明的上述目的、特征和优点会变得显而易见，其中：
图1A到图1G示出了Cu柱工艺的示例性实施例的横断面图。
图2示出了Cu柱结构的示例性实施例的横断面图。
图3A到图3C示出了Cu柱工艺的示例性实施例的横断面图。
图4示出了Cu柱结构的示例性实施例的横断面图。
图5A到图5C示出了Cu柱工艺的示例性实施例的横断面图。
图6示出了Cu柱结构的示例性实施例的横断面图。
图7A到图7C示出了Cu柱工艺的示例性实施例的横断面图。
图8示出了Cu柱结构的示例性实施例的横断面图。
具体实施方式
在以下描述中，阐述了许多特别的详细资料以对于本发明进行完整理解。然而，本领域普通技术人员应该了解，没有这些特别的详细资料，本发明也可以实施。在一些示例中，为人所熟知的结构和工艺都不进行详细描述，以避免给本发明带来不必要的晦涩不清。
参考整个说明书，“一个实施例”或者“一实施例”意味着在实施例中描述特别的特征、结构、或者性能至少包括在一个实施例中。这样，在整个说明书的各个地方出现短语“一个实施例”或者“一实施例”并不一定都指的是同一实施例。而且，该特别的特征、结构、或者性能可以以任一合适的方式合并到一个或者更多实施例中。应该了解，以下附图并没有按尺寸作出；相反，附图仅仅用于示出。
本发明提供了一种由铜互连柱技术形成的新式集成电路结构即其形成方法。在整个说明书中，术语“铜(Cu)柱”指的是形成在焊盘上的铜凸起物，和/或形成在焊盘上的连接层上的含铜凸起物。如整个说明书中所用，术语“铜”包括基本纯的元素铜、包括不可避免的杂质的铜、以及包括少量元素(比如钽、铟、锡、锌、锰、铬、钛、锗、锶、铂、镁、铝或者锆)的铜合金。
在这里，横断面图图1A到图1G示出了Cu柱结构的示例性实施例。
在图1A中，用于构造Cu柱互连的衬底10的示例可以包括用在半导体集成电路制造中的半导体衬底，集成电路可以形成在其中或者其上。将该半导体衬底定义为包括半导体材料的任一结构，包括但不限于，体硅、半导体晶圆、绝缘体上硅(SOI)衬底，或者硅锗衬底。还可以使用其他半导体材料，包括III族元素、IV族元素、和V族元素。这里所使用的集成电路指的是具有多个独立电路部件(比如晶体管、二极管、电阻器、电容器、电感器、以及其他有源的和无源的半导体器件)的电子电路。
衬底10进一步包括叠加在集成电路上的层间介电层和金属化结构。金属化结构中的层间介电层包括低k介电金属、未掺杂硅玻璃(USG)、氮化硅、氮氧化硅、或者其他通常使用的材料。低k介电材料的介电常数(k值)可以小于大约3.9，或者小于大约2.8。金属化结构中的金属线可以由铜或者铜合金形成。本领域普通技术人员了解该金属化层的组成细节。导电区域12是形成在顶层层间介电层的顶部金属化层，如果有必要，顶层层间介电层是导电线的一部分，并且具有通过平坦化工艺(比如化学机械抛光(CMP))处理过的暴露的表面。用于导电区域12的适宜材料可以包括但不限于，例如铜、铝、铜合金、或者其他移动(mobile)导电材料。在一个实施例中，导电区域12是接合焊盘区域12，可以用于接合过程，以将相关芯片上的集成电路连接到外部部件。
图1A还示出了形成在衬底10上的钝化层14，并且进行图案化，以形成开口15，暴露了导电区域12的一部分。在一个实施例中，钝化层14由无机材料形成，该无机材料选自未掺杂硅玻璃(USG)、氮化硅、氮氧化硅、氧化硅、以及上述的组合。在另一实施例中，钝化层14由聚合物层，比如环氧树脂、聚酰亚胺、苯并环丁烯(BCB)、聚苯并恶唑(PBO)等等形成，然而也可以使用其他相对柔软、通常为有机的、电介质材料。
参考图1B，形成粘附层16和种子层18，在钝化层14的部分进行图案化，并且将开口15的侧壁和底部作为衬里。并且，在层16和18上形成并图案化后-钝化互连(PPI)线22，并且填充开口15。粘附层16也称为胶层，形成了单涂层(blanket)，覆盖了钝化层14和开口15的侧壁和底部。该粘附层16可以包括通常使用的阻隔材料，比如钛、氮化钛、钽、氮化钽、以及上述的混合物，并且可以使用物理气相沉积、溅镀等等形成。该粘附层16有助于改进随后形成的铜线在钝化层14上的粘附效果。种子层18在粘附层16上形成单涂层。种子层18的材料包括铜或者铜合金，还可以包括金属，比如银、金、铝、及其组合。种子层18还包括铝或者铝合金。在一个实施例中，种子层18用溅镀形成。在另一实施例中，也可以使用其他通常使用的方法，比如物理气相沉积或者化学镀。为了清晰，在下面的附图中，将种子层18和粘附层16结合为层20示出。
应用掩膜和光刻工艺，将导电材料填充到掩膜的开口中，随后去除掩膜，暴露层20。该导电材料形成在层20上，并且填充开口15作为PPI线22。PPI线22可以包括但不限于，例如铜、铝、铜合金、或者其他移动导电材料。PPI线22可以进一步包括在含铜层的顶部的含镍层(未示出)。PPI形成方法包括镀层、化学镀、溅镀、化学气相沉积法等等。PPI线22将接合焊盘区域12连接到凸块部件。PPI线22也可以用作电源线、重分布线(RDL)、电感器、电容器或者任何无源部件。PPI线22可以具有小于大约30μm的厚度，例如在大约2μm到大约25μm之间。接着，去除包括粘附层16和种子层18的层20的暴露部分。该去除步骤可以包括湿式蚀刻或者干式蚀刻工艺。在一个实施例中，该去除步骤包括使用氨基酸的各向同性湿式蚀刻，其可以是短期的闪光蚀刻。
接下来，在图1C中，介电层24也称为隔离层或者钝化层，形成于钝化层14和PPI线22上。介电层24可以由介电材料形成，比如氮化硅、氮化硅、氢氧化硅或者其他可用材料。形成方法包括电浆增强型化学式气相沉积(PECVD)或者其他普遍使用的CVD方法。接着，聚合物层26通过涂覆、固化、电浆预处理等步骤形成在介电层24上。然后，实施光刻技术和蚀刻工艺(比如干式蚀刻和/或湿式蚀刻制程)，以在聚合物层26和穿过聚合物层26和介电层24的开口27上形成图案，这样使得部分下面的PPI线22暴露出来。聚合物层26，如其名称所表明的那样，优选地由聚合物形成，比如环氧树脂、聚酰亚胺、苯并环丁烯(BCB)、聚苯并恶唑(PBO)等等，然而也可以使用其他相对柔软、通常为有机的、电介质材料。在一个实施例中，聚合物层26是聚酰亚胺层。聚合物层26是柔软的，因此具有减小衬底上固有应力的作用。另外，聚合物层26可以轻易形成几十微米的厚度。
在图1D中，凸点下金属层(UBM)层28的组成物包括扩散阻挡层，并且种子层在所得到的结构上完成。UBM层28形成在聚合物层26和PPI线22的暴露部分上，并且将开口27的侧壁和底部加上衬里。形成扩散阻挡层(也称为胶层)以覆盖开口27的侧壁和底部。该扩散阻挡层可以由氮化钽形成，然而也可以由其他材料形成，比如氮化钛、钽、钛等等。形成方法包括物理气相沉积(PVD)或溅镀。种子层可以是形成在扩散阻挡层上的铜种子层。种子层可以由铜合金形成，该铜合金包括银、铬、镍、锡、金、以及其组合。在一个实施例中，UBM层28是Cu/Ti层。
接着，掩膜层30设置在UBM层28上，并且图案化成用开口32暴露UBM层28用于形成凸块的部分。开口32在开口27的上方。在一个具体实施方式中，开口32的直径大于或等于开口27的直径。掩膜层30可以是干膜或者光刻胶膜。
参考图1E，用Cu合金层34填充开口32。形成方法可以包括溅镀、印刷、电镀、化学镀、以及普遍应用的化学气相沉积(CVD)方法。例如，实施电化学电镀(ECP)以形成Cu合金层34。在一个实施例中，Cu合金34是铜-锰(CuMn)层。CuMn层中包括的锰(Mn)与铜的比率没有限制。在一个实施例中，可以利用Ti、Al、Nb、Cr、V、Y、Tc、Re等等作为金属添加剂用于形成Cu合金层34。
接着，如图1F所示，去除掩膜层30。在掩膜层30是干膜的情况下，可以使用碱性溶液对其进行去除。如果掩膜层30由光刻胶形成，可以使用丙酮、N-甲基吡咯烷酮(NMP)、二甲亚砜(DMSO)、氨基氧基乙醇等等去除。然后，对UBM层28的暴露部分进行蚀刻，以将下面的聚合物层26暴露在Cu合金层34的范围之外。在一个示例性实施例中，去除UBM层28的步骤是干式蚀刻或者湿式蚀刻。比如，使用利用氨基酸进行的各向同性湿式蚀刻(由于持续期间短通常称作闪电蚀刻)。这样，Cu合金层34从聚合物层26中突出出来。
此后，在图1G中，使用退火工艺36，存在于Cu合金层34中的Mn扩散到Cu合金层34之外，这样，具有较小Mn的Cu合金层34就成了Cu柱34a。铜柱34a含有的Mn与铜的比率比铜合金34中含有的Mn与铜的比率的要小。并且，扩散出的Mn与退火环境起反应，从而以自对准方式在Cu柱34a的表面形成保护层38。保护层38可以形成在Cu柱34a的顶表面34t和侧壁表面34s上。在一个实施例中，在NH3或者N2/H2环境中所进行的退火工艺期间，Mn会与氮反应，从而以自对准方式在Cu柱34a的表面上形成氮化锰(MnNx)层作为保护层38。可替换地，在退火工艺36期间，Cu柱34a表面上的氧化铜层(CuOx)减少，形成氧化锰层，比如MnOx或者MnOx，Ny，从而以自对准方式在Cu柱34a的表面上形成保护层38。该保护层38可以减小电阻并且防止铜扩散，以增强后道互连(BEOL)的实施。而且，保护层可以改进通过ECP方法形成的Cu柱34a和通过PVD方法形成的下面的Cu层之间的粘附，这样，可以抑制Cu剥离问题。进一步，以自对准方式形成的保护层38可以防止在邻近开口底部的介电层中出现的开口，这样就解决了连接问题。这些都可以改进封装性能。
这样，衬底10可以被截断并利用安装在封装衬底或者其他晶片上的焊盘上的锡球或者Cu柱封装(sawed and packaged)在封装衬底或者另一晶片上。
图1F示出了一个形成在PPI线22上面的带有保护层38的Cu柱34a示例性实施例的横截面图，其中，PPI线22电连接到接合焊盘区域12。图2示出了一个带有保护层38的Cu柱34a示例性实施例的横截面图，其中，Cu柱在接合焊盘区域12上面并且与其电连接，同时，将忽略对与图1G中相同或者相似部分的解释。如图2所示，UBM层28形成在钝化层14中开口15的侧壁和底部，并且Cu柱34a形成在UBM层28上，以填充开口15并且从钝化层14中突出出来。保护层38以自对准方式形成在Cu柱34a的顶表面和侧壁表面。这样，Cu柱34a和UBM层28就直接形成在接合焊盘区域12上。
图3A到图3C示出了带有盖层的Cu柱结构的一个示例性实施例，同时，将忽略对与图1A到1G中相同或者相似部分的解释。
参考图3A，在掩膜层30的开口32中形成Cu合金层34之后，盖层40沉淀在开口32中的Cu合金层34之上。盖层40可以充当阻隔层以阻止Cu柱34a中的铜扩散到接合材料(比如锡球)中。接合材料用于将衬底10接合到外部部件。对于铜扩散的阻止增加了封装的可靠性和接合强度。盖层40可以包括镍、锡、锡铅(SnPb)、金(Au)、银、钯(Pd)、铟、镍钯金(NiPdAu)、其他类似材料或者合金。在一个实施例中，盖层40是无铅的预焊层，例如，SnAg。在另一实施例中，盖层40是焊锡材料，包括锡、铅、银、铜、镍、铋的合金，或其组合。在其他实施例中，盖层40是镍层、Au层、或者NiAu层。如图3B所示，在去除掩膜层30和没有覆盖层34的UBM层28之后，实施退火过程36，从而以自对准方式在Cu柱34a的侧壁表面34t上形成保护层38。保护层38可以是氮化锰(MnNx)层、或者氧化锰层，比如MnOx或者MnOx，Ny。
图4示出带有表面保护层38和盖层40的Cu柱34a的示例性实施例，该盖层40处于接合焊盘区域12上并与其电连接。UBM层28形成在钝化层14中的开口15的侧壁和底部上，并且在UBM层28上形成Cu柱34a，以填充开口15，并且从钝化层14中突出出来。保护层38以自对准方式形成在Cu柱34a的侧壁表面。盖层40形成在Cu柱34a的顶部。这样，Cu柱34a和UBM层28直接形成在接合焊盘区域12上。
图5A到图5C示出了Cu柱结构的示例性实施例的横截面图，同时，将忽略对与图1A到图1G中相同或者相似部分的解释。
参考图5A，在如图1C所示在聚合物层26中形成开口27之后，凸点下金属层(UBM)层28a包括了形成在所得到的结构上的扩散阻挡层。UBM层28a形成在聚合物层26上和PPI线22的暴露部分，并且将开口27的侧壁和底部加上衬里。扩散阻挡层(也称为胶层)可以由氮化钽形成，然而也可以由其他材料形成，比如氮化钛、钽、钛等等。在一个实施例中，UBM层28a是Ti层。
接下来，Cu合金薄膜29沉积在UBM层28a上，给开口27的侧壁和底部加上衬里。形成方法可以包括溅镀、印刷、电镀、化学镀、以及普遍应用的化学气相沉积(CVD)方法。在一个实施例中，Cu合金薄膜29是铜-锰(CuMn)层。CuMn层中包括的锰(Mn)与铜的比率没有限制。在其他实施例中，可以利用Ti、Al、Nb、Cr、V、Y、Tc、Re等等作为形成Cu合金层29的金属添加剂。例如，可以考虑通过物理方法(比如类似PVD(物理气相沉积)的溅镀)，形成具有上述Mn梯度浓度的Cu合金薄膜29。
此后，具有开口32的掩膜层30设置在Cu合金薄膜29上，并且接着实施铜沉积过程(例如电化学电镀(ECP))，以在Cu合金薄膜29上形成Cu层42，并且填充开口32。这样，下面的接合焊盘区域12可以与Cu层42电连接。Cu层42包括基本纯的铜元素、包括不可避免的杂质的铜、以及包括少量元素如钽、铟、锡、锌、锰、铬、钛、锗、锶、铂、镁、铝或者锆的铜合金。在图5B中，去除掩膜层30，以使得Cu层42从聚合物层26中突出出来，以变成Cu柱42a。接着，蚀刻Cu合金薄膜29和UBM层28a的暴露部分，以将下部的聚合物层26暴露出来。
在图5C中，使用退火过程36，Cu合金薄膜29中存在的Mn扩散出来，以减小Cu合金薄膜29中Mn与Cu的比率。并且，扩散出来的Mn与退火环境反应，从而在Cu柱42a的表面以自对准方式形成保护层38。在一个实施例中，铜柱42a下的UBM层在子对准保护形成后变成包括扩散阻挡层28a和铜层的UBM层28b。在另一个实施例中，Mn可以保留在UBM层28b中。
保护层38可以形成在Cu柱42a的顶表面42t和侧壁表面42s上。在一个实施例中，用NM3或者N2/H2环境进行退火工艺期间，Mn会与氮进行反应，从而以自对准方式在Cu柱42a的表面形成氮化锰(MnNx)层作为保护层38。可替换地，在退火工艺36期间，Cu柱42a的表面上氧化铜层(CuOx)减少，形成氧化锰层，比如MnOx或者MnOxNy，从而以自对准方式在Cu柱34a的表面上形成保护层38。该保护层38可以减小电阻，并且防止铜扩散，以增强BEOL SPICE的实施。而且，保护层可以改进通过ECP方法形成的Cu柱34a和通过PVD方法形成的下面的Cu层之间的粘附，这样，可以抑制Cu剥离问题。进一步，以自对准方式形成的保护层38可以防止在邻近开口底部的介电层中的出现开口，因此解决了连接问题。这些都可以改进封装性能。
图6示出了具有表面保护层38的Cu柱42a的示例性实施例的横截面图，其中，该Cu柱42a在接合焊盘区域12上面并与其电连接，同时，将忽略对与图5A到图5C中相同或者相似部分的解释。
图7A到图7C示出了具有盖层的Cu柱结构的示例性实施例的横截面图，同时，将忽略对与图5A到图5C中相同或者相似部分的解释。
参考图7A，在掩膜层30的开口32中形成Cu层42之后，将盖层40沉积到开口32中的Cu层42之上。该盖层40可以充当阻隔层以阻止Cu柱42a中的铜扩散到接合材料(比如锡球)中，接合材料用于将衬底10接合到外部部件。对于铜扩散的阻止增加了封装的可靠性和接合强度。盖层40可以包括镍、锡、锡-铅(SnPb)、金(Au)、银、钯(Pd)、铟(In)、镍-钯-金(NiPdAu)、镍-金(NiAu)其他类似材料或者合金。在一个实施例中，盖层40是无铅的预焊层，例如，SnAg。在另一实施例中，盖层40是焊锡材料，包括锡、铅、银、铜、镍、铋或其组合的合金。在其他实施例中，盖层40是镍层、Au层、或者NiAu层。如图7B所示，在去除掩膜层30和暴露出的UBM层28a以及Cu合金薄膜29之后，实施退火过程36，从而以自对准方式在Cu柱42a的侧壁表面42t上形成保护层38。保护层38可以是氮化锰(MnNx)层、或者氧化锰层，比如MnOx或者MnOxNy。
图8示出了具有表面保护层38和盖层40的Cu柱42a的示例性实施例，其中，该Cu柱42a在接合焊盘区域12上面并与其电连接。
在之前的详细描述中，本发明通过参考其特别的示例性实施例而进行了描述。然而，显而易见，在不偏离在权利要求中所述的本发明的普遍精神和范围的情况下，可以做出各种修改、结构、工艺和改变。因此，本说明书和附图应视为解释性的而非限制性的。可以理解，本发明能够使用各种其他混合物和环境，并且本发明能够在这里表达出的发明构思的范围内做出改变和修改。

Claims (10)

1.一种半导体装置，包括：
半导体衬底；
所述半导体衬底上的接合焊盘区域；
在所述接合焊盘区域上并与所述接合焊盘区域电连接的含铜柱；以及
所述含铜柱表面上的保护层，其中，所述保护层包括锰(Mn)。
2.根据权利要求1所述的半导体装置，其中，所述保护层是包括锰的氧化层、氮化层或氮氧化层。
3.根据权利要求1所述的半导体装置，其中，所述含铜柱包括顶表面和侧壁表面，其中所述保护层形成在所述含铜柱的侧壁表面或顶表面上。
4.根据权利要求1所述的半导体装置，进一步包括形成在所述含铜柱顶表面的盖层，其中，所述盖层包括至少锡、银、镍、金中之一或者它们的组合。
5.根据权利要求1所述的半导体装置，进一步包括：
在所述半导体衬底上并且将所述接合焊盘区域的一部分暴露出来的钝化层，其中，
所述含铜柱形成在所述钝化层中并且在所述接合焊盘区域的暴露部分之上，以及
延伸所述含铜柱以从所述钝化层突出；以及
形成在接合焊盘区域和含铜柱之间的凸点下金属(UBM)层。
6.根据权利要求1所述的半导体装置，进一步包括：
在所述半导体衬底上并且将所述接合焊盘区域的一部分暴露出来的钝化层；
形成在所述钝化层并且所述接合焊盘区域的暴露部分之上的互连线，其中所述互连线与所述接合焊盘区域电连接；
形成在所述互连线之上并暴露所述接合焊盘区域的一部分的聚合物层，其中
所述含铜柱形成在所述聚合物层中并且延伸以从所述聚合物层中突出，以及
所述含铜柱形成在所述互连线的暴露部分之上并与所述互连线的暴露部分电连接；以及
形成在所述互连线和所述含铜柱之间的凸点下金属(UBM)层。
7.根据权利要求6所述的半导体装置，进一步包括形成在所述聚合物层和所述互连线之间的介电层，以及形成在所述聚合物层和所述钝化层之间的介电层，其中，所述介电层包括氮化硅层，所述互连线包括铜，所述聚合物层包括聚酰亚胺。
8.根据权利要求6所述的半导体装置，进一步包括形成在所述钝化层和所述互连线之间的粘附层，其中所述粘合层包括至少钛、铜之一或者它们的组合。
9.一种半导体装置，包括：
半导体衬底；
在所述半导体衬底上的导电区域；
在所述半导体衬底上的钝化层，具有暴露部分所述导电区域的第一开口；
在所述钝化层上并且填充所述第一开口的互连线，所述互连线与所述导电区域电连接；
在所述互连线上的聚合物层，所述聚合物层具有暴露部分所述互连线的第二开口；
在所述第二开口中形成的铜柱，所述铜柱与所述互连线电连接，并且从聚合物层突出；以及
在所述铜柱侧壁表面上形成的保护层，其中，所述保护层包括含锰氧化层、含锰氮化层或者含锰氮氧化层；
在所述铜柱顶表面上形成盖层。
10.一种半导体装置，包括：
半导体衬底；
在所述半导体衬底上的导电区域；
在所述半导体衬底上的钝化层，具有暴露部分所述导电区域的开口；
在所述开口中形成并且与所述导电区域电连接的铜柱，并且所述铜柱从所述钝化层中突出；以及
在所述铜柱的侧壁表面上形成的保护层，其中所述保护层包括含锰氧化层、含锰氮化层或者含锰氮氧化层；
所述铜柱顶表面上形成盖层。
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